emit_x86.c 19 KB

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  1. /*
  2. * Basic macros to emit x86 instructions and some utils
  3. * Copyright (C) 2008,2009,2010 notaz
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. *
  8. * note:
  9. * temp registers must be eax-edx due to use of SETcc and r/w 8/16.
  10. * note about silly things like emith_eor_r_r_r:
  11. * these are here because the compiler was designed
  12. * for ARM as it's primary target.
  13. */
  14. #include <stdarg.h>
  15. enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
  16. #define CONTEXT_REG xBP
  17. #define RET_REG xAX
  18. #define ICOND_JO 0x00
  19. #define ICOND_JNO 0x01
  20. #define ICOND_JB 0x02
  21. #define ICOND_JAE 0x03
  22. #define ICOND_JE 0x04
  23. #define ICOND_JNE 0x05
  24. #define ICOND_JBE 0x06
  25. #define ICOND_JA 0x07
  26. #define ICOND_JS 0x08
  27. #define ICOND_JNS 0x09
  28. #define ICOND_JL 0x0c
  29. #define ICOND_JGE 0x0d
  30. #define ICOND_JLE 0x0e
  31. #define ICOND_JG 0x0f
  32. #define IOP_JMP 0xeb
  33. // unified conditions (we just use rel8 jump instructions for x86)
  34. #define DCOND_EQ ICOND_JE
  35. #define DCOND_NE ICOND_JNE
  36. #define DCOND_MI ICOND_JS // MInus
  37. #define DCOND_PL ICOND_JNS // PLus or zero
  38. #define DCOND_HI ICOND_JA // higher (unsigned)
  39. #define DCOND_HS ICOND_JAE // higher || same (unsigned)
  40. #define DCOND_LO ICOND_JB // lower (unsigned)
  41. #define DCOND_LS ICOND_JBE // lower || same (unsigned)
  42. #define DCOND_GE ICOND_JGE // greater || equal (signed)
  43. #define DCOND_GT ICOND_JG // greater (signed)
  44. #define DCOND_LE ICOND_JLE // less || equal (signed)
  45. #define DCOND_LT ICOND_JL // less (signed)
  46. #define DCOND_VS ICOND_JO // oVerflow Set
  47. #define DCOND_VC ICOND_JNO // oVerflow Clear
  48. #define EMIT_PTR(ptr, val, type) \
  49. *(type *)(ptr) = val
  50. #define EMIT(val, type) do { \
  51. EMIT_PTR(tcache_ptr, val, type); \
  52. tcache_ptr += sizeof(type); \
  53. } while (0)
  54. #define EMIT_OP(op) do { \
  55. COUNT_OP; \
  56. EMIT(op, u8); \
  57. } while (0)
  58. #define EMIT_MODRM(mod,r,rm) \
  59. EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)
  60. #define EMIT_SIB(scale,index,base) \
  61. EMIT(((scale)<<6) | ((index)<<3) | (base), u8)
  62. #define EMIT_REX(w,r,x,b) \
  63. EMIT(0x40 | ((w)<<3) | ((r)<<2) | ((x)<<1) | (b), u8)
  64. #define EMIT_OP_MODRM(op,mod,r,rm) do { \
  65. EMIT_OP(op); \
  66. EMIT_MODRM(mod, r, rm); \
  67. } while (0)
  68. #define JMP8_POS(ptr) \
  69. ptr = tcache_ptr; \
  70. tcache_ptr += 2
  71. #define JMP8_EMIT(op, ptr) \
  72. EMIT_PTR(ptr, 0x70|(op), u8); \
  73. EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
  74. #define JMP8_EMIT_NC(ptr) \
  75. EMIT_PTR(ptr, IOP_JMP, u8); \
  76. EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
  77. // _r_r
  78. #define emith_move_r_r(dst, src) \
  79. EMIT_OP_MODRM(0x8b, 3, dst, src)
  80. #define emith_move_r_r_ptr(dst, src) do { \
  81. EMIT_REX_FOR_PTR(); \
  82. EMIT_OP_MODRM(0x8b, 3, dst, src); \
  83. } while (0)
  84. #define emith_add_r_r(d, s) \
  85. EMIT_OP_MODRM(0x01, 3, s, d)
  86. #define emith_sub_r_r(d, s) \
  87. EMIT_OP_MODRM(0x29, 3, s, d)
  88. #define emith_adc_r_r(d, s) \
  89. EMIT_OP_MODRM(0x11, 3, s, d)
  90. #define emith_sbc_r_r(d, s) \
  91. EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */
  92. #define emith_or_r_r(d, s) \
  93. EMIT_OP_MODRM(0x09, 3, s, d)
  94. #define emith_and_r_r(d, s) \
  95. EMIT_OP_MODRM(0x21, 3, s, d)
  96. #define emith_eor_r_r(d, s) \
  97. EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */
  98. #define emith_tst_r_r(d, s) \
  99. EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */
  100. #define emith_cmp_r_r(d, s) \
  101. EMIT_OP_MODRM(0x39, 3, s, d)
  102. // fake teq - test equivalence - get_flags(d ^ s)
  103. #define emith_teq_r_r(d, s) do { \
  104. emith_push(d); \
  105. emith_eor_r_r(d, s); \
  106. emith_pop(d); \
  107. } while (0)
  108. #define emith_mvn_r_r(d, s) do { \
  109. if (d != s) \
  110. emith_move_r_r(d, s); \
  111. EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
  112. } while (0)
  113. #define emith_negc_r_r(d, s) do { \
  114. int tmp_ = rcache_get_tmp(); \
  115. emith_move_r_imm(tmp_, 0); \
  116. emith_sbc_r_r(tmp_, s); \
  117. emith_move_r_r(d, tmp_); \
  118. rcache_free_tmp(tmp_); \
  119. } while (0)
  120. #define emith_neg_r_r(d, s) do { \
  121. if (d != s) \
  122. emith_move_r_r(d, s); \
  123. EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
  124. } while (0)
  125. // _r_r_r
  126. #define emith_add_r_r_r(d, s1, s2) do { \
  127. if (d == s1) { \
  128. emith_add_r_r(d, s2); \
  129. } else if (d == s2) { \
  130. emith_add_r_r(d, s1); \
  131. } else { \
  132. emith_move_r_r(d, s1); \
  133. emith_add_r_r(d, s2); \
  134. } \
  135. } while (0)
  136. #define emith_eor_r_r_r(d, s1, s2) do { \
  137. if (d == s1) { \
  138. emith_eor_r_r(d, s2); \
  139. } else if (d == s2) { \
  140. emith_eor_r_r(d, s1); \
  141. } else { \
  142. emith_move_r_r(d, s1); \
  143. emith_eor_r_r(d, s2); \
  144. } \
  145. } while (0)
  146. // _r_r_shift
  147. #define emith_or_r_r_lsl(d, s, lslimm) do { \
  148. int tmp_ = rcache_get_tmp(); \
  149. emith_lsl(tmp_, s, lslimm); \
  150. emith_or_r_r(d, tmp_); \
  151. rcache_free_tmp(tmp_); \
  152. } while (0)
  153. // d != s
  154. #define emith_eor_r_r_lsr(d, s, lsrimm) do { \
  155. emith_push(s); \
  156. emith_lsr(s, s, lsrimm); \
  157. emith_eor_r_r(d, s); \
  158. emith_pop(s); \
  159. } while (0)
  160. // _r_imm
  161. #define emith_move_r_imm(r, imm) do { \
  162. EMIT_OP(0xb8 + (r)); \
  163. EMIT(imm, u32); \
  164. } while (0)
  165. #define emith_move_r_imm_s8(r, imm) \
  166. emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))
  167. #define emith_arith_r_imm(op, r, imm) do { \
  168. EMIT_OP_MODRM(0x81, 3, op, r); \
  169. EMIT(imm, u32); \
  170. } while (0)
  171. #define emith_add_r_imm(r, imm) \
  172. emith_arith_r_imm(0, r, imm)
  173. #define emith_or_r_imm(r, imm) \
  174. emith_arith_r_imm(1, r, imm)
  175. #define emith_adc_r_imm(r, imm) \
  176. emith_arith_r_imm(2, r, imm)
  177. #define emith_sbc_r_imm(r, imm) \
  178. emith_arith_r_imm(3, r, imm) // sbb
  179. #define emith_and_r_imm(r, imm) \
  180. emith_arith_r_imm(4, r, imm)
  181. /* used for sub cycles after test, so retain flags with lea */
  182. #define emith_sub_r_imm(r, imm) do { \
  183. assert(r != xSP); \
  184. EMIT_OP_MODRM(0x8d, 2, r, r); \
  185. EMIT(-(s32)(imm), s32); \
  186. } while (0)
  187. #define emith_subf_r_imm(r, imm) \
  188. emith_arith_r_imm(5, r, imm)
  189. #define emith_eor_r_imm(r, imm) \
  190. emith_arith_r_imm(6, r, imm)
  191. #define emith_cmp_r_imm(r, imm) \
  192. emith_arith_r_imm(7, r, imm)
  193. #define emith_tst_r_imm(r, imm) do { \
  194. EMIT_OP_MODRM(0xf7, 3, 0, r); \
  195. EMIT(imm, u32); \
  196. } while (0)
  197. // fake
  198. #define emith_bic_r_imm(r, imm) \
  199. emith_arith_r_imm(4, r, ~(imm))
  200. // fake conditionals (using SJMP instead)
  201. #define emith_move_r_imm_c(cond, r, imm) do { \
  202. (void)(cond); \
  203. emith_move_r_imm(r, imm); \
  204. } while (0)
  205. #define emith_add_r_imm_c(cond, r, imm) do { \
  206. (void)(cond); \
  207. emith_add_r_imm(r, imm); \
  208. } while (0)
  209. #define emith_sub_r_imm_c(cond, r, imm) do { \
  210. (void)(cond); \
  211. emith_sub_r_imm(r, imm); \
  212. } while (0)
  213. #define emith_or_r_imm_c(cond, r, imm) \
  214. emith_or_r_imm(r, imm)
  215. #define emith_eor_r_imm_c(cond, r, imm) \
  216. emith_eor_r_imm(r, imm)
  217. #define emith_bic_r_imm_c(cond, r, imm) \
  218. emith_bic_r_imm(r, imm)
  219. #define emith_ror_c(cond, d, s, cnt) \
  220. emith_ror(d, s, cnt)
  221. #define emith_read_r_r_offs_c(cond, r, rs, offs) \
  222. emith_read_r_r_offs(r, rs, offs)
  223. #define emith_write_r_r_offs_c(cond, r, rs, offs) \
  224. emith_write_r_r_offs(r, rs, offs)
  225. #define emith_read8_r_r_offs_c(cond, r, rs, offs) \
  226. emith_read8_r_r_offs(r, rs, offs)
  227. #define emith_write8_r_r_offs_c(cond, r, rs, offs) \
  228. emith_write8_r_r_offs(r, rs, offs)
  229. #define emith_read16_r_r_offs_c(cond, r, rs, offs) \
  230. emith_read16_r_r_offs(r, rs, offs)
  231. #define emith_write16_r_r_offs_c(cond, r, rs, offs) \
  232. emith_write16_r_r_offs(r, rs, offs)
  233. #define emith_jump_reg_c(cond, r) \
  234. emith_jump_reg(r)
  235. #define emith_jump_ctx_c(cond, offs) \
  236. emith_jump_ctx(offs)
  237. #define emith_ret_c(cond) \
  238. emith_ret()
  239. // _r_r_imm - use lea
  240. #define emith_add_r_r_imm(d, s, imm) do { \
  241. assert(s != xSP); \
  242. EMIT_OP_MODRM(0x8d, 2, d, s); /* lea */ \
  243. EMIT(imm, s32); \
  244. } while (0)
  245. #define emith_add_r_r_ptr_imm(d, s, imm) do { \
  246. if (s != xSP) { \
  247. EMIT_REX_FOR_PTR(); \
  248. EMIT_OP_MODRM(0x8d, 2, d, s); /* lea */ \
  249. } \
  250. else { \
  251. if (d != s) \
  252. emith_move_r_r_ptr(d, s); \
  253. EMIT_REX_FOR_PTR(); \
  254. EMIT_OP_MODRM(0x81, 3, 0, d); /* add */ \
  255. } \
  256. EMIT(imm, s32); \
  257. } while (0)
  258. #define emith_and_r_r_imm(d, s, imm) do { \
  259. if (d != s) \
  260. emith_move_r_r(d, s); \
  261. emith_and_r_imm(d, imm); \
  262. } while (0)
  263. // shift
  264. #define emith_shift(op, d, s, cnt) do { \
  265. if (d != s) \
  266. emith_move_r_r(d, s); \
  267. EMIT_OP_MODRM(0xc1, 3, op, d); \
  268. EMIT(cnt, u8); \
  269. } while (0)
  270. #define emith_lsl(d, s, cnt) \
  271. emith_shift(4, d, s, cnt)
  272. #define emith_lsr(d, s, cnt) \
  273. emith_shift(5, d, s, cnt)
  274. #define emith_asr(d, s, cnt) \
  275. emith_shift(7, d, s, cnt)
  276. #define emith_rol(d, s, cnt) \
  277. emith_shift(0, d, s, cnt)
  278. #define emith_ror(d, s, cnt) \
  279. emith_shift(1, d, s, cnt)
  280. #define emith_rolc(r) \
  281. EMIT_OP_MODRM(0xd1, 3, 2, r)
  282. #define emith_rorc(r) \
  283. EMIT_OP_MODRM(0xd1, 3, 3, r)
  284. // misc
  285. #define emith_push(r) \
  286. EMIT_OP(0x50 + (r))
  287. #define emith_push_imm(imm) do { \
  288. EMIT_OP(0x68); \
  289. EMIT(imm, u32); \
  290. } while (0)
  291. #define emith_pop(r) \
  292. EMIT_OP(0x58 + (r))
  293. #define emith_neg_r(r) \
  294. EMIT_OP_MODRM(0xf7, 3, 3, r)
  295. #define emith_clear_msb(d, s, count) { \
  296. u32 t = (u32)-1; \
  297. t >>= count; \
  298. if (d != s) \
  299. emith_move_r_r(d, s); \
  300. emith_and_r_imm(d, t); \
  301. }
  302. #define emith_clear_msb_c(cond, d, s, count) { \
  303. (void)(cond); \
  304. emith_clear_msb(d, s, count); \
  305. }
  306. #define emith_sext(d, s, bits) { \
  307. emith_lsl(d, s, 32 - (bits)); \
  308. emith_asr(d, d, 32 - (bits)); \
  309. }
  310. #define emith_setc(r) do { \
  311. assert(is_abcdx(r)); \
  312. EMIT_OP(0x0f); \
  313. EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
  314. } while (0)
  315. // XXX: stupid mess
  316. #define emith_mul_(op, dlo, dhi, s1, s2) do { \
  317. int rmr; \
  318. if (dlo != xAX && dhi != xAX) \
  319. emith_push(xAX); \
  320. if (dlo != xDX && dhi != xDX) \
  321. emith_push(xDX); \
  322. if ((s1) == xAX) \
  323. rmr = s2; \
  324. else if ((s2) == xAX) \
  325. rmr = s1; \
  326. else { \
  327. emith_move_r_r(xAX, s1); \
  328. rmr = s2; \
  329. } \
  330. EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
  331. /* XXX: using push/pop for the case of edx->eax; eax->edx */ \
  332. if (dhi != xDX && dhi != -1) \
  333. emith_push(xDX); \
  334. if (dlo != xAX) \
  335. emith_move_r_r(dlo, xAX); \
  336. if (dhi != xDX && dhi != -1) \
  337. emith_pop(dhi); \
  338. if (dlo != xDX && dhi != xDX) \
  339. emith_pop(xDX); \
  340. if (dlo != xAX && dhi != xAX) \
  341. emith_pop(xAX); \
  342. } while (0)
  343. #define emith_mul_u64(dlo, dhi, s1, s2) \
  344. emith_mul_(4, dlo, dhi, s1, s2) /* MUL */
  345. #define emith_mul_s64(dlo, dhi, s1, s2) \
  346. emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */
  347. #define emith_mul(d, s1, s2) \
  348. emith_mul_(4, d, -1, s1, s2)
  349. // (dlo,dhi) += signed(s1) * signed(s2)
  350. #define emith_mula_s64(dlo, dhi, s1, s2) do { \
  351. emith_push(dhi); \
  352. emith_push(dlo); \
  353. emith_mul_(5, dlo, dhi, s1, s2); \
  354. EMIT_OP_MODRM(0x03, 0, dlo, 4); \
  355. EMIT_SIB(0, 4, 4); /* add dlo, [xsp] */ \
  356. EMIT_OP_MODRM(0x13, 1, dhi, 4); \
  357. EMIT_SIB(0, 4, 4); \
  358. EMIT(sizeof(void *), u8); /* adc dhi, [xsp+{4,8}] */ \
  359. emith_add_r_r_ptr_imm(xSP, xSP, sizeof(void *) * 2); \
  360. } while (0)
  361. // "flag" instructions are the same
  362. #define emith_addf_r_r emith_add_r_r
  363. #define emith_subf_r_r emith_sub_r_r
  364. #define emith_adcf_r_r emith_adc_r_r
  365. #define emith_sbcf_r_r emith_sbc_r_r
  366. #define emith_eorf_r_r emith_eor_r_r
  367. #define emith_negcf_r_r emith_negc_r_r
  368. #define emith_lslf emith_lsl
  369. #define emith_lsrf emith_lsr
  370. #define emith_asrf emith_asr
  371. #define emith_rolf emith_rol
  372. #define emith_rorf emith_ror
  373. #define emith_rolcf emith_rolc
  374. #define emith_rorcf emith_rorc
  375. #define emith_deref_op(op, r, rs, offs) do { \
  376. /* mov r <-> [ebp+#offs] */ \
  377. if ((offs) >= 0x80) { \
  378. EMIT_OP_MODRM(op, 2, r, rs); \
  379. EMIT(offs, u32); \
  380. } else { \
  381. EMIT_OP_MODRM(op, 1, r, rs); \
  382. EMIT(offs, u8); \
  383. } \
  384. } while (0)
  385. #define is_abcdx(r) (xAX <= (r) && (r) <= xDX)
  386. #define emith_read_r_r_offs(r, rs, offs) \
  387. emith_deref_op(0x8b, r, rs, offs)
  388. #define emith_write_r_r_offs(r, rs, offs) \
  389. emith_deref_op(0x89, r, rs, offs)
  390. // note: don't use prefixes on this
  391. #define emith_read8_r_r_offs(r, rs, offs) do { \
  392. int r_ = r; \
  393. if (!is_abcdx(r)) \
  394. r_ = rcache_get_tmp(); \
  395. emith_deref_op(0x8a, r_, rs, offs); \
  396. if ((r) != r_) { \
  397. emith_move_r_r(r, r_); \
  398. rcache_free_tmp(r_); \
  399. } \
  400. } while (0)
  401. #define emith_write8_r_r_offs(r, rs, offs) do {\
  402. int r_ = r; \
  403. if (!is_abcdx(r)) { \
  404. r_ = rcache_get_tmp(); \
  405. emith_move_r_r(r_, r); \
  406. } \
  407. emith_deref_op(0x88, r_, rs, offs); \
  408. if ((r) != r_) \
  409. rcache_free_tmp(r_); \
  410. } while (0)
  411. #define emith_read16_r_r_offs(r, rs, offs) do { \
  412. EMIT(0x66, u8); /* operand override */ \
  413. emith_read_r_r_offs(r, rs, offs); \
  414. } while (0)
  415. #define emith_write16_r_r_offs(r, rs, offs) do { \
  416. EMIT(0x66, u8); \
  417. emith_write_r_r_offs(r, rs, offs); \
  418. } while (0)
  419. #define emith_ctx_read(r, offs) \
  420. emith_read_r_r_offs(r, CONTEXT_REG, offs)
  421. #define emith_ctx_read_ptr(r, offs) do { \
  422. EMIT_REX_FOR_PTR(); \
  423. emith_deref_op(0x8b, r, CONTEXT_REG, offs); \
  424. } while (0)
  425. #define emith_ctx_write(r, offs) \
  426. emith_write_r_r_offs(r, CONTEXT_REG, offs)
  427. #define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
  428. int r_ = r, offs_ = offs, cnt_ = cnt; \
  429. for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
  430. emith_ctx_read(r_, offs_); \
  431. } while (0)
  432. #define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
  433. int r_ = r, offs_ = offs, cnt_ = cnt; \
  434. for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
  435. emith_ctx_write(r_, offs_); \
  436. } while (0)
  437. // assumes EBX is free
  438. #define emith_ret_to_ctx(offs) { \
  439. emith_pop(xBX); \
  440. emith_ctx_write(xBX, offs); \
  441. }
  442. #define emith_jump(ptr) { \
  443. u32 disp = (u8 *)(ptr) - ((u8 *)tcache_ptr + 5); \
  444. EMIT_OP(0xe9); \
  445. EMIT(disp, u32); \
  446. }
  447. #define emith_jump_patchable(target) \
  448. emith_jump(target)
  449. #define emith_jump_cond(cond, ptr) do { \
  450. u32 disp = (u8 *)(ptr) - ((u8 *)tcache_ptr + 6); \
  451. EMIT(0x0f, u8); \
  452. EMIT_OP(0x80 | (cond)); \
  453. EMIT(disp, u32); \
  454. } while (0)
  455. #define emith_jump_cond_patchable(cond, target) \
  456. emith_jump_cond(cond, target)
  457. #define emith_jump_patch(ptr, target) do { \
  458. u32 disp_ = (u8 *)(target) - ((u8 *)(ptr) + 4); \
  459. u32 offs_ = (*(u8 *)(ptr) == 0x0f) ? 2 : 1; \
  460. EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
  461. } while (0)
  462. #define emith_jump_at(ptr, target) { \
  463. u32 disp_ = (u8 *)(target) - ((u8 *)(ptr) + 5); \
  464. EMIT_PTR(ptr, 0xe9, u8); \
  465. EMIT_PTR((u8 *)(ptr) + 1, disp_, u32); \
  466. }
  467. #define emith_call(ptr) { \
  468. u32 disp = (u8 *)(ptr) - ((u8 *)tcache_ptr + 5); \
  469. EMIT_OP(0xe8); \
  470. EMIT(disp, u32); \
  471. }
  472. #define emith_call_cond(cond, ptr) \
  473. emith_call(ptr)
  474. #define emith_call_reg(r) \
  475. EMIT_OP_MODRM(0xff, 3, 2, r)
  476. #define emith_call_ctx(offs) do { \
  477. EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
  478. EMIT(offs, u32); \
  479. } while (0)
  480. #define emith_ret() \
  481. EMIT_OP(0xc3)
  482. #define emith_jump_reg(r) \
  483. EMIT_OP_MODRM(0xff, 3, 4, r)
  484. #define emith_jump_ctx(offs) do { \
  485. EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
  486. EMIT(offs, u32); \
  487. } while (0)
  488. #define emith_push_ret()
  489. #define emith_pop_and_ret() \
  490. emith_ret()
  491. #define EMITH_JMP_START(cond) { \
  492. u8 *cond_ptr; \
  493. JMP8_POS(cond_ptr)
  494. #define EMITH_JMP_END(cond) \
  495. JMP8_EMIT(cond, cond_ptr); \
  496. }
  497. #define EMITH_JMP3_START(cond) { \
  498. u8 *cond_ptr, *else_ptr; \
  499. JMP8_POS(cond_ptr)
  500. #define EMITH_JMP3_MID(cond) \
  501. JMP8_POS(else_ptr); \
  502. JMP8_EMIT(cond, cond_ptr);
  503. #define EMITH_JMP3_END() \
  504. JMP8_EMIT_NC(else_ptr); \
  505. }
  506. // "simple" jump (no more then a few insns)
  507. // ARM will use conditional instructions here
  508. #define EMITH_SJMP_DECL_() \
  509. u8 *cond_ptr
  510. #define EMITH_SJMP_START_(cond) \
  511. JMP8_POS(cond_ptr)
  512. #define EMITH_SJMP_END_(cond) \
  513. JMP8_EMIT(cond, cond_ptr)
  514. #define EMITH_SJMP_START EMITH_JMP_START
  515. #define EMITH_SJMP_END EMITH_JMP_END
  516. #define EMITH_SJMP3_START EMITH_JMP3_START
  517. #define EMITH_SJMP3_MID EMITH_JMP3_MID
  518. #define EMITH_SJMP3_END EMITH_JMP3_END
  519. #define emith_pass_arg_r(arg, reg) do { \
  520. int rd = 7; \
  521. host_arg2reg(rd, arg); \
  522. emith_move_r_r_ptr(rd, reg); \
  523. } while (0)
  524. #define emith_pass_arg_imm(arg, imm) do { \
  525. int rd = 7; \
  526. host_arg2reg(rd, arg); \
  527. emith_move_r_imm(rd, imm); \
  528. } while (0)
  529. #define host_instructions_updated(base, end)
  530. #ifdef __x86_64__
  531. #define PTR_SCALE 3
  532. #define NA_TMP_REG xCX // non-arg tmp from reg_temp[]
  533. #define EMIT_REX_FOR_PTR() \
  534. EMIT_REX(1,0,0,0)
  535. #define host_arg2reg(rd, arg) \
  536. switch (arg) { \
  537. case 0: rd = xDI; break; \
  538. case 1: rd = xSI; break; \
  539. case 2: rd = xDX; break; \
  540. }
  541. #define emith_sh2_drc_entry() { \
  542. emith_push(xBX); \
  543. emith_push(xBP); \
  544. emith_push(xSI); /* to align */ \
  545. }
  546. #define emith_sh2_drc_exit() { \
  547. emith_pop(xSI); \
  548. emith_pop(xBP); \
  549. emith_pop(xBX); \
  550. emith_ret(); \
  551. }
  552. #else
  553. #define PTR_SCALE 2
  554. #define NA_TMP_REG xBX // non-arg tmp from reg_temp[]
  555. #define EMIT_REX_FOR_PTR()
  556. #define host_arg2reg(rd, arg) \
  557. switch (arg) { \
  558. case 0: rd = xAX; break; \
  559. case 1: rd = xDX; break; \
  560. case 2: rd = xCX; break; \
  561. }
  562. #define emith_sh2_drc_entry() { \
  563. emith_push(xBX); \
  564. emith_push(xBP); \
  565. emith_push(xSI); \
  566. emith_push(xDI); \
  567. }
  568. #define emith_sh2_drc_exit() { \
  569. emith_pop(xDI); \
  570. emith_pop(xSI); \
  571. emith_pop(xBP); \
  572. emith_pop(xBX); \
  573. emith_ret(); \
  574. }
  575. #endif
  576. #define emith_save_caller_regs(mask) do { \
  577. if ((mask) & (1 << xAX)) emith_push(xAX); \
  578. if ((mask) & (1 << xCX)) emith_push(xCX); \
  579. if ((mask) & (1 << xDX)) emith_push(xDX); \
  580. if ((mask) & (1 << xSI)) emith_push(xSI); \
  581. if ((mask) & (1 << xDI)) emith_push(xDI); \
  582. } while (0)
  583. #define emith_restore_caller_regs(mask) do { \
  584. if ((mask) & (1 << xDI)) emith_pop(xDI); \
  585. if ((mask) & (1 << xSI)) emith_pop(xSI); \
  586. if ((mask) & (1 << xDX)) emith_pop(xDX); \
  587. if ((mask) & (1 << xCX)) emith_pop(xCX); \
  588. if ((mask) & (1 << xAX)) emith_pop(xAX); \
  589. } while (0)
  590. #define emith_sh2_wcall(a, tab) { \
  591. int arg2_; \
  592. host_arg2reg(arg2_, 2); \
  593. emith_lsr(NA_TMP_REG, a, SH2_WRITE_SHIFT); \
  594. EMIT_REX_FOR_PTR(); \
  595. EMIT_OP_MODRM(0x8b, 0, NA_TMP_REG, 4); \
  596. EMIT_SIB(PTR_SCALE, NA_TMP_REG, tab); /* mov tmp, [tab + tmp * {4,8}] */ \
  597. emith_move_r_r_ptr(arg2_, CONTEXT_REG); \
  598. emith_jump_reg(NA_TMP_REG); \
  599. }
  600. #define emith_sh2_dtbf_loop() { \
  601. u8 *jmp0; /* negative cycles check */ \
  602. u8 *jmp1; /* unsinged overflow check */ \
  603. int cr, rn; \
  604. int tmp_ = rcache_get_tmp(); \
  605. cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
  606. rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
  607. emith_sub_r_imm(rn, 1); \
  608. emith_sub_r_imm(cr, (cycles+1) << 12); \
  609. cycles = 0; \
  610. emith_asr(tmp_, cr, 2+12); \
  611. JMP8_POS(jmp0); /* no negative cycles */ \
  612. emith_move_r_imm(tmp_, 0); \
  613. JMP8_EMIT(ICOND_JNS, jmp0); \
  614. emith_and_r_imm(cr, 0xffe); \
  615. emith_subf_r_r(rn, tmp_); \
  616. JMP8_POS(jmp1); /* no overflow */ \
  617. emith_neg_r(rn); /* count left */ \
  618. emith_lsl(rn, rn, 2+12); \
  619. emith_or_r_r(cr, rn); \
  620. emith_or_r_imm(cr, 1); \
  621. emith_move_r_imm(rn, 0); \
  622. JMP8_EMIT(ICOND_JA, jmp1); \
  623. rcache_free_tmp(tmp_); \
  624. }
  625. #define emith_write_sr(sr, srcr) { \
  626. int tmp_ = rcache_get_tmp(); \
  627. emith_clear_msb(tmp_, srcr, 22); \
  628. emith_bic_r_imm(sr, 0x3ff); \
  629. emith_or_r_r(sr, tmp_); \
  630. rcache_free_tmp(tmp_); \
  631. }
  632. #define emith_tpop_carry(sr, is_sub) \
  633. emith_lsr(sr, sr, 1)
  634. #define emith_tpush_carry(sr, is_sub) \
  635. emith_adc_r_r(sr, sr)
  636. /*
  637. * if Q
  638. * t = carry(Rn += Rm)
  639. * else
  640. * t = carry(Rn -= Rm)
  641. * T ^= t
  642. */
  643. #define emith_sh2_div1_step(rn, rm, sr) { \
  644. u8 *jmp0, *jmp1; \
  645. int tmp_ = rcache_get_tmp(); \
  646. emith_eor_r_r(tmp_, tmp_); \
  647. emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
  648. JMP8_POS(jmp0); /* je do_sub */ \
  649. emith_add_r_r(rn, rm); \
  650. JMP8_POS(jmp1); /* jmp done */ \
  651. JMP8_EMIT(ICOND_JE, jmp0); /* do_sub: */ \
  652. emith_sub_r_r(rn, rm); \
  653. JMP8_EMIT_NC(jmp1); /* done: */ \
  654. emith_adc_r_r(tmp_, tmp_); \
  655. emith_eor_r_r(sr, tmp_); \
  656. rcache_free_tmp(tmp_); \
  657. }