eeprom_spi.c 11 KB

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  1. /****************************************************************************
  2. * Genesis Plus
  3. * SPI Serial EEPROM (25xxx/95xxx) support
  4. *
  5. * Copyright (C) 2012 Eke-Eke (Genesis Plus GX)
  6. *
  7. * Redistribution and use of this code or any derivative works are permitted
  8. * provided that the following conditions are met:
  9. *
  10. * - Redistributions may not be sold, nor may they be used in a commercial
  11. * product or activity.
  12. *
  13. * - Redistributions that are modified from the original source must include the
  14. * complete source code, including the source code for all components used by a
  15. * binary built from the modified sources. However, as a special exception, the
  16. * source code distributed need not include anything that is normally distributed
  17. * (in either source or binary form) with the major components (compiler, kernel,
  18. * and so on) of the operating system on which the executable runs, unless that
  19. * component itself accompanies the executable.
  20. *
  21. * - Redistributions must reproduce the above copyright notice, this list of
  22. * conditions and the following disclaimer in the documentation and/or other
  23. * materials provided with the distribution.
  24. *
  25. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  27. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  28. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  29. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35. * POSSIBILITY OF SUCH DAMAGE.
  36. *
  37. ****************************************************************************************/
  38. #include "../pico_int.h"
  39. #include "../cd/genplus_macros.h"
  40. #include "eeprom_spi.h"
  41. /* max supported size 64KB (25x512/95x512) */
  42. #define SIZE_MASK 0xffff
  43. #define PAGE_MASK 0x7f
  44. /* hard-coded board implementation (!WP pin not used) */
  45. #define BIT_DATA (0)
  46. #define BIT_CLK (1)
  47. #define BIT_HOLD (2)
  48. #define BIT_CS (3)
  49. typedef enum
  50. {
  51. STANDBY,
  52. GET_OPCODE,
  53. GET_ADDRESS,
  54. WRITE_BYTE,
  55. READ_BYTE
  56. } T_STATE_SPI;
  57. typedef struct
  58. {
  59. uint8 cs; /* !CS line state */
  60. uint8 clk; /* SCLK line state */
  61. uint8 out; /* SO line state */
  62. uint8 status; /* status register */
  63. uint8 opcode; /* 8-bit opcode */
  64. uint8 buffer; /* 8-bit data buffer */
  65. uint16 addr; /* 16-bit address */
  66. uint32 cycles; /* current operation cycle */
  67. T_STATE_SPI state; /* current operation state */
  68. } T_EEPROM_SPI;
  69. static T_EEPROM_SPI spi_eeprom;
  70. void *eeprom_spi_init(int *size)
  71. {
  72. /* reset eeprom state */
  73. memset(&spi_eeprom, 0, sizeof(T_EEPROM_SPI));
  74. spi_eeprom.out = 1;
  75. spi_eeprom.state = GET_OPCODE;
  76. if (size)
  77. *size = sizeof(T_EEPROM_SPI);
  78. return &spi_eeprom;
  79. }
  80. void eeprom_spi_write(unsigned char data)
  81. {
  82. /* Make sure !HOLD is high */
  83. if (data & (1 << BIT_HOLD))
  84. {
  85. /* Check !CS state */
  86. if (data & (1 << BIT_CS))
  87. {
  88. /* !CS high -> end of current operation */
  89. spi_eeprom.cycles = 0;
  90. spi_eeprom.out = 1;
  91. spi_eeprom.opcode = 0;
  92. spi_eeprom.state = GET_OPCODE;
  93. }
  94. else
  95. {
  96. /* !CS low -> process current operation */
  97. switch (spi_eeprom.state)
  98. {
  99. case GET_OPCODE:
  100. {
  101. /* latch data on CLK positive edge */
  102. if ((data & (1 << BIT_CLK)) && !spi_eeprom.clk)
  103. {
  104. /* 8-bit opcode buffer */
  105. spi_eeprom.opcode |= ((data >> BIT_DATA) & 1);
  106. spi_eeprom.cycles++;
  107. /* last bit ? */
  108. if (spi_eeprom.cycles == 8)
  109. {
  110. /* reset cycles count */
  111. spi_eeprom.cycles = 0;
  112. /* Decode instruction */
  113. switch (spi_eeprom.opcode)
  114. {
  115. case 0x01:
  116. {
  117. /* WRITE STATUS */
  118. spi_eeprom.buffer = 0;
  119. spi_eeprom.state = WRITE_BYTE;
  120. break;
  121. }
  122. case 0x02:
  123. {
  124. /* WRITE BYTE */
  125. spi_eeprom.addr = 0;
  126. spi_eeprom.state = GET_ADDRESS;
  127. break;
  128. }
  129. case 0x03:
  130. {
  131. /* READ BYTE */
  132. spi_eeprom.addr = 0;
  133. spi_eeprom.state = GET_ADDRESS;
  134. break;
  135. }
  136. case 0x04:
  137. {
  138. /* WRITE DISABLE */
  139. spi_eeprom.status &= ~0x02;
  140. spi_eeprom.state = STANDBY;
  141. break;
  142. }
  143. case 0x05:
  144. {
  145. /* READ STATUS */
  146. spi_eeprom.buffer = spi_eeprom.status;
  147. spi_eeprom.state = READ_BYTE;
  148. break;
  149. }
  150. case 0x06:
  151. {
  152. /* WRITE ENABLE */
  153. spi_eeprom.status |= 0x02;
  154. spi_eeprom.state = STANDBY;
  155. break;
  156. }
  157. default:
  158. {
  159. /* specific instructions (not supported) */
  160. spi_eeprom.state = STANDBY;
  161. break;
  162. }
  163. }
  164. }
  165. else
  166. {
  167. /* shift opcode value */
  168. spi_eeprom.opcode = spi_eeprom.opcode << 1;
  169. }
  170. }
  171. break;
  172. }
  173. case GET_ADDRESS:
  174. {
  175. /* latch data on CLK positive edge */
  176. if ((data & (1 << BIT_CLK)) && !spi_eeprom.clk)
  177. {
  178. /* 16-bit address */
  179. spi_eeprom.addr |= ((data >> BIT_DATA) & 1);
  180. spi_eeprom.cycles++;
  181. /* last bit ? */
  182. if (spi_eeprom.cycles == 16)
  183. {
  184. /* reset cycles count */
  185. spi_eeprom.cycles = 0;
  186. /* mask unused address bits */
  187. spi_eeprom.addr &= SIZE_MASK;
  188. /* operation type */
  189. if (spi_eeprom.opcode & 0x01)
  190. {
  191. /* READ operation */
  192. spi_eeprom.buffer = Pico.sv.data[spi_eeprom.addr];
  193. spi_eeprom.state = READ_BYTE;
  194. }
  195. else
  196. {
  197. /* WRITE operation */
  198. spi_eeprom.buffer = 0;
  199. spi_eeprom.state = WRITE_BYTE;
  200. }
  201. }
  202. else
  203. {
  204. /* shift address value */
  205. spi_eeprom.addr = spi_eeprom.addr << 1;
  206. }
  207. }
  208. break;
  209. }
  210. case WRITE_BYTE:
  211. {
  212. /* latch data on CLK positive edge */
  213. if ((data & (1 << BIT_CLK)) && !spi_eeprom.clk)
  214. {
  215. /* 8-bit data buffer */
  216. spi_eeprom.buffer |= ((data >> BIT_DATA) & 1);
  217. spi_eeprom.cycles++;
  218. /* last bit ? */
  219. if (spi_eeprom.cycles == 8)
  220. {
  221. /* reset cycles count */
  222. spi_eeprom.cycles = 0;
  223. /* write data to destination */
  224. if (spi_eeprom.opcode & 0x01)
  225. {
  226. /* update status register */
  227. spi_eeprom.status = (spi_eeprom.status & 0x02) | (spi_eeprom.buffer & 0x0c);
  228. /* wait for operation end */
  229. spi_eeprom.state = STANDBY;
  230. }
  231. else
  232. {
  233. /* Memory Array (write-protected) */
  234. if (spi_eeprom.status & 2)
  235. {
  236. /* check array protection bits (BP0, BP1) */
  237. switch ((spi_eeprom.status >> 2) & 0x03)
  238. {
  239. case 0x01:
  240. {
  241. /* $C000-$FFFF (sector #3) is protected */
  242. if (spi_eeprom.addr < 0xC000)
  243. {
  244. Pico.sv.data[spi_eeprom.addr] = spi_eeprom.buffer;
  245. }
  246. break;
  247. }
  248. case 0x02:
  249. {
  250. /* $8000-$FFFF (sectors #2 and #3) is protected */
  251. if (spi_eeprom.addr < 0x8000)
  252. {
  253. Pico.sv.data[spi_eeprom.addr] = spi_eeprom.buffer;
  254. }
  255. break;
  256. }
  257. case 0x03:
  258. {
  259. /* $0000-$FFFF (all sectors) is protected */
  260. break;
  261. }
  262. default:
  263. {
  264. /* no sectors protected */
  265. Pico.sv.data[spi_eeprom.addr] = spi_eeprom.buffer;
  266. break;
  267. }
  268. }
  269. }
  270. /* reset data buffer */
  271. spi_eeprom.buffer = 0;
  272. /* increase array address (sequential writes are limited within the same page) */
  273. spi_eeprom.addr = (spi_eeprom.addr & ~PAGE_MASK) | ((spi_eeprom.addr + 1) & PAGE_MASK);
  274. }
  275. }
  276. else
  277. {
  278. /* shift data buffer value */
  279. spi_eeprom.buffer = spi_eeprom.buffer << 1;
  280. }
  281. }
  282. break;
  283. }
  284. case READ_BYTE:
  285. {
  286. /* output data on CLK positive edge */
  287. if ((data & (1 << BIT_CLK)) && !spi_eeprom.clk)
  288. {
  289. /* read out bits */
  290. spi_eeprom.out = (spi_eeprom.buffer >> (7 - spi_eeprom.cycles)) & 1;
  291. spi_eeprom.cycles++;
  292. /* last bit ? */
  293. if (spi_eeprom.cycles == 8)
  294. {
  295. /* reset cycles count */
  296. spi_eeprom.cycles = 0;
  297. /* read from memory array ? */
  298. if (spi_eeprom.opcode == 0x03)
  299. {
  300. /* read next array byte */
  301. spi_eeprom.addr = (spi_eeprom.addr + 1) & SIZE_MASK;
  302. spi_eeprom.buffer = Pico.sv.data[spi_eeprom.addr];
  303. }
  304. }
  305. }
  306. break;
  307. }
  308. default:
  309. {
  310. /* wait for !CS low->high transition */
  311. break;
  312. }
  313. }
  314. }
  315. }
  316. /* update input lines */
  317. spi_eeprom.cs = (data >> BIT_CS) & 1;
  318. spi_eeprom.clk = (data >> BIT_CLK) & 1;
  319. }
  320. unsigned int eeprom_spi_read(unsigned int address)
  321. {
  322. return (spi_eeprom.out << BIT_DATA);
  323. }