memory.c 47 KB

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  1. /*
  2. * PicoDrive
  3. * (C) notaz, 2009,2010,2013
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. *
  8. * Register map:
  9. * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
  10. * a15102 ........ ......SM ? 4002 // intS intM
  11. * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
  12. * a15106 ........ F....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
  13. * a15108 (32bit DREQ src) 4008
  14. * a1510c (32bit DREQ dst) 400c
  15. * a15110 llllllll llllll00 4010 // DREQ Len
  16. * a15112 (16bit FIFO reg) 4012
  17. * a15114 0 (16bit VRES clr) 4014
  18. * a15116 0 (16bit Vint clr) 4016
  19. * a15118 0 (16bit Hint clr) 4018
  20. * a1511a .......? .......C (16bit CMD clr) 401a // TV Cm
  21. * a1511c 0 (16bit PWM clr) 401c
  22. * a1511e 0 ? 401e
  23. * a15120 (16 bytes comm) 2020
  24. * a15130 (PWM) 2030
  25. *
  26. * SH2 addr lines:
  27. * iii. .cc. ..xx * // Internal, Cs, x
  28. *
  29. * sh2 map, wait/bus cycles (from docs):
  30. * r w
  31. * rom 0000000-0003fff 1 -
  32. * sys reg 0004000-00040ff 1 1
  33. * vdp reg 0004100-00041ff 5 5
  34. * vdp pal 0004200-00043ff 5 5
  35. * cart 2000000-23fffff 6-15
  36. * dram/fb 4000000-401ffff 5-12 1-3
  37. * fb ovr 4020000-403ffff
  38. * sdram 6000000-603ffff 12 2 (cycles)
  39. * d.a. c0000000-?
  40. */
  41. #include "../pico_int.h"
  42. #include "../memory.h"
  43. #include "../../cpu/sh2/compiler.h"
  44. static const char str_mars[] = "MARS";
  45. void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
  46. struct Pico32xMem *Pico32xMem;
  47. static void bank_switch(int b);
  48. // addressing byte in 16bit reg
  49. #define REG8IN16(ptr, offs) ((u8 *)ptr)[(offs) ^ 1]
  50. // poll detection
  51. #define POLL_THRESHOLD 3
  52. static struct {
  53. u32 addr, cycles;
  54. int cnt;
  55. } m68k_poll;
  56. static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
  57. {
  58. int ret = 0;
  59. if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2
  60. && cycles - m68k_poll.cycles <= 64 && !SekNotPolling)
  61. {
  62. if (m68k_poll.cnt++ > POLL_THRESHOLD) {
  63. if (!(Pico32x.emu_flags & flags)) {
  64. elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
  65. a, cycles - m68k_poll.cycles);
  66. ret = 1;
  67. }
  68. Pico32x.emu_flags |= flags;
  69. }
  70. }
  71. else {
  72. m68k_poll.cnt = 0;
  73. m68k_poll.addr = a;
  74. SekNotPolling = 0;
  75. }
  76. m68k_poll.cycles = cycles;
  77. return ret;
  78. }
  79. void p32x_m68k_poll_event(u32 flags)
  80. {
  81. if (Pico32x.emu_flags & flags) {
  82. elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags,
  83. Pico32x.emu_flags & ~flags);
  84. Pico32x.emu_flags &= ~flags;
  85. SekSetStop(0);
  86. }
  87. m68k_poll.addr = m68k_poll.cnt = 0;
  88. }
  89. static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags, int maxcnt)
  90. {
  91. int cycles_left = sh2_cycles_left(sh2);
  92. if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
  93. if (sh2->poll_cnt++ > maxcnt) {
  94. if (!(sh2->state & flags))
  95. elprintf_sh2(sh2, EL_32X, "state: %02x->%02x",
  96. sh2->state, sh2->state | flags);
  97. sh2->state |= flags;
  98. sh2_end_run(sh2, 1);
  99. pevt_log_sh2(sh2, EVT_POLL_START);
  100. return;
  101. }
  102. }
  103. else
  104. sh2->poll_cnt = 0;
  105. sh2->poll_addr = a;
  106. sh2->poll_cycles = cycles_left;
  107. }
  108. void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
  109. {
  110. if (sh2->state & flags) {
  111. elprintf_sh2(sh2, EL_32X, "state: %02x->%02x", sh2->state,
  112. sh2->state & ~flags);
  113. if (sh2->m68krcycles_done < m68k_cycles)
  114. sh2->m68krcycles_done = m68k_cycles;
  115. pevt_log_sh2_o(sh2, EVT_POLL_END);
  116. }
  117. sh2->state &= ~flags;
  118. sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
  119. }
  120. static void sh2s_sync_on_read(SH2 *sh2)
  121. {
  122. int cycles;
  123. if (sh2->poll_cnt != 0)
  124. return;
  125. cycles = sh2_cycles_done(sh2);
  126. if (cycles > 600)
  127. p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3);
  128. }
  129. // SH2 faking
  130. //#define FAKE_SH2
  131. #ifdef FAKE_SH2
  132. static int p32x_csum_faked;
  133. static const u16 comm_fakevals[] = {
  134. 0x4d5f, 0x4f4b, // M_OK
  135. 0x535f, 0x4f4b, // S_OK
  136. 0x4D41, 0x5346, // MASF - Brutal Unleashed
  137. 0x5331, 0x4d31, // Darxide
  138. 0x5332, 0x4d32,
  139. 0x5333, 0x4d33,
  140. 0x0000, 0x0000, // eq for doom
  141. 0x0002, // Mortal Kombat
  142. // 0, // pad
  143. };
  144. static u32 sh2_comm_faker(u32 a)
  145. {
  146. static int f = 0;
  147. if (a == 0x28 && !p32x_csum_faked) {
  148. p32x_csum_faked = 1;
  149. return *(unsigned short *)(Pico.rom + 0x18e);
  150. }
  151. if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
  152. f = 0;
  153. return comm_fakevals[f++];
  154. }
  155. #endif
  156. // ------------------------------------------------------------------
  157. // 68k regs
  158. static u32 p32x_reg_read16(u32 a)
  159. {
  160. a &= 0x3e;
  161. #if 0
  162. if ((a & 0x30) == 0x20)
  163. return sh2_comm_faker(a);
  164. #else
  165. if ((a & 0x30) == 0x20) {
  166. unsigned int cycles = SekCyclesDone();
  167. int comreg = 1 << (a & 0x0f) / 2;
  168. if (cycles - msh2.m68krcycles_done > 244
  169. || (Pico32x.comm_dirty_68k & comreg))
  170. p32x_sync_sh2s(cycles);
  171. if (Pico32x.comm_dirty_sh2 & comreg)
  172. Pico32x.comm_dirty_sh2 &= ~comreg;
  173. else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
  174. SekSetStop(1);
  175. SekEndRun(16);
  176. }
  177. goto out;
  178. }
  179. #endif
  180. if (a == 2) { // INTM, INTS
  181. unsigned int cycles = SekCyclesDone();
  182. if (cycles - msh2.m68krcycles_done > 64)
  183. p32x_sync_sh2s(cycles);
  184. goto out;
  185. }
  186. if ((a & 0x30) == 0x30)
  187. return p32x_pwm_read16(a, NULL, SekCyclesDone());
  188. out:
  189. return Pico32x.regs[a / 2];
  190. }
  191. static void dreq0_write(u16 *r, u32 d)
  192. {
  193. if (!(r[6 / 2] & P32XS_68S)) {
  194. elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
  195. return; // ignored - tested
  196. }
  197. if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) {
  198. Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d;
  199. if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN)
  200. r[6 / 2] |= P32XS_FULL;
  201. // tested: len register decrements and 68S clears
  202. // even if SH2s/DMAC aren't active..
  203. r[0x10 / 2]--;
  204. if (r[0x10 / 2] == 0)
  205. r[6 / 2] &= ~P32XS_68S;
  206. if ((Pico32x.dmac0_fifo_ptr & 3) == 0) {
  207. p32x_sync_sh2s(SekCyclesDone());
  208. p32x_dreq0_trigger();
  209. }
  210. }
  211. else
  212. elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO overflow!");
  213. }
  214. // writable bits tested
  215. static void p32x_reg_write8(u32 a, u32 d)
  216. {
  217. u16 *r = Pico32x.regs;
  218. a &= 0x3f;
  219. // for things like bset on comm port
  220. m68k_poll.cnt = 0;
  221. switch (a) {
  222. case 0x00: // adapter ctl: FM writable
  223. REG8IN16(r, 0x00) = d & 0x80;
  224. return;
  225. case 0x01: // adapter ctl: RES and ADEN writable
  226. if ((d ^ r[0]) & d & P32XS_nRES)
  227. p32x_reset_sh2s();
  228. REG8IN16(r, 0x01) &= ~(P32XS_nRES|P32XS_ADEN);
  229. REG8IN16(r, 0x01) |= d & (P32XS_nRES|P32XS_ADEN);
  230. return;
  231. case 0x02: // ignored, always 0
  232. return;
  233. case 0x03: // irq ctl
  234. if ((d ^ r[0x02 / 2]) & 3) {
  235. int cycles = SekCyclesDone();
  236. p32x_sync_sh2s(cycles);
  237. r[0x02 / 2] = d & 3;
  238. p32x_update_cmd_irq(NULL, cycles);
  239. }
  240. return;
  241. case 0x04: // ignored, always 0
  242. return;
  243. case 0x05: // bank
  244. d &= 3;
  245. if (r[0x04 / 2] != d) {
  246. r[0x04 / 2] = d;
  247. bank_switch(d);
  248. }
  249. return;
  250. case 0x06: // ignored, always 0
  251. return;
  252. case 0x07: // DREQ ctl
  253. REG8IN16(r, 0x07) &= ~(P32XS_68S|P32XS_DMA|P32XS_RV);
  254. if (!(d & P32XS_68S)) {
  255. Pico32x.dmac0_fifo_ptr = 0;
  256. REG8IN16(r, 0x07) &= ~P32XS_FULL;
  257. }
  258. REG8IN16(r, 0x07) |= d & (P32XS_68S|P32XS_DMA|P32XS_RV);
  259. return;
  260. case 0x08: // ignored, always 0
  261. return;
  262. case 0x09: // DREQ src
  263. REG8IN16(r, 0x09) = d;
  264. return;
  265. case 0x0a:
  266. REG8IN16(r, 0x0a) = d;
  267. return;
  268. case 0x0b:
  269. REG8IN16(r, 0x0b) = d & 0xfe;
  270. return;
  271. case 0x0c: // ignored, always 0
  272. return;
  273. case 0x0d: // DREQ dest
  274. case 0x0e:
  275. case 0x0f:
  276. case 0x10: // DREQ len
  277. REG8IN16(r, a) = d;
  278. return;
  279. case 0x11:
  280. REG8IN16(r, a) = d & 0xfc;
  281. return;
  282. // DREQ FIFO - writes to odd addr go to fifo
  283. // do writes to even work? Reads return 0
  284. case 0x12:
  285. REG8IN16(r, a) = d;
  286. return;
  287. case 0x13:
  288. d = (REG8IN16(r, 0x12) << 8) | (d & 0xff);
  289. REG8IN16(r, 0x12) = 0;
  290. dreq0_write(r, d);
  291. return;
  292. case 0x14: // ignored, always 0
  293. case 0x15:
  294. case 0x16:
  295. case 0x17:
  296. case 0x18:
  297. case 0x19:
  298. return;
  299. case 0x1a: // what's this?
  300. elprintf(EL_32X|EL_ANOMALY, "mystery w8 %02x %02x", a, d);
  301. REG8IN16(r, a) = d & 0x01;
  302. return;
  303. case 0x1b: // TV
  304. REG8IN16(r, a) = d & 0x01;
  305. return;
  306. case 0x1c: // ignored, always 0
  307. case 0x1d:
  308. case 0x1e:
  309. case 0x1f:
  310. case 0x30:
  311. return;
  312. case 0x31: // PWM control
  313. REG8IN16(r, a) &= ~0x0f;
  314. REG8IN16(r, a) |= d & 0x0f;
  315. d = r[0x30 / 2];
  316. goto pwm_write;
  317. case 0x32: // PWM cycle
  318. REG8IN16(r, a) = d & 0x0f;
  319. d = r[0x32 / 2];
  320. goto pwm_write;
  321. case 0x33:
  322. REG8IN16(r, a) = d;
  323. d = r[0x32 / 2];
  324. goto pwm_write;
  325. // PWM pulse regs.. Only writes to odd address send a value
  326. // to FIFO; reads are 0 (except status bits)
  327. case 0x34:
  328. case 0x36:
  329. case 0x38:
  330. REG8IN16(r, a) = d;
  331. return;
  332. case 0x35:
  333. case 0x37:
  334. case 0x39:
  335. d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
  336. REG8IN16(r, a ^ 1) = 0;
  337. goto pwm_write;
  338. case 0x3a: // ignored, always 0
  339. case 0x3b:
  340. case 0x3c:
  341. case 0x3d:
  342. case 0x3e:
  343. case 0x3f:
  344. return;
  345. pwm_write:
  346. p32x_pwm_write16(a & ~1, d, NULL, SekCyclesDone());
  347. return;
  348. }
  349. if ((a & 0x30) == 0x20) {
  350. int cycles = SekCyclesDone();
  351. int comreg;
  352. if (REG8IN16(r, a) == d)
  353. return;
  354. comreg = 1 << (a & 0x0f) / 2;
  355. if (Pico32x.comm_dirty_68k & comreg)
  356. p32x_sync_sh2s(cycles);
  357. REG8IN16(r, a) = d;
  358. p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
  359. p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
  360. Pico32x.comm_dirty_68k |= comreg;
  361. if (cycles - (int)msh2.m68krcycles_done > 120)
  362. p32x_sync_sh2s(cycles);
  363. return;
  364. }
  365. }
  366. static void p32x_reg_write16(u32 a, u32 d)
  367. {
  368. u16 *r = Pico32x.regs;
  369. a &= 0x3e;
  370. // for things like bset on comm port
  371. m68k_poll.cnt = 0;
  372. switch (a) {
  373. case 0x00: // adapter ctl
  374. if ((d ^ r[0]) & d & P32XS_nRES)
  375. p32x_reset_sh2s();
  376. r[0] &= ~(P32XS_FM|P32XS_nRES|P32XS_ADEN);
  377. r[0] |= d & (P32XS_FM|P32XS_nRES|P32XS_ADEN);
  378. return;
  379. case 0x08: // DREQ src
  380. r[a / 2] = d & 0xff;
  381. return;
  382. case 0x0a:
  383. r[a / 2] = d & ~1;
  384. return;
  385. case 0x0c: // DREQ dest
  386. r[a / 2] = d & 0xff;
  387. return;
  388. case 0x0e:
  389. r[a / 2] = d;
  390. return;
  391. case 0x10: // DREQ len
  392. r[a / 2] = d & ~3;
  393. return;
  394. case 0x12: // FIFO reg
  395. dreq0_write(r, d);
  396. return;
  397. case 0x1a: // TV + mystery bit
  398. r[a / 2] = d & 0x0101;
  399. return;
  400. case 0x30: // PWM control
  401. d = (r[a / 2] & ~0x0f) | (d & 0x0f);
  402. r[a / 2] = d;
  403. p32x_pwm_write16(a, d, NULL, SekCyclesDone());
  404. return;
  405. }
  406. // comm port
  407. if ((a & 0x30) == 0x20) {
  408. int cycles = SekCyclesDone();
  409. int comreg;
  410. if (r[a / 2] == d)
  411. return;
  412. comreg = 1 << (a & 0x0f) / 2;
  413. if (Pico32x.comm_dirty_68k & comreg)
  414. p32x_sync_sh2s(cycles);
  415. r[a / 2] = d;
  416. p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
  417. p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
  418. Pico32x.comm_dirty_68k |= comreg;
  419. if (cycles - (int)msh2.m68krcycles_done > 120)
  420. p32x_sync_sh2s(cycles);
  421. return;
  422. }
  423. // PWM
  424. else if ((a & 0x30) == 0x30) {
  425. p32x_pwm_write16(a, d, NULL, SekCyclesDone());
  426. return;
  427. }
  428. p32x_reg_write8(a + 1, d);
  429. }
  430. // ------------------------------------------------------------------
  431. // VDP regs
  432. static u32 p32x_vdp_read16(u32 a)
  433. {
  434. u32 d;
  435. a &= 0x0e;
  436. d = Pico32x.vdp_regs[a / 2];
  437. if (a == 0x0a) {
  438. // tested: FEN seems to be randomly pulsing on hcnt 0x80-0xf0,
  439. // most often at 0xb1-0xb5, even during vblank,
  440. // what's the deal with that?
  441. // we'll just fake it along with hblank for now
  442. Pico32x.vdp_fbcr_fake++;
  443. if (Pico32x.vdp_fbcr_fake & 4)
  444. d |= P32XV_HBLK;
  445. if ((Pico32x.vdp_fbcr_fake & 7) == 0)
  446. d |= P32XV_nFEN;
  447. }
  448. return d;
  449. }
  450. static void p32x_vdp_write8(u32 a, u32 d)
  451. {
  452. u16 *r = Pico32x.vdp_regs;
  453. a &= 0x0f;
  454. // TODO: verify what's writeable
  455. switch (a) {
  456. case 0x01:
  457. // priority inversion is handled in palette
  458. if ((r[0] ^ d) & P32XV_PRI)
  459. Pico32x.dirty_pal = 1;
  460. r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
  461. break;
  462. case 0x03: // shift (for pp mode)
  463. r[2 / 2] = d & 1;
  464. break;
  465. case 0x05: // fill len
  466. r[4 / 2] = d & 0xff;
  467. break;
  468. case 0x0b:
  469. d &= 1;
  470. Pico32x.pending_fb = d;
  471. // if we are blanking and FS bit is changing
  472. if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
  473. r[0x0a/2] ^= P32XV_FS;
  474. Pico32xSwapDRAM(d ^ 1);
  475. elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
  476. }
  477. break;
  478. }
  479. }
  480. static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
  481. {
  482. a &= 0x0e;
  483. if (a == 6) { // fill start
  484. Pico32x.vdp_regs[6 / 2] = d;
  485. return;
  486. }
  487. if (a == 8) { // fill data
  488. u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
  489. int len = Pico32x.vdp_regs[4 / 2] + 1;
  490. int len1 = len;
  491. a = Pico32x.vdp_regs[6 / 2];
  492. while (len1--) {
  493. dram[a] = d;
  494. a = (a & 0xff00) | ((a + 1) & 0xff);
  495. }
  496. Pico32x.vdp_regs[0x06 / 2] = a;
  497. Pico32x.vdp_regs[0x08 / 2] = d;
  498. if (sh2 != NULL && len > 4) {
  499. Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
  500. // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles?
  501. p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len);
  502. }
  503. return;
  504. }
  505. p32x_vdp_write8(a | 1, d);
  506. }
  507. // ------------------------------------------------------------------
  508. // SH2 regs
  509. static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
  510. {
  511. u16 *r = Pico32x.regs;
  512. a &= 0x3e;
  513. switch (a) {
  514. case 0x00: // adapter/irq ctl
  515. return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0]
  516. | Pico32x.sh2irq_mask[sh2->is_slave];
  517. case 0x04: // H count (often as comm too)
  518. sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
  519. sh2s_sync_on_read(sh2);
  520. return Pico32x.sh2_regs[4 / 2];
  521. case 0x06:
  522. return (r[a / 2] & ~P32XS_FULL) | 0x4000;
  523. case 0x08: // DREQ src
  524. case 0x0a:
  525. case 0x0c: // DREQ dst
  526. case 0x0e:
  527. case 0x10: // DREQ len
  528. return r[a / 2];
  529. case 0x12: // DREQ FIFO - does this work on hw?
  530. if (Pico32x.dmac0_fifo_ptr > 0) {
  531. Pico32x.dmac0_fifo_ptr--;
  532. r[a / 2] = Pico32x.dmac_fifo[0];
  533. memmove(&Pico32x.dmac_fifo[0], &Pico32x.dmac_fifo[1],
  534. Pico32x.dmac0_fifo_ptr * 2);
  535. }
  536. return r[a / 2];
  537. case 0x14:
  538. case 0x16:
  539. case 0x18:
  540. case 0x1a:
  541. case 0x1c:
  542. return 0; // ?
  543. }
  544. // comm port
  545. if ((a & 0x30) == 0x20) {
  546. int comreg = 1 << (a & 0x0f) / 2;
  547. if (Pico32x.comm_dirty_68k & comreg)
  548. Pico32x.comm_dirty_68k &= ~comreg;
  549. else
  550. sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
  551. sh2s_sync_on_read(sh2);
  552. return r[a / 2];
  553. }
  554. if ((a & 0x30) == 0x30)
  555. return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2));
  556. elprintf_sh2(sh2, EL_32X|EL_ANOMALY,
  557. "unhandled sysreg r16 [%02x] @%08x", a, sh2_pc(sh2));
  558. return 0;
  559. }
  560. static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
  561. {
  562. u16 *r = Pico32x.regs;
  563. u32 old;
  564. a &= 0x3f;
  565. sh2->poll_addr = 0;
  566. switch (a) {
  567. case 0x00: // FM
  568. r[0] &= ~P32XS_FM;
  569. r[0] |= (d << 8) & P32XS_FM;
  570. return;
  571. case 0x01: // HEN/irq masks
  572. old = Pico32x.sh2irq_mask[sh2->is_slave];
  573. if ((d ^ old) & 1)
  574. p32x_pwm_sync_to_sh2(sh2);
  575. Pico32x.sh2irq_mask[sh2->is_slave] = d & 0x0f;
  576. Pico32x.sh2_regs[0] &= ~0x80;
  577. Pico32x.sh2_regs[0] |= d & 0x80;
  578. if ((d ^ old) & 1)
  579. p32x_pwm_schedule_sh2(sh2);
  580. if ((old ^ d) & 2)
  581. p32x_update_cmd_irq(sh2, 0);
  582. if ((old ^ d) & 4)
  583. p32x_schedule_hint(sh2, 0);
  584. return;
  585. case 0x04: // ignored?
  586. return;
  587. case 0x05: // H count
  588. d &= 0xff;
  589. if (Pico32x.sh2_regs[4 / 2] != d) {
  590. Pico32x.sh2_regs[4 / 2] = d;
  591. p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
  592. sh2_cycles_done_m68k(sh2));
  593. sh2_end_run(sh2, 4);
  594. }
  595. return;
  596. case 0x30:
  597. REG8IN16(r, a) = d & 0x0f;
  598. d = r[0x30 / 2];
  599. goto pwm_write;
  600. case 0x31: // PWM control
  601. REG8IN16(r, a) = d & 0x8f;
  602. d = r[0x30 / 2];
  603. goto pwm_write;
  604. case 0x32: // PWM cycle
  605. REG8IN16(r, a) = d & 0x0f;
  606. d = r[0x32 / 2];
  607. goto pwm_write;
  608. case 0x33:
  609. REG8IN16(r, a) = d;
  610. d = r[0x32 / 2];
  611. goto pwm_write;
  612. // PWM pulse regs.. Only writes to odd address send a value
  613. // to FIFO; reads are 0 (except status bits)
  614. case 0x34:
  615. case 0x36:
  616. case 0x38:
  617. REG8IN16(r, a) = d;
  618. return;
  619. case 0x35:
  620. case 0x37:
  621. case 0x39:
  622. d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
  623. REG8IN16(r, a ^ 1) = 0;
  624. goto pwm_write;
  625. case 0x3a: // ignored, always 0?
  626. case 0x3b:
  627. case 0x3c:
  628. case 0x3d:
  629. case 0x3e:
  630. case 0x3f:
  631. return;
  632. pwm_write:
  633. p32x_pwm_write16(a & ~1, d, sh2, 0);
  634. return;
  635. }
  636. if ((a & 0x30) == 0x20) {
  637. int comreg;
  638. if (REG8IN16(r, a) == d)
  639. return;
  640. REG8IN16(r, a) = d;
  641. p32x_m68k_poll_event(P32XF_68KCPOLL);
  642. p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
  643. sh2_cycles_done_m68k(sh2));
  644. comreg = 1 << (a & 0x0f) / 2;
  645. Pico32x.comm_dirty_sh2 |= comreg;
  646. return;
  647. }
  648. elprintf(EL_32X|EL_ANOMALY,
  649. "unhandled sysreg w8 [%02x] %02x @%08x", a, d, sh2_pc(sh2));
  650. }
  651. static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
  652. {
  653. a &= 0x3e;
  654. sh2->poll_addr = 0;
  655. // comm
  656. if ((a & 0x30) == 0x20) {
  657. int comreg;
  658. if (Pico32x.regs[a / 2] == d)
  659. return;
  660. Pico32x.regs[a / 2] = d;
  661. p32x_m68k_poll_event(P32XF_68KCPOLL);
  662. p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
  663. sh2_cycles_done_m68k(sh2));
  664. comreg = 1 << (a & 0x0f) / 2;
  665. Pico32x.comm_dirty_sh2 |= comreg;
  666. return;
  667. }
  668. // PWM
  669. else if ((a & 0x30) == 0x30) {
  670. p32x_pwm_write16(a, d, sh2, sh2_cycles_done_m68k(sh2));
  671. return;
  672. }
  673. switch (a) {
  674. case 0: // FM
  675. Pico32x.regs[0] &= ~P32XS_FM;
  676. Pico32x.regs[0] |= d & P32XS_FM;
  677. break;
  678. case 0x14:
  679. Pico32x.sh2irqs &= ~P32XI_VRES;
  680. goto irls;
  681. case 0x16:
  682. Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_VINT;
  683. goto irls;
  684. case 0x18:
  685. Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_HINT;
  686. goto irls;
  687. case 0x1a:
  688. Pico32x.regs[2 / 2] &= ~(1 << sh2->is_slave);
  689. p32x_update_cmd_irq(sh2, 0);
  690. return;
  691. case 0x1c:
  692. p32x_pwm_sync_to_sh2(sh2);
  693. Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_PWM;
  694. p32x_pwm_schedule_sh2(sh2);
  695. goto irls;
  696. }
  697. p32x_sh2reg_write8(a | 1, d, sh2);
  698. return;
  699. irls:
  700. p32x_update_irls(sh2, 0);
  701. }
  702. // ------------------------------------------------------------------
  703. // 32x 68k handlers
  704. // after ADEN
  705. static u32 PicoRead8_32x_on(u32 a)
  706. {
  707. u32 d = 0;
  708. if ((a & 0xffc0) == 0x5100) { // a15100
  709. d = p32x_reg_read16(a);
  710. goto out_16to8;
  711. }
  712. if ((a & 0xfc00) != 0x5000) {
  713. if (PicoAHW & PAHW_MCD)
  714. return PicoRead8_mcd_io(a);
  715. else
  716. return PicoRead8_io(a);
  717. }
  718. if ((a & 0xfff0) == 0x5180) { // a15180
  719. d = p32x_vdp_read16(a);
  720. goto out_16to8;
  721. }
  722. if ((a & 0xfe00) == 0x5200) { // a15200
  723. d = Pico32xMem->pal[(a & 0x1ff) / 2];
  724. goto out_16to8;
  725. }
  726. if ((a & 0xfffc) == 0x30ec) { // a130ec
  727. d = str_mars[a & 3];
  728. goto out;
  729. }
  730. elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
  731. return d;
  732. out_16to8:
  733. if (a & 1)
  734. d &= 0xff;
  735. else
  736. d >>= 8;
  737. out:
  738. elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
  739. return d;
  740. }
  741. static u32 PicoRead16_32x_on(u32 a)
  742. {
  743. u32 d = 0;
  744. if ((a & 0xffc0) == 0x5100) { // a15100
  745. d = p32x_reg_read16(a);
  746. goto out;
  747. }
  748. if ((a & 0xfc00) != 0x5000) {
  749. if (PicoAHW & PAHW_MCD)
  750. return PicoRead16_mcd_io(a);
  751. else
  752. return PicoRead16_io(a);
  753. }
  754. if ((a & 0xfff0) == 0x5180) { // a15180
  755. d = p32x_vdp_read16(a);
  756. goto out;
  757. }
  758. if ((a & 0xfe00) == 0x5200) { // a15200
  759. d = Pico32xMem->pal[(a & 0x1ff) / 2];
  760. goto out;
  761. }
  762. if ((a & 0xfffc) == 0x30ec) { // a130ec
  763. d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
  764. goto out;
  765. }
  766. elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
  767. return d;
  768. out:
  769. elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
  770. return d;
  771. }
  772. static void PicoWrite8_32x_on(u32 a, u32 d)
  773. {
  774. if ((a & 0xfc00) == 0x5000)
  775. elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  776. if ((a & 0xffc0) == 0x5100) { // a15100
  777. p32x_reg_write8(a, d);
  778. return;
  779. }
  780. if ((a & 0xfc00) != 0x5000) {
  781. if (PicoAHW & PAHW_MCD)
  782. PicoWrite8_mcd_io(a, d);
  783. else
  784. PicoWrite8_io(a, d);
  785. if (a == 0xa130f1)
  786. bank_switch(Pico32x.regs[4 / 2]);
  787. return;
  788. }
  789. if (!(Pico32x.regs[0] & P32XS_FM)) {
  790. if ((a & 0xfff0) == 0x5180) { // a15180
  791. p32x_vdp_write8(a, d);
  792. return;
  793. }
  794. // TODO: verify
  795. if ((a & 0xfe00) == 0x5200) { // a15200
  796. elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  797. ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
  798. Pico32x.dirty_pal = 1;
  799. return;
  800. }
  801. }
  802. elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  803. }
  804. static void PicoWrite16_32x_on(u32 a, u32 d)
  805. {
  806. if ((a & 0xfc00) == 0x5000)
  807. elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  808. if ((a & 0xffc0) == 0x5100) { // a15100
  809. p32x_reg_write16(a, d);
  810. return;
  811. }
  812. if ((a & 0xfc00) != 0x5000) {
  813. if (PicoAHW & PAHW_MCD)
  814. PicoWrite16_mcd_io(a, d);
  815. else
  816. PicoWrite16_io(a, d);
  817. if (a == 0xa130f0)
  818. bank_switch(Pico32x.regs[4 / 2]);
  819. return;
  820. }
  821. if (!(Pico32x.regs[0] & P32XS_FM)) {
  822. if ((a & 0xfff0) == 0x5180) { // a15180
  823. p32x_vdp_write16(a, d, NULL); // FIXME?
  824. return;
  825. }
  826. if ((a & 0xfe00) == 0x5200) { // a15200
  827. Pico32xMem->pal[(a & 0x1ff) / 2] = d;
  828. Pico32x.dirty_pal = 1;
  829. return;
  830. }
  831. }
  832. elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  833. }
  834. // before ADEN
  835. u32 PicoRead8_32x(u32 a)
  836. {
  837. u32 d = 0;
  838. if ((a & 0xffc0) == 0x5100) { // a15100
  839. // regs are always readable
  840. d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
  841. goto out;
  842. }
  843. if ((a & 0xfffc) == 0x30ec) { // a130ec
  844. d = str_mars[a & 3];
  845. goto out;
  846. }
  847. elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
  848. return d;
  849. out:
  850. elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
  851. return d;
  852. }
  853. u32 PicoRead16_32x(u32 a)
  854. {
  855. u32 d = 0;
  856. if ((a & 0xffc0) == 0x5100) { // a15100
  857. d = Pico32x.regs[(a & 0x3f) / 2];
  858. goto out;
  859. }
  860. if ((a & 0xfffc) == 0x30ec) { // a130ec
  861. d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
  862. goto out;
  863. }
  864. elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
  865. return d;
  866. out:
  867. elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
  868. return d;
  869. }
  870. void PicoWrite8_32x(u32 a, u32 d)
  871. {
  872. if ((a & 0xffc0) == 0x5100) { // a15100
  873. u16 *r = Pico32x.regs;
  874. elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  875. a &= 0x3f;
  876. if (a == 1) {
  877. if ((d ^ r[0]) & d & P32XS_ADEN) {
  878. Pico32xStartup();
  879. r[0] &= ~P32XS_nRES; // causes reset if specified by this write
  880. r[0] |= P32XS_ADEN;
  881. p32x_reg_write8(a, d); // forward for reset processing
  882. }
  883. return;
  884. }
  885. // allow only COMM for now
  886. if ((a & 0x30) == 0x20) {
  887. u8 *r8 = (u8 *)r;
  888. r8[a ^ 1] = d;
  889. }
  890. return;
  891. }
  892. elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  893. }
  894. void PicoWrite16_32x(u32 a, u32 d)
  895. {
  896. if ((a & 0xffc0) == 0x5100) { // a15100
  897. u16 *r = Pico32x.regs;
  898. elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  899. a &= 0x3e;
  900. if (a == 0) {
  901. if ((d ^ r[0]) & d & P32XS_ADEN) {
  902. Pico32xStartup();
  903. r[0] &= ~P32XS_nRES; // causes reset if specified by this write
  904. r[0] |= P32XS_ADEN;
  905. p32x_reg_write16(a, d); // forward for reset processing
  906. }
  907. return;
  908. }
  909. // allow only COMM for now
  910. if ((a & 0x30) == 0x20)
  911. r[a / 2] = d;
  912. return;
  913. }
  914. elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  915. }
  916. /* quirk: in both normal and overwrite areas only nonzero values go through */
  917. #define sh2_write8_dramN(n) \
  918. if ((d & 0xff) != 0) { \
  919. u8 *dram = (u8 *)Pico32xMem->dram[n]; \
  920. dram[(a & 0x1ffff) ^ 1] = d; \
  921. }
  922. static void m68k_write8_dram0_ow(u32 a, u32 d)
  923. {
  924. sh2_write8_dramN(0);
  925. }
  926. static void m68k_write8_dram1_ow(u32 a, u32 d)
  927. {
  928. sh2_write8_dramN(1);
  929. }
  930. #define sh2_write16_dramN(n) \
  931. u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
  932. if (!(a & 0x20000)) { \
  933. *pd = d; \
  934. return; \
  935. } \
  936. /* overwrite */ \
  937. if (!(d & 0xff00)) d |= *pd & 0xff00; \
  938. if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
  939. *pd = d;
  940. static void m68k_write16_dram0_ow(u32 a, u32 d)
  941. {
  942. sh2_write16_dramN(0);
  943. }
  944. static void m68k_write16_dram1_ow(u32 a, u32 d)
  945. {
  946. sh2_write16_dramN(1);
  947. }
  948. // -----------------------------------------------------------------
  949. // hint vector is writeable
  950. static void PicoWrite8_hint(u32 a, u32 d)
  951. {
  952. if ((a & 0xfffc) == 0x0070) {
  953. Pico32xMem->m68k_rom[a ^ 1] = d;
  954. return;
  955. }
  956. elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x",
  957. a, d & 0xff, SekPc);
  958. }
  959. static void PicoWrite16_hint(u32 a, u32 d)
  960. {
  961. if ((a & 0xfffc) == 0x0070) {
  962. ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
  963. return;
  964. }
  965. elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x",
  966. a, d & 0xffff, SekPc);
  967. }
  968. // normally not writable, but somebody could make a RAM cart
  969. static void PicoWrite8_cart(u32 a, u32 d)
  970. {
  971. elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  972. a &= 0xfffff;
  973. m68k_write8(a, d);
  974. }
  975. static void PicoWrite16_cart(u32 a, u32 d)
  976. {
  977. elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  978. a &= 0xfffff;
  979. m68k_write16(a, d);
  980. }
  981. // same with bank, but save ram is sometimes here
  982. static u32 PicoRead8_bank(u32 a)
  983. {
  984. a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
  985. return m68k_read8(a);
  986. }
  987. static u32 PicoRead16_bank(u32 a)
  988. {
  989. a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
  990. return m68k_read16(a);
  991. }
  992. static void PicoWrite8_bank(u32 a, u32 d)
  993. {
  994. if (!(Pico.m.sram_reg & SRR_MAPPED))
  995. elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x",
  996. a, d & 0xff, SekPc);
  997. a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
  998. m68k_write8(a, d);
  999. }
  1000. static void PicoWrite16_bank(u32 a, u32 d)
  1001. {
  1002. if (!(Pico.m.sram_reg & SRR_MAPPED))
  1003. elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x",
  1004. a, d & 0xffff, SekPc);
  1005. a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
  1006. m68k_write16(a, d);
  1007. }
  1008. static void bank_map_handler(void)
  1009. {
  1010. cpu68k_map_set(m68k_read8_map, 0x900000, 0x9fffff, PicoRead8_bank, 1);
  1011. cpu68k_map_set(m68k_read16_map, 0x900000, 0x9fffff, PicoRead16_bank, 1);
  1012. }
  1013. static void bank_switch(int b)
  1014. {
  1015. unsigned int rs, bank;
  1016. if (Pico.m.ncart_in)
  1017. return;
  1018. bank = b << 20;
  1019. if ((Pico.m.sram_reg & SRR_MAPPED) && bank == Pico.sv.start) {
  1020. bank_map_handler();
  1021. return;
  1022. }
  1023. if (bank >= Pico.romsize) {
  1024. elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
  1025. bank_map_handler();
  1026. return;
  1027. }
  1028. // 32X ROM (unbanked, XXX: consider mirroring?)
  1029. rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
  1030. rs -= bank;
  1031. if (rs > 0x100000)
  1032. rs = 0x100000;
  1033. cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
  1034. cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
  1035. elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
  1036. }
  1037. // -----------------------------------------------------------------
  1038. // SH2
  1039. // -----------------------------------------------------------------
  1040. // read8
  1041. static u32 sh2_read8_unmapped(u32 a, SH2 *sh2)
  1042. {
  1043. elprintf_sh2(sh2, EL_32X, "unmapped r8 [%08x] %02x @%06x",
  1044. a, 0, sh2_pc(sh2));
  1045. return 0;
  1046. }
  1047. static u32 sh2_read8_cs0(u32 a, SH2 *sh2)
  1048. {
  1049. u32 d = 0;
  1050. sh2_burn_cycles(sh2, 1*2);
  1051. // 0x3ffc0 is veridied
  1052. if ((a & 0x3ffc0) == 0x4000) {
  1053. d = p32x_sh2reg_read16(a, sh2);
  1054. goto out_16to8;
  1055. }
  1056. if ((a & 0x3fff0) == 0x4100) {
  1057. d = p32x_vdp_read16(a);
  1058. sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
  1059. goto out_16to8;
  1060. }
  1061. // TODO: mirroring?
  1062. if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
  1063. return Pico32xMem->sh2_rom_m.b[a ^ 1];
  1064. if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
  1065. return Pico32xMem->sh2_rom_s.b[a ^ 1];
  1066. if ((a & 0x3fe00) == 0x4200) {
  1067. d = Pico32xMem->pal[(a & 0x1ff) / 2];
  1068. goto out_16to8;
  1069. }
  1070. return sh2_read8_unmapped(a, sh2);
  1071. out_16to8:
  1072. if (a & 1)
  1073. d &= 0xff;
  1074. else
  1075. d >>= 8;
  1076. elprintf_sh2(sh2, EL_32X, "r8 [%08x] %02x @%06x",
  1077. a, d, sh2_pc(sh2));
  1078. return d;
  1079. }
  1080. static u32 sh2_read8_da(u32 a, SH2 *sh2)
  1081. {
  1082. return sh2->data_array[(a & 0xfff) ^ 1];
  1083. }
  1084. // read16
  1085. static u32 sh2_read16_unmapped(u32 a, SH2 *sh2)
  1086. {
  1087. elprintf_sh2(sh2, EL_32X, "unmapped r16 [%08x] %04x @%06x",
  1088. a, 0, sh2_pc(sh2));
  1089. return 0;
  1090. }
  1091. static u32 sh2_read16_cs0(u32 a, SH2 *sh2)
  1092. {
  1093. u32 d = 0;
  1094. sh2_burn_cycles(sh2, 1*2);
  1095. if ((a & 0x3ffc0) == 0x4000) {
  1096. d = p32x_sh2reg_read16(a, sh2);
  1097. if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
  1098. return d;
  1099. goto out;
  1100. }
  1101. if ((a & 0x3fff0) == 0x4100) {
  1102. d = p32x_vdp_read16(a);
  1103. sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
  1104. goto out;
  1105. }
  1106. if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
  1107. return Pico32xMem->sh2_rom_m.w[a / 2];
  1108. if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
  1109. return Pico32xMem->sh2_rom_s.w[a / 2];
  1110. if ((a & 0x3fe00) == 0x4200) {
  1111. d = Pico32xMem->pal[(a & 0x1ff) / 2];
  1112. goto out;
  1113. }
  1114. return sh2_read16_unmapped(a, sh2);
  1115. out:
  1116. elprintf_sh2(sh2, EL_32X, "r16 [%08x] %04x @%06x",
  1117. a, d, sh2_pc(sh2));
  1118. return d;
  1119. }
  1120. static u32 sh2_read16_da(u32 a, SH2 *sh2)
  1121. {
  1122. return ((u16 *)sh2->data_array)[(a & 0xfff) / 2];
  1123. }
  1124. // writes
  1125. static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2)
  1126. {
  1127. }
  1128. // write8
  1129. static void REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, SH2 *sh2)
  1130. {
  1131. elprintf_sh2(sh2, EL_32X, "unmapped w8 [%08x] %02x @%06x",
  1132. a, d & 0xff, sh2_pc(sh2));
  1133. }
  1134. static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
  1135. {
  1136. elprintf_sh2(sh2, EL_32X, "w8 [%08x] %02x @%06x",
  1137. a, d & 0xff, sh2_pc(sh2));
  1138. if (Pico32x.regs[0] & P32XS_FM) {
  1139. if ((a & 0x3fff0) == 0x4100) {
  1140. sh2->poll_addr = 0;
  1141. p32x_vdp_write8(a, d);
  1142. return;
  1143. }
  1144. }
  1145. if ((a & 0x3ffc0) == 0x4000) {
  1146. p32x_sh2reg_write8(a, d, sh2);
  1147. return;
  1148. }
  1149. sh2_write8_unmapped(a, d, sh2);
  1150. }
  1151. static void REGPARM(3) sh2_write8_dram0(u32 a, u32 d, SH2 *sh2)
  1152. {
  1153. sh2_write8_dramN(0);
  1154. }
  1155. static void REGPARM(3) sh2_write8_dram1(u32 a, u32 d, SH2 *sh2)
  1156. {
  1157. sh2_write8_dramN(1);
  1158. }
  1159. static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2)
  1160. {
  1161. u32 a1 = a & 0x3ffff;
  1162. #ifdef DRC_SH2
  1163. int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
  1164. if (t)
  1165. sh2_drc_wcheck_ram(a, t, sh2->is_slave);
  1166. #endif
  1167. Pico32xMem->sdram[a1 ^ 1] = d;
  1168. }
  1169. static void REGPARM(3) sh2_write8_sdram_wt(u32 a, u32 d, SH2 *sh2)
  1170. {
  1171. // xmen sync hack..
  1172. if (a < 0x26000200)
  1173. sh2_end_run(sh2, 32);
  1174. sh2_write8_sdram(a, d, sh2);
  1175. }
  1176. static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2)
  1177. {
  1178. u32 a1 = a & 0xfff;
  1179. #ifdef DRC_SH2
  1180. int id = sh2->is_slave;
  1181. int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
  1182. if (t)
  1183. sh2_drc_wcheck_da(a, t, id);
  1184. #endif
  1185. sh2->data_array[a1 ^ 1] = d;
  1186. }
  1187. // write16
  1188. static void REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, SH2 *sh2)
  1189. {
  1190. elprintf_sh2(sh2, EL_32X, "unmapped w16 [%08x] %04x @%06x",
  1191. a, d & 0xffff, sh2_pc(sh2));
  1192. }
  1193. static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2)
  1194. {
  1195. if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
  1196. elprintf_sh2(sh2, EL_32X, "w16 [%08x] %04x @%06x",
  1197. a, d & 0xffff, sh2_pc(sh2));
  1198. if (Pico32x.regs[0] & P32XS_FM) {
  1199. if ((a & 0x3fff0) == 0x4100) {
  1200. sh2->poll_addr = 0;
  1201. p32x_vdp_write16(a, d, sh2);
  1202. return;
  1203. }
  1204. if ((a & 0x3fe00) == 0x4200) {
  1205. Pico32xMem->pal[(a & 0x1ff) / 2] = d;
  1206. Pico32x.dirty_pal = 1;
  1207. return;
  1208. }
  1209. }
  1210. if ((a & 0x3ffc0) == 0x4000) {
  1211. p32x_sh2reg_write16(a, d, sh2);
  1212. return;
  1213. }
  1214. sh2_write16_unmapped(a, d, sh2);
  1215. }
  1216. static void REGPARM(3) sh2_write16_dram0(u32 a, u32 d, SH2 *sh2)
  1217. {
  1218. sh2_write16_dramN(0);
  1219. }
  1220. static void REGPARM(3) sh2_write16_dram1(u32 a, u32 d, SH2 *sh2)
  1221. {
  1222. sh2_write16_dramN(1);
  1223. }
  1224. static void REGPARM(3) sh2_write16_sdram(u32 a, u32 d, SH2 *sh2)
  1225. {
  1226. u32 a1 = a & 0x3ffff;
  1227. #ifdef DRC_SH2
  1228. int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
  1229. if (t)
  1230. sh2_drc_wcheck_ram(a, t, sh2->is_slave);
  1231. #endif
  1232. ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
  1233. }
  1234. static void REGPARM(3) sh2_write16_da(u32 a, u32 d, SH2 *sh2)
  1235. {
  1236. u32 a1 = a & 0xfff;
  1237. #ifdef DRC_SH2
  1238. int id = sh2->is_slave;
  1239. int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
  1240. if (t)
  1241. sh2_drc_wcheck_da(a, t, id);
  1242. #endif
  1243. ((u16 *)sh2->data_array)[a1 / 2] = d;
  1244. }
  1245. typedef u32 (sh2_read_handler)(u32 a, SH2 *sh2);
  1246. typedef void REGPARM(3) (sh2_write_handler)(u32 a, u32 d, SH2 *sh2);
  1247. #define SH2MAP_ADDR2OFFS_R(a) \
  1248. ((u32)(a) >> SH2_READ_SHIFT)
  1249. #define SH2MAP_ADDR2OFFS_W(a) \
  1250. ((u32)(a) >> SH2_WRITE_SHIFT)
  1251. u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
  1252. {
  1253. const sh2_memmap *sh2_map = sh2->read8_map;
  1254. uptr p;
  1255. sh2_map += SH2MAP_ADDR2OFFS_R(a);
  1256. p = sh2_map->addr;
  1257. if (map_flag_set(p))
  1258. return ((sh2_read_handler *)(p << 1))(a, sh2);
  1259. else
  1260. return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
  1261. }
  1262. u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
  1263. {
  1264. const sh2_memmap *sh2_map = sh2->read16_map;
  1265. uptr p;
  1266. sh2_map += SH2MAP_ADDR2OFFS_R(a);
  1267. p = sh2_map->addr;
  1268. if (map_flag_set(p))
  1269. return ((sh2_read_handler *)(p << 1))(a, sh2);
  1270. else
  1271. return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
  1272. }
  1273. u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
  1274. {
  1275. const sh2_memmap *sh2_map = sh2->read16_map;
  1276. sh2_read_handler *handler;
  1277. u32 offs;
  1278. uptr p;
  1279. offs = SH2MAP_ADDR2OFFS_R(a);
  1280. sh2_map += offs;
  1281. p = sh2_map->addr;
  1282. if (!map_flag_set(p)) {
  1283. // XXX: maybe 32bit access instead with ror?
  1284. u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
  1285. return (pd[0] << 16) | pd[1];
  1286. }
  1287. if (offs == SH2MAP_ADDR2OFFS_R(0xffffc000))
  1288. return sh2_peripheral_read32(a, sh2);
  1289. handler = (sh2_read_handler *)(p << 1);
  1290. return (handler(a, sh2) << 16) | handler(a + 2, sh2);
  1291. }
  1292. void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
  1293. {
  1294. const void **sh2_wmap = sh2->write8_tab;
  1295. sh2_write_handler *wh;
  1296. wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
  1297. wh(a, d, sh2);
  1298. }
  1299. void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
  1300. {
  1301. const void **sh2_wmap = sh2->write16_tab;
  1302. sh2_write_handler *wh;
  1303. wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
  1304. wh(a, d, sh2);
  1305. }
  1306. void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
  1307. {
  1308. const void **sh2_wmap = sh2->write16_tab;
  1309. sh2_write_handler *wh;
  1310. u32 offs;
  1311. offs = SH2MAP_ADDR2OFFS_W(a);
  1312. if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
  1313. sh2_peripheral_write32(a, d, sh2);
  1314. return;
  1315. }
  1316. wh = sh2_wmap[offs];
  1317. wh(a, d >> 16, sh2);
  1318. wh(a + 2, d, sh2);
  1319. }
  1320. // -----------------------------------------------------------------
  1321. static void z80_md_bank_write_32x(unsigned int a, unsigned char d)
  1322. {
  1323. unsigned int addr68k;
  1324. addr68k = Pico.m.z80_bank68k << 15;
  1325. addr68k += a & 0x7fff;
  1326. if ((addr68k & 0xfff000) == 0xa15000)
  1327. Pico32x.emu_flags |= P32XF_Z80_32X_IO;
  1328. elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, d);
  1329. m68k_write8(addr68k, d);
  1330. }
  1331. // -----------------------------------------------------------------
  1332. static const u16 msh2_code[] = {
  1333. // trap instructions
  1334. 0xaffe, // 200 bra <self>
  1335. 0x0009, // 202 nop
  1336. // have to wait a bit until m68k initial program finishes clearing stuff
  1337. // to avoid races with game SH2 code, like in Tempo
  1338. 0xd406, // 204 mov.l @(_m_ok,pc), r4
  1339. 0xc400, // 206 mov.b @(h'0,gbr),r0
  1340. 0xc801, // 208 tst #1, r0
  1341. 0x8b0f, // 20a bf cd_start
  1342. 0xd105, // 20c mov.l @(_cnt,pc), r1
  1343. 0xd206, // 20e mov.l @(_start,pc), r2
  1344. 0x71ff, // 210 add #-1, r1
  1345. 0x4115, // 212 cmp/pl r1
  1346. 0x89fc, // 214 bt -2
  1347. 0x6043, // 216 mov r4, r0
  1348. 0xc208, // 218 mov.l r0, @(h'20,gbr)
  1349. 0x6822, // 21a mov.l @r2, r8
  1350. 0x482b, // 21c jmp @r8
  1351. 0x0009, // 21e nop
  1352. ('M'<<8)|'_', ('O'<<8)|'K', // 220 _m_ok
  1353. 0x0001, 0x0000, // 224 _cnt
  1354. 0x2200, 0x03e0, // master start pointer in ROM
  1355. // cd_start:
  1356. 0xd20d, // 22c mov.l @(__cd_,pc), r2
  1357. 0xc608, // 22e mov.l @(h'20,gbr), r0
  1358. 0x3200, // 230 cmp/eq r0, r2
  1359. 0x8bfc, // 232 bf #-2
  1360. 0xe000, // 234 mov #0, r0
  1361. 0xcf80, // 236 or.b #0x80,@(r0,gbr)
  1362. 0xd80b, // 238 mov.l @(_start_cd,pc), r8 // 24000018
  1363. 0xd30c, // 23a mov.l @(_max_len,pc), r3
  1364. 0x5b84, // 23c mov.l @(h'10,r8), r11 // master vbr
  1365. 0x5a82, // 23e mov.l @(8,r8), r10 // entry
  1366. 0x5081, // 240 mov.l @(4,r8), r0 // len
  1367. 0x5980, // 242 mov.l @(0,r8), r9 // dst
  1368. 0x3036, // 244 cmp/hi r3,r0
  1369. 0x8b00, // 246 bf #1
  1370. 0x6033, // 248 mov r3,r0
  1371. 0x7820, // 24a add #0x20, r8
  1372. // ipl_copy:
  1373. 0x6286, // 24c mov.l @r8+, r2
  1374. 0x2922, // 24e mov.l r2, @r9
  1375. 0x7904, // 250 add #4, r9
  1376. 0x70fc, // 252 add #-4, r0
  1377. 0x8800, // 254 cmp/eq #0, r0
  1378. 0x8bf9, // 256 bf #-5
  1379. //
  1380. 0x4b2e, // 258 ldc r11, vbr
  1381. 0x6043, // 25a mov r4, r0 // M_OK
  1382. 0xc208, // 25c mov.l r0, @(h'20,gbr)
  1383. 0x4a2b, // 25e jmp @r10
  1384. 0x0009, // 260 nop
  1385. 0x0009, // 262 nop // pad
  1386. ('_'<<8)|'C', ('D'<<8)|'_', // 264 __cd_
  1387. 0x2400, 0x0018, // 268 _start_cd
  1388. 0x0001, 0xffe0, // 26c _max_len
  1389. };
  1390. static const u16 ssh2_code[] = {
  1391. 0xaffe, // 200 bra <self>
  1392. 0x0009, // 202 nop
  1393. // code to wait for master, in case authentic master BIOS is used
  1394. 0xd106, // 204 mov.l @(_m_ok,pc), r1
  1395. 0xd208, // 206 mov.l @(_start,pc), r2
  1396. 0xc608, // 208 mov.l @(h'20,gbr), r0
  1397. 0x3100, // 20a cmp/eq r0, r1
  1398. 0x8bfc, // 20c bf #-2
  1399. 0xc400, // 20e mov.b @(h'0,gbr),r0
  1400. 0xc801, // 210 tst #1, r0
  1401. 0xd004, // 212 mov.l @(_s_ok,pc), r0
  1402. 0x8b0a, // 214 bf cd_start
  1403. 0xc209, // 216 mov.l r0, @(h'24,gbr)
  1404. 0x6822, // 218 mov.l @r2, r8
  1405. 0x482b, // 21a jmp @r8
  1406. 0x0009, // 21c nop
  1407. 0x0009, // 21e nop
  1408. ('M'<<8)|'_', ('O'<<8)|'K', // 220
  1409. ('S'<<8)|'_', ('O'<<8)|'K', // 224
  1410. 0x2200, 0x03e4, // slave start pointer in ROM
  1411. // cd_start:
  1412. 0xd803, // 22c mov.l @(_start_cd,pc), r8 // 24000018
  1413. 0x5b85, // 22e mov.l @(h'14,r8), r11 // slave vbr
  1414. 0x5a83, // 230 mov.l @(h'0c,r8), r10 // entry
  1415. 0x4b2e, // 232 ldc r11, vbr
  1416. 0xc209, // 234 mov.l r0, @(h'24,gbr) // write S_OK
  1417. 0x4a2b, // 236 jmp @r10
  1418. 0x0009, // 238 nop
  1419. 0x0009, // 23a nop
  1420. 0x2400, 0x0018, // 23c _start_cd
  1421. };
  1422. #define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16))
  1423. static void get_bios(void)
  1424. {
  1425. u16 *ps;
  1426. u32 *pl;
  1427. int i;
  1428. // M68K ROM
  1429. if (p32x_bios_g != NULL) {
  1430. elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
  1431. Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
  1432. }
  1433. else {
  1434. // generate 68k ROM
  1435. ps = (u16 *)Pico32xMem->m68k_rom;
  1436. pl = (u32 *)ps;
  1437. for (i = 1; i < 0xc0/4; i++)
  1438. pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
  1439. // fill with nops
  1440. for (i = 0xc0/2; i < 0x100/2; i++)
  1441. ps[i] = 0x4e71;
  1442. #if 0
  1443. ps[0xc0/2] = 0x46fc;
  1444. ps[0xc2/2] = 0x2700; // move #0x2700,sr
  1445. ps[0xfe/2] = 0x60fe; // jump to self
  1446. #else
  1447. ps[0xfe/2] = 0x4e75; // rts
  1448. #endif
  1449. }
  1450. // fill remaining m68k_rom page with game ROM
  1451. memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
  1452. Pico.rom + sizeof(Pico32xMem->m68k_rom),
  1453. sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
  1454. // MSH2
  1455. if (p32x_bios_m != NULL) {
  1456. elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
  1457. Byteswap(&Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
  1458. }
  1459. else {
  1460. pl = (u32 *)&Pico32xMem->sh2_rom_m;
  1461. // fill exception vector table to our trap address
  1462. for (i = 0; i < 128; i++)
  1463. pl[i] = HWSWAP(0x200);
  1464. // start
  1465. pl[0] = pl[2] = HWSWAP(0x204);
  1466. // reset SP
  1467. pl[1] = pl[3] = HWSWAP(0x6040000);
  1468. // startup code
  1469. memcpy(&Pico32xMem->sh2_rom_m.b[0x200], msh2_code, sizeof(msh2_code));
  1470. }
  1471. // SSH2
  1472. if (p32x_bios_s != NULL) {
  1473. elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
  1474. Byteswap(&Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
  1475. }
  1476. else {
  1477. pl = (u32 *)&Pico32xMem->sh2_rom_s;
  1478. // fill exception vector table to our trap address
  1479. for (i = 0; i < 128; i++)
  1480. pl[i] = HWSWAP(0x200);
  1481. // start
  1482. pl[0] = pl[2] = HWSWAP(0x204);
  1483. // reset SP
  1484. pl[1] = pl[3] = HWSWAP(0x603f800);
  1485. // startup code
  1486. memcpy(&Pico32xMem->sh2_rom_s.b[0x200], ssh2_code, sizeof(ssh2_code));
  1487. }
  1488. }
  1489. #define MAP_MEMORY(m) ((uptr)(m) >> 1)
  1490. #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
  1491. static sh2_memmap sh2_read8_map[0x80], sh2_read16_map[0x80];
  1492. // for writes we are using handlers only
  1493. static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
  1494. void Pico32xSwapDRAM(int b)
  1495. {
  1496. cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
  1497. cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
  1498. cpu68k_map_set(m68k_read8_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
  1499. cpu68k_map_set(m68k_read16_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
  1500. cpu68k_map_set(m68k_write8_map, 0x840000, 0x87ffff,
  1501. b ? m68k_write8_dram1_ow : m68k_write8_dram0_ow, 1);
  1502. cpu68k_map_set(m68k_write16_map, 0x840000, 0x87ffff,
  1503. b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1);
  1504. // SH2
  1505. sh2_read8_map[0x04/2].addr = sh2_read8_map[0x24/2].addr =
  1506. sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
  1507. sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
  1508. sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
  1509. }
  1510. void PicoMemSetup32x(void)
  1511. {
  1512. unsigned int rs;
  1513. int i;
  1514. Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
  1515. if (Pico32xMem == NULL) {
  1516. elprintf(EL_STATUS, "OOM");
  1517. return;
  1518. }
  1519. get_bios();
  1520. // cartridge area becomes unmapped
  1521. // XXX: we take the easy way and don't unmap ROM,
  1522. // so that we can avoid handling the RV bit.
  1523. // m68k_map_unmap(0x000000, 0x3fffff);
  1524. if (!Pico.m.ncart_in) {
  1525. // MD ROM area
  1526. rs = sizeof(Pico32xMem->m68k_rom_bank);
  1527. cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
  1528. cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
  1529. cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
  1530. cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
  1531. // 32X ROM (unbanked, XXX: consider mirroring?)
  1532. rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
  1533. if (rs > 0x80000)
  1534. rs = 0x80000;
  1535. cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
  1536. cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
  1537. cpu68k_map_set(m68k_write8_map, 0x880000, 0x880000 + rs - 1, PicoWrite8_cart, 1);
  1538. cpu68k_map_set(m68k_write16_map, 0x880000, 0x880000 + rs - 1, PicoWrite16_cart, 1);
  1539. #ifdef EMU_F68K
  1540. // setup FAME fetchmap
  1541. PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
  1542. for (rs = 0x88; rs < 0x90; rs++)
  1543. PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
  1544. #endif
  1545. // 32X ROM (banked)
  1546. bank_switch(0);
  1547. cpu68k_map_set(m68k_write8_map, 0x900000, 0x9fffff, PicoWrite8_bank, 1);
  1548. cpu68k_map_set(m68k_write16_map, 0x900000, 0x9fffff, PicoWrite16_bank, 1);
  1549. }
  1550. // SYS regs
  1551. cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
  1552. cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
  1553. cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
  1554. cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
  1555. // SH2 maps: A31,A30,A29,CS1,CS0
  1556. // all unmapped by default
  1557. for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
  1558. sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
  1559. sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
  1560. }
  1561. for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
  1562. sh2_write8_map[i] = sh2_write8_unmapped;
  1563. sh2_write16_map[i] = sh2_write16_unmapped;
  1564. }
  1565. // "purge area"
  1566. for (i = 0x40; i <= 0x5f; i++) {
  1567. sh2_write8_map[i >> 1] =
  1568. sh2_write16_map[i >> 1] = sh2_write_ignore;
  1569. }
  1570. // CS0
  1571. sh2_read8_map[0x00/2].addr = sh2_read8_map[0x20/2].addr = MAP_HANDLER(sh2_read8_cs0);
  1572. sh2_read16_map[0x00/2].addr = sh2_read16_map[0x20/2].addr = MAP_HANDLER(sh2_read16_cs0);
  1573. sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
  1574. sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
  1575. // CS1 - ROM
  1576. sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr =
  1577. sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
  1578. sh2_read8_map[0x02/2].mask = sh2_read8_map[0x22/2].mask =
  1579. sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3fffff; // FIXME
  1580. // CS2 - DRAM - done by Pico32xSwapDRAM()
  1581. sh2_read8_map[0x04/2].mask = sh2_read8_map[0x24/2].mask =
  1582. sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01ffff;
  1583. // CS3 - SDRAM
  1584. sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr =
  1585. sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram);
  1586. sh2_write8_map[0x06/2] = sh2_write8_sdram;
  1587. sh2_write8_map[0x26/2] = sh2_write8_sdram_wt;
  1588. sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
  1589. sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask =
  1590. sh2_read16_map[0x06/2].mask = sh2_read16_map[0x26/2].mask = 0x03ffff;
  1591. // SH2 data array
  1592. sh2_read8_map[0xc0/2].addr = MAP_HANDLER(sh2_read8_da);
  1593. sh2_read16_map[0xc0/2].addr = MAP_HANDLER(sh2_read16_da);
  1594. sh2_write8_map[0xc0/2] = sh2_write8_da;
  1595. sh2_write16_map[0xc0/2] = sh2_write16_da;
  1596. // SH2 IO
  1597. sh2_read8_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read8);
  1598. sh2_read16_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read16);
  1599. sh2_write8_map[0xff/2] = sh2_peripheral_write8;
  1600. sh2_write16_map[0xff/2] = sh2_peripheral_write16;
  1601. // map DRAM area, both 68k and SH2
  1602. Pico32xSwapDRAM(1);
  1603. msh2.read8_map = ssh2.read8_map = sh2_read8_map;
  1604. msh2.read16_map = ssh2.read16_map = sh2_read16_map;
  1605. msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
  1606. msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
  1607. sh2_drc_mem_setup(&msh2);
  1608. sh2_drc_mem_setup(&ssh2);
  1609. // z80 hack
  1610. z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write_32x, 1);
  1611. }
  1612. void Pico32xMemStateLoaded(void)
  1613. {
  1614. bank_switch(Pico32x.regs[4 / 2]);
  1615. Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
  1616. memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
  1617. Pico32x.dirty_pal = 1;
  1618. Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL);
  1619. memset(&m68k_poll, 0, sizeof(m68k_poll));
  1620. msh2.state = 0;
  1621. msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0;
  1622. ssh2.state = 0;
  1623. ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0;
  1624. sh2_drc_flush_all();
  1625. }
  1626. // vim:shiftwidth=2:ts=2:expandtab