z80if.c 7.7 KB

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  1. /*
  2. * PicoDrive
  3. * (C) notaz, 2007-2010
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. */
  8. #include <stddef.h>
  9. #include "pico_int.h"
  10. #include "memory.h"
  11. uptr z80_read_map [0x10000 >> Z80_MEM_SHIFT];
  12. uptr z80_write_map[0x10000 >> Z80_MEM_SHIFT];
  13. #ifdef _USE_DRZ80
  14. // this causes trouble in some cases, like doukutsu putting sp in bank area
  15. // no perf difference for most, upto 1-2% for some others
  16. //#define FAST_Z80SP
  17. struct DrZ80 drZ80;
  18. static void drz80_load_pcsp(u32 pc, u32 sp)
  19. {
  20. drZ80.Z80PC_BASE = z80_read_map[pc >> Z80_MEM_SHIFT];
  21. if (drZ80.Z80PC_BASE & (1<<31)) {
  22. elprintf(EL_STATUS|EL_ANOMALY, "load_pcsp: bad PC: %04x", pc);
  23. drZ80.Z80PC_BASE = drZ80.Z80PC = z80_read_map[0];
  24. } else {
  25. drZ80.Z80PC_BASE <<= 1;
  26. drZ80.Z80PC = drZ80.Z80PC_BASE + pc;
  27. }
  28. drZ80.Z80SP = sp;
  29. #ifdef FAST_Z80SP
  30. drZ80.Z80SP_BASE = z80_read_map[sp >> Z80_MEM_SHIFT];
  31. if (drZ80.Z80SP_BASE & (1<<31)) {
  32. elprintf(EL_STATUS|EL_ANOMALY, "load_pcsp: bad SP: %04x", sp);
  33. drZ80.Z80SP_BASE = z80_read_map[0];
  34. drZ80.Z80SP = drZ80.Z80SP_BASE + (1 << Z80_MEM_SHIFT);
  35. } else {
  36. drZ80.Z80SP_BASE <<= 1;
  37. drZ80.Z80SP = drZ80.Z80SP_BASE + sp;
  38. }
  39. #endif
  40. }
  41. // called only if internal xmap rebase fails
  42. static unsigned int dz80_rebase_pc(unsigned short pc)
  43. {
  44. elprintf(EL_STATUS|EL_ANOMALY, "dz80_rebase_pc: fail on %04x", pc);
  45. drZ80.Z80PC_BASE = z80_read_map[0] << 1;
  46. return drZ80.Z80PC_BASE;
  47. }
  48. #ifdef FAST_Z80SP
  49. static u32 drz80_sp_base;
  50. static unsigned int dz80_rebase_sp(unsigned short sp)
  51. {
  52. elprintf(EL_STATUS|EL_ANOMALY, "dz80_rebase_sp: fail on %04x", sp);
  53. drZ80.Z80SP_BASE = z80_read_map[drz80_sp_base >> Z80_MEM_SHIFT] << 1;
  54. return drZ80.Z80SP_BASE + (1 << Z80_MEM_SHIFT) - 0x100;
  55. }
  56. #else
  57. #define dz80_rebase_sp NULL
  58. #endif
  59. #endif // _USE_DRZ80
  60. void z80_init(void)
  61. {
  62. #ifdef _USE_DRZ80
  63. memset(&drZ80, 0, sizeof(drZ80));
  64. drZ80.z80_rebasePC = dz80_rebase_pc;
  65. drZ80.z80_rebaseSP = dz80_rebase_sp;
  66. drZ80.z80_read8 = (void *)z80_read_map;
  67. drZ80.z80_read16 = NULL;
  68. drZ80.z80_write8 = (void *)z80_write_map;
  69. drZ80.z80_write16 = NULL;
  70. drZ80.z80_irq_callback = NULL;
  71. #endif
  72. #ifdef _USE_CZ80
  73. memset(&CZ80, 0, sizeof(CZ80));
  74. Cz80_Init(&CZ80);
  75. Cz80_Set_ReadB(&CZ80, NULL); // unused (hacked in)
  76. Cz80_Set_WriteB(&CZ80, NULL);
  77. #endif
  78. }
  79. void z80_reset(void)
  80. {
  81. #ifdef _USE_DRZ80
  82. drZ80.Z80I = 0;
  83. drZ80.Z80IM = 0;
  84. drZ80.Z80IF = 0;
  85. drZ80.z80irqvector = 0xff0000; // RST 38h
  86. drZ80.Z80PC_BASE = drZ80.Z80PC = z80_read_map[0] << 1;
  87. // others not changed, undefined on cold boot
  88. /*
  89. drZ80.Z80F = (1<<2); // set ZFlag
  90. drZ80.Z80F2 = (1<<2); // set ZFlag
  91. drZ80.Z80IX = 0xFFFF << 16;
  92. drZ80.Z80IY = 0xFFFF << 16;
  93. */
  94. #ifdef FAST_Z80SP
  95. // drZ80 is locked in single bank
  96. drz80_sp_base = (PicoAHW & PAHW_SMS) ? 0xc000 : 0x0000;
  97. drZ80.Z80SP_BASE = z80_read_map[drz80_sp_base >> Z80_MEM_SHIFT] << 1;
  98. #endif
  99. if (PicoAHW & PAHW_SMS)
  100. drZ80.Z80SP = drZ80.Z80SP_BASE + 0xdff0; // simulate BIOS
  101. // XXX: since we use direct SP pointer, it might make sense to force it to RAM,
  102. // but we'll rely on built-in stack protection for now
  103. #endif
  104. #ifdef _USE_CZ80
  105. Cz80_Reset(&CZ80);
  106. if (PicoAHW & PAHW_SMS)
  107. Cz80_Set_Reg(&CZ80, CZ80_SP, 0xdff0);
  108. #endif
  109. }
  110. struct z80sr_main {
  111. u8 a, f;
  112. u8 b, c;
  113. u8 d, e;
  114. u8 h, l;
  115. };
  116. struct z80_state {
  117. char magic[4];
  118. // regs
  119. struct z80sr_main m; // main regs
  120. struct z80sr_main a; // alt (') regs
  121. u8 i, r;
  122. u16 ix, iy;
  123. u16 sp;
  124. u16 pc;
  125. // other
  126. u8 halted;
  127. u8 iff1, iff2;
  128. u8 im; // irq mode
  129. u8 irq_pending; // irq line level, 1 if active
  130. u8 irq_vector[3]; // up to 3 byte vector for irq mode0 handling
  131. u8 reserved[8];
  132. };
  133. void z80_pack(void *data)
  134. {
  135. struct z80_state *s = data;
  136. memset(data, 0, Z80_STATE_SIZE);
  137. strcpy(s->magic, "Z80");
  138. #if defined(_USE_DRZ80)
  139. #define DRR8(n) (drZ80.Z80##n >> 24)
  140. #define DRR16(n) (drZ80.Z80##n >> 16)
  141. #define DRR16H(n) (drZ80.Z80##n >> 24)
  142. #define DRR16L(n) ((drZ80.Z80##n >> 16) & 0xff)
  143. s->m.a = DRR8(A); s->m.f = drZ80.Z80F;
  144. s->m.b = DRR16H(BC); s->m.c = DRR16L(BC);
  145. s->m.d = DRR16H(DE); s->m.e = DRR16L(DE);
  146. s->m.h = DRR16H(HL); s->m.l = DRR16L(HL);
  147. s->a.a = DRR8(A2); s->a.f = drZ80.Z80F2;
  148. s->a.b = DRR16H(BC2); s->a.c = DRR16L(BC2);
  149. s->a.d = DRR16H(DE2); s->a.e = DRR16L(DE2);
  150. s->a.h = DRR16H(HL2); s->a.l = DRR16L(HL2);
  151. s->i = DRR8(I); s->r = drZ80.spare;
  152. s->ix = DRR16(IX); s->iy = DRR16(IY);
  153. s->sp = drZ80.Z80SP - drZ80.Z80SP_BASE;
  154. s->pc = drZ80.Z80PC - drZ80.Z80PC_BASE;
  155. s->halted = !!(drZ80.Z80IF & 4);
  156. s->iff1 = !!(drZ80.Z80IF & 1);
  157. s->iff2 = !!(drZ80.Z80IF & 2);
  158. s->im = drZ80.Z80IM;
  159. s->irq_pending = !!drZ80.Z80_IRQ;
  160. s->irq_vector[0] = drZ80.z80irqvector >> 16;
  161. s->irq_vector[1] = drZ80.z80irqvector >> 8;
  162. s->irq_vector[2] = drZ80.z80irqvector;
  163. #elif defined(_USE_CZ80)
  164. {
  165. const cz80_struc *CPU = &CZ80;
  166. s->m.a = zA; s->m.f = zF;
  167. s->m.b = zB; s->m.c = zC;
  168. s->m.d = zD; s->m.e = zE;
  169. s->m.h = zH; s->m.l = zL;
  170. s->a.a = zA2; s->a.f = zF2;
  171. s->a.b = CZ80.BC2.B.H; s->a.c = CZ80.BC2.B.L;
  172. s->a.d = CZ80.DE2.B.H; s->a.e = CZ80.DE2.B.L;
  173. s->a.h = CZ80.HL2.B.H; s->a.l = CZ80.HL2.B.L;
  174. s->i = zI; s->r = zR;
  175. s->ix = zIX; s->iy = zIY;
  176. s->sp = Cz80_Get_Reg(&CZ80, CZ80_SP);
  177. s->pc = Cz80_Get_Reg(&CZ80, CZ80_PC);
  178. s->halted = !!Cz80_Get_Reg(&CZ80, CZ80_HALT);
  179. s->iff1 = !!zIFF1;
  180. s->iff2 = !!zIFF2;
  181. s->im = zIM;
  182. s->irq_pending = (Cz80_Get_Reg(&CZ80, CZ80_IRQ) == HOLD_LINE);
  183. s->irq_vector[0] = 0xff;
  184. }
  185. #endif
  186. }
  187. int z80_unpack(const void *data)
  188. {
  189. const struct z80_state *s = data;
  190. if (strcmp(s->magic, "Z80") != 0) {
  191. elprintf(EL_STATUS, "legacy z80 state - ignored");
  192. return 0;
  193. }
  194. #if defined(_USE_DRZ80)
  195. #define DRW8(n, v) drZ80.Z80##n = (u32)(v) << 24
  196. #define DRW16(n, v) drZ80.Z80##n = (u32)(v) << 16
  197. #define DRW16HL(n, h, l) drZ80.Z80##n = ((u32)(h) << 24) | ((u32)(l) << 16)
  198. DRW8(A, s->m.a); drZ80.Z80F = s->m.f;
  199. DRW16HL(BC, s->m.b, s->m.c);
  200. DRW16HL(DE, s->m.d, s->m.e);
  201. DRW16HL(HL, s->m.h, s->m.l);
  202. DRW8(A2, s->a.a); drZ80.Z80F2 = s->a.f;
  203. DRW16HL(BC2, s->a.b, s->a.c);
  204. DRW16HL(DE2, s->a.d, s->a.e);
  205. DRW16HL(HL2, s->a.h, s->a.l);
  206. DRW8(I, s->i); drZ80.spare = s->r;
  207. DRW16(IX, s->ix); DRW16(IY, s->iy);
  208. drz80_load_pcsp(s->pc, s->sp);
  209. drZ80.Z80IF = 0;
  210. if (s->halted) drZ80.Z80IF |= 4;
  211. if (s->iff1) drZ80.Z80IF |= 1;
  212. if (s->iff2) drZ80.Z80IF |= 2;
  213. drZ80.Z80IM = s->im;
  214. drZ80.Z80_IRQ = s->irq_pending;
  215. drZ80.z80irqvector = ((u32)s->irq_vector[0] << 16) |
  216. ((u32)s->irq_vector[1] << 8) | s->irq_vector[2];
  217. return 0;
  218. #elif defined(_USE_CZ80)
  219. {
  220. cz80_struc *CPU = &CZ80;
  221. zA = s->m.a; zF = s->m.f;
  222. zB = s->m.b; zC = s->m.c;
  223. zD = s->m.d; zE = s->m.e;
  224. zH = s->m.h; zL = s->m.l;
  225. zA2 = s->a.a; zF2 = s->a.f;
  226. CZ80.BC2.B.H = s->a.b; CZ80.BC2.B.L = s->a.c;
  227. CZ80.DE2.B.H = s->a.d; CZ80.DE2.B.L = s->a.e;
  228. CZ80.HL2.B.H = s->a.h; CZ80.HL2.B.L = s->a.l;
  229. zI = s->i; zR = s->r;
  230. zIX = s->ix; zIY = s->iy;
  231. Cz80_Set_Reg(&CZ80, CZ80_SP, s->sp);
  232. Cz80_Set_Reg(&CZ80, CZ80_PC, s->pc);
  233. Cz80_Set_Reg(&CZ80, CZ80_HALT, s->halted);
  234. Cz80_Set_Reg(&CZ80, CZ80_IFF1, s->iff1);
  235. Cz80_Set_Reg(&CZ80, CZ80_IFF2, s->iff2);
  236. zIM = s->im;
  237. Cz80_Set_Reg(&CZ80, CZ80_IRQ, s->irq_pending ? HOLD_LINE : CLEAR_LINE);
  238. return 0;
  239. }
  240. #else
  241. return 0;
  242. #endif
  243. }
  244. void z80_exit(void)
  245. {
  246. }
  247. void z80_debug(char *dstr)
  248. {
  249. #if defined(_USE_DRZ80)
  250. sprintf(dstr, "Z80 state: PC: %04x SP: %04x\n", drZ80.Z80PC-drZ80.Z80PC_BASE, drZ80.Z80SP-drZ80.Z80SP_BASE);
  251. #elif defined(_USE_CZ80)
  252. sprintf(dstr, "Z80 state: PC: %04x SP: %04x\n", (unsigned int)(CZ80.PC - CZ80.BasePC), CZ80.SP.W);
  253. #endif
  254. }
  255. // vim:ts=2:sw=2:expandtab