cz80.h 6.3 KB

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  1. /******************************************************************************
  2. *
  3. * CZ80 (Z80 CPU emulator) version 0.9
  4. * Compiled with Dev-C++
  5. * Copyright 2004-2005 Stéphane Dallongeville
  6. *
  7. * (Modified by NJ)
  8. *
  9. *****************************************************************************/
  10. #ifndef CZ80_H
  11. #define CZ80_H
  12. // uintptr_t
  13. #include <stdlib.h>
  14. #ifndef _MSC_VER
  15. #include <stdint.h>
  16. #endif
  17. #ifdef __cplusplus
  18. extern "C" {
  19. #endif
  20. #include <pico/pico_port.h>
  21. /******************************/
  22. /* Compiler dependant defines */
  23. /******************************/
  24. #ifndef UINT8
  25. #define UINT8 u8
  26. #endif
  27. #ifndef INT8
  28. #define INT8 s8
  29. #endif
  30. #ifndef UINT16
  31. #define UINT16 u16
  32. #endif
  33. #ifndef INT16
  34. #define INT16 s16
  35. #endif
  36. #ifndef UINT32
  37. #define UINT32 u32
  38. #endif
  39. #ifndef INT32
  40. #define INT32 s32
  41. #endif
  42. #ifndef FPTR
  43. #define FPTR uptr
  44. #endif
  45. /*************************************/
  46. /* Z80 core Structures & definitions */
  47. /*************************************/
  48. // NB this must have at least the value of (16-Z80_MEM_SHIFT)
  49. #define CZ80_FETCH_BITS 6 // [4-12] default = 8
  50. #define CZ80_FETCH_SFT (16 - CZ80_FETCH_BITS)
  51. #define CZ80_FETCH_BANK (1 << CZ80_FETCH_BITS)
  52. #define PICODRIVE_HACKS 1
  53. #define CZ80_LITTLE_ENDIAN CPU_IS_LE
  54. #define CZ80_USE_JUMPTABLE 1
  55. #define CZ80_BIG_FLAGS_ARRAY 1
  56. //#ifdef BUILD_CPS1PSP
  57. //#define CZ80_ENCRYPTED_ROM 1
  58. //#else
  59. #define CZ80_ENCRYPTED_ROM 0
  60. //#endif
  61. #define CZ80_EMULATE_R_EXACTLY 1
  62. #define zR8(A) (*CPU->pzR8[A])
  63. #define zR16(A) (CPU->pzR16[A]->W)
  64. #define pzAF &(CPU->AF)
  65. #define zAF CPU->AF.W
  66. #define zlAF CPU->AF.B.L
  67. #define zhAF CPU->AF.B.H
  68. #define zA zhAF
  69. #define zF zlAF
  70. #define pzBC &(CPU->BC)
  71. #define zBC CPU->BC.W
  72. #define zlBC CPU->BC.B.L
  73. #define zhBC CPU->BC.B.H
  74. #define zB zhBC
  75. #define zC zlBC
  76. #define pzDE &(CPU->DE)
  77. #define zDE CPU->DE.W
  78. #define zlDE CPU->DE.B.L
  79. #define zhDE CPU->DE.B.H
  80. #define zD zhDE
  81. #define zE zlDE
  82. #define pzHL &(CPU->HL)
  83. #define zHL CPU->HL.W
  84. #define zlHL CPU->HL.B.L
  85. #define zhHL CPU->HL.B.H
  86. #define zH zhHL
  87. #define zL zlHL
  88. #define zAF2 CPU->AF2.W
  89. #define zlAF2 CPU->AF2.B.L
  90. #define zhAF2 CPU->AF2.B.H
  91. #define zA2 zhAF2
  92. #define zF2 zlAF2
  93. #define zBC2 CPU->BC2.W
  94. #define zDE2 CPU->DE2.W
  95. #define zHL2 CPU->HL2.W
  96. #define pzIX &(CPU->IX)
  97. #define zIX CPU->IX.W
  98. #define zlIX CPU->IX.B.L
  99. #define zhIX CPU->IX.B.H
  100. #define pzIY &(CPU->IY)
  101. #define zIY CPU->IY.W
  102. #define zlIY CPU->IY.B.L
  103. #define zhIY CPU->IY.B.H
  104. #define pzSP &(CPU->SP)
  105. #define zSP CPU->SP.W
  106. #define zlSP CPU->SP.B.L
  107. #define zhSP CPU->SP.B.H
  108. #define zRealPC (PC - CPU->BasePC)
  109. #define zPC PC
  110. #define zI CPU->I
  111. #define zIM CPU->IM
  112. #define zwR CPU->R.W
  113. #define zR1 CPU->R.B.L
  114. #define zR2 CPU->R.B.H
  115. #define zR zR1
  116. #define zIFF CPU->IFF.W
  117. #define zIFF1 CPU->IFF.B.L
  118. #define zIFF2 CPU->IFF.B.H
  119. #define CZ80_SF_SFT 7
  120. #define CZ80_ZF_SFT 6
  121. #define CZ80_YF_SFT 5
  122. #define CZ80_HF_SFT 4
  123. #define CZ80_XF_SFT 3
  124. #define CZ80_PF_SFT 2
  125. #define CZ80_VF_SFT 2
  126. #define CZ80_NF_SFT 1
  127. #define CZ80_CF_SFT 0
  128. #define CZ80_SF (1 << CZ80_SF_SFT)
  129. #define CZ80_ZF (1 << CZ80_ZF_SFT)
  130. #define CZ80_YF (1 << CZ80_YF_SFT)
  131. #define CZ80_HF (1 << CZ80_HF_SFT)
  132. #define CZ80_XF (1 << CZ80_XF_SFT)
  133. #define CZ80_PF (1 << CZ80_PF_SFT)
  134. #define CZ80_VF (1 << CZ80_VF_SFT)
  135. #define CZ80_NF (1 << CZ80_NF_SFT)
  136. #define CZ80_CF (1 << CZ80_CF_SFT)
  137. #define CZ80_IFF_SFT CZ80_PF_SFT
  138. #define CZ80_IFF CZ80_PF
  139. #ifndef IRQ_LINE_STATE
  140. #define IRQ_LINE_STATE
  141. #define CLEAR_LINE 0 /* clear (a fired, held or pulsed) line */
  142. #define ASSERT_LINE 1 /* assert an interrupt immediately */
  143. #define HOLD_LINE 2 /* hold interrupt line until acknowledged */
  144. #define PULSE_LINE 3 /* pulse interrupt line for one instruction */
  145. #define IRQ_LINE_NMI 127 /* IRQ line for NMIs */
  146. #endif
  147. enum
  148. {
  149. CZ80_PC = 1,
  150. CZ80_SP,
  151. CZ80_AF,
  152. CZ80_BC,
  153. CZ80_DE,
  154. CZ80_HL,
  155. CZ80_IX,
  156. CZ80_IY,
  157. CZ80_AF2,
  158. CZ80_BC2,
  159. CZ80_DE2,
  160. CZ80_HL2,
  161. CZ80_R,
  162. CZ80_I,
  163. CZ80_IM,
  164. CZ80_IFF1,
  165. CZ80_IFF2,
  166. CZ80_HALT,
  167. CZ80_IRQ
  168. };
  169. typedef union
  170. {
  171. struct
  172. {
  173. #if CZ80_LITTLE_ENDIAN
  174. UINT8 L;
  175. UINT8 H;
  176. #else
  177. UINT8 H;
  178. UINT8 L;
  179. #endif
  180. } B;
  181. UINT16 W;
  182. } union16;
  183. typedef struct cz80_t
  184. {
  185. union
  186. {
  187. UINT8 r8[8];
  188. union16 r16[4];
  189. struct
  190. {
  191. union16 BC;
  192. union16 DE;
  193. union16 HL;
  194. union16 AF;
  195. };
  196. };
  197. union16 IX;
  198. union16 IY;
  199. union16 SP;
  200. UINT32 unusedPC; /* left for binary compat */
  201. union16 BC2;
  202. union16 DE2;
  203. union16 HL2;
  204. union16 AF2;
  205. union16 R;
  206. union16 IFF;
  207. UINT8 I;
  208. UINT8 IM;
  209. UINT8 HaltState;
  210. UINT8 dummy;
  211. INT32 IRQLine;
  212. INT32 IRQState;
  213. INT32 ICount;
  214. INT32 ExtraCycles;
  215. FPTR BasePC;
  216. FPTR PC;
  217. FPTR Fetch[CZ80_FETCH_BANK];
  218. #if CZ80_ENCRYPTED_ROM
  219. FPTR OPBase;
  220. FPTR OPFetch[CZ80_FETCH_BANK];
  221. #endif
  222. UINT8 *pzR8[8];
  223. union16 *pzR16[4];
  224. UINT8 (*Read_Byte)(UINT32 address);
  225. void (*Write_Byte)(UINT32 address, UINT8 data);
  226. UINT8 (*IN_Port)(UINT16 port);
  227. void (*OUT_Port)(UINT16 port, UINT8 value);
  228. INT32 (*Interrupt_Callback)(INT32 irqline);
  229. } cz80_struc;
  230. /*************************/
  231. /* Publics Z80 variables */
  232. /*************************/
  233. extern cz80_struc CZ80;
  234. /*************************/
  235. /* Publics Z80 functions */
  236. /*************************/
  237. void Cz80_Init(cz80_struc *CPU);
  238. void Cz80_Reset(cz80_struc *CPU);
  239. INT32 Cz80_Exec(cz80_struc *CPU, INT32 cycles);
  240. void Cz80_Set_IRQ(cz80_struc *CPU, INT32 line, INT32 state);
  241. UINT32 Cz80_Get_Reg(cz80_struc *CPU, INT32 regnum);
  242. void Cz80_Set_Reg(cz80_struc *CPU, INT32 regnum, UINT32 value);
  243. void Cz80_Set_Fetch(cz80_struc *CPU, UINT32 low_adr, UINT32 high_adr, FPTR fetch_adr);
  244. #if CZ80_ENCRYPTED_ROM
  245. void Cz80_Set_Encrypt_Range(cz80_struc *CPU, UINT32 low_adr, UINT32 high_adr, UINT32 decrypted_rom);
  246. #endif
  247. void Cz80_Set_ReadB(cz80_struc *CPU, UINT8 (*Func)(UINT32 address));
  248. void Cz80_Set_WriteB(cz80_struc *CPU, void (*Func)(UINT32 address, UINT8 data));
  249. void Cz80_Set_INPort(cz80_struc *CPU, UINT8 (*Func)(UINT16 port));
  250. void Cz80_Set_OUTPort(cz80_struc *CPU, void (*Func)(UINT16 port, UINT8 value));
  251. void Cz80_Set_IRQ_Callback(cz80_struc *CPU, INT32 (*Func)(INT32 irqline));
  252. #ifdef __cplusplus
  253. };
  254. #endif
  255. #endif /* CZ80_H */