sh2.h 4.1 KB

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  1. #ifndef __SH2_H__
  2. #define __SH2_H__
  3. #include "../../pico/pico_port.h"
  4. // registers - matches structure order
  5. typedef enum {
  6. SHR_R0 = 0, SHR_SP = 15,
  7. SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
  8. SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
  9. SH2_REGS // register set size
  10. } sh2_reg_e;
  11. #define SHR_R(n) (SHR_R0+(n))
  12. typedef struct SH2_
  13. {
  14. // registers. this MUST correlate with enum sh2_reg_e.
  15. uint32_t r[16] ALIGNED(32);
  16. uint32_t pc; // 40
  17. uint32_t ppc;
  18. uint32_t pr;
  19. uint32_t sr;
  20. uint32_t gbr, vbr; // 50
  21. uint32_t mach, macl; // 58
  22. // common
  23. const void *read8_map;
  24. const void *read16_map;
  25. const void *read32_map;
  26. const void **write8_tab;
  27. const void **write16_tab;
  28. const void **write32_tab;
  29. // drc stuff
  30. int drc_tmp;
  31. int irq_cycles;
  32. void *p_bios; // convenience pointers
  33. void *p_da;
  34. void *p_sdram;
  35. void *p_rom;
  36. void *p_dram;
  37. void *p_drcblk_da;
  38. void *p_drcblk_ram;
  39. unsigned int pdb_io_csum[2];
  40. #define SH2_STATE_RUN (1 << 0) // to prevent recursion
  41. #define SH2_STATE_SLEEP (1 << 1) // temporarily stopped (DMA, IO, ...)
  42. #define SH2_STATE_CPOLL (1 << 2) // polling comm regs
  43. #define SH2_STATE_VPOLL (1 << 3) // polling VDP
  44. #define SH2_STATE_RPOLL (1 << 4) // polling address in SDRAM
  45. #define SH2_TIMER_RUN (1 << 8) // SOC WDT timer is running
  46. unsigned int state;
  47. uint32_t poll_addr;
  48. int poll_cycles;
  49. int poll_cnt;
  50. // DRC branch cache. size must be 2^n and <=128
  51. int rts_cache_idx;
  52. struct { uint32_t pc; void *code; } rts_cache[16];
  53. struct { uint32_t pc; void *code; } branch_cache[128];
  54. // interpreter stuff
  55. int icount; // cycles left in current timeslice
  56. unsigned int ea;
  57. unsigned int delay;
  58. unsigned int test_irq;
  59. int pending_level; // MAX(pending_irl, pending_int_irq)
  60. int pending_irl;
  61. int pending_int_irq; // internal irq
  62. int pending_int_vector;
  63. int REGPARM(2) (*irq_callback)(struct SH2_ *sh2, int level);
  64. int is_slave;
  65. unsigned int cycles_timeslice;
  66. struct SH2_ *other_sh2;
  67. int (*run)(struct SH2_ *, int);
  68. // we use 68k reference cycles for easier sync
  69. unsigned int m68krcycles_done;
  70. unsigned int mult_m68k_to_sh2;
  71. unsigned int mult_sh2_to_m68k;
  72. uint8_t data_array[0x1000]; // cache (can be used as RAM)
  73. uint32_t peri_regs[0x200/4]; // peripheral regs
  74. } SH2;
  75. #define CYCLE_MULT_SHIFT 10
  76. #define C_M68K_TO_SH2(xsh2, c) \
  77. (int)(((uint64_t)(c) * (xsh2)->mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)
  78. #define C_SH2_TO_M68K(xsh2, c) \
  79. (int)(((uint64_t)(c+3U) * (xsh2)->mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)
  80. int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);
  81. void sh2_finish(SH2 *sh2);
  82. void sh2_reset(SH2 *sh2);
  83. int sh2_irl_irq(SH2 *sh2, int level, int nested_call);
  84. void sh2_internal_irq(SH2 *sh2, int level, int vector);
  85. void sh2_do_irq(SH2 *sh2, int level, int vector);
  86. void sh2_pack(const SH2 *sh2, unsigned char *buff);
  87. void sh2_unpack(SH2 *sh2, const unsigned char *buff);
  88. int sh2_execute_drc(SH2 *sh2c, int cycles);
  89. int sh2_execute_interpreter(SH2 *sh2c, int cycles);
  90. static __inline void sh2_execute_prepare(SH2 *sh2, int use_drc)
  91. {
  92. #ifdef DRC_SH2
  93. sh2->run = use_drc ? sh2_execute_drc : sh2_execute_interpreter;
  94. #else
  95. sh2->run = sh2_execute_interpreter;
  96. #endif
  97. }
  98. static __inline int sh2_execute(SH2 *sh2, int cycles)
  99. {
  100. int ret;
  101. sh2->cycles_timeslice = cycles;
  102. ret = sh2->run(sh2, cycles);
  103. return sh2->cycles_timeslice - ret;
  104. }
  105. // regs, pending_int*, cycles, reserved
  106. #define SH2_STATE_SIZE ((24 + 2 + 2 + 12) * 4)
  107. // pico memhandlers
  108. // XXX: move somewhere else
  109. unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);
  110. unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);
  111. unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);
  112. void REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);
  113. void REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);
  114. void REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);
  115. // debug
  116. #ifdef DRC_CMP
  117. void do_sh2_trace(SH2 *current, int cycles);
  118. void REGPARM(1) do_sh2_cmp(SH2 *current);
  119. #endif
  120. #endif /* __SH2_H__ */