emit_x86.c 38 KB

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  1. /*
  2. * Basic macros to emit x86 instructions and some utils
  3. * Copyright (C) 2008,2009,2010 notaz
  4. * Copyright (C) 2019 kub
  5. *
  6. * This work is licensed under the terms of MAME license.
  7. * See COPYING file in the top-level directory.
  8. *
  9. * note:
  10. * temp registers must be eax-edx due to use of SETcc and r/w 8/16.
  11. * note about silly things like emith_eor_r_r_r:
  12. * these are here because the compiler was designed
  13. * for ARM as it's primary target.
  14. */
  15. #include <stdarg.h>
  16. enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
  17. xR8, xR9, xR10, xR11, xR12, xR13, xR14, xR15 }; // x86-64 only
  18. #define CONTEXT_REG xBP
  19. #define RET_REG xAX
  20. #define ICOND_JO 0x00
  21. #define ICOND_JNO 0x01
  22. #define ICOND_JB 0x02
  23. #define ICOND_JAE 0x03
  24. #define ICOND_JE 0x04
  25. #define ICOND_JNE 0x05
  26. #define ICOND_JBE 0x06
  27. #define ICOND_JA 0x07
  28. #define ICOND_JS 0x08
  29. #define ICOND_JNS 0x09
  30. #define ICOND_JL 0x0c
  31. #define ICOND_JGE 0x0d
  32. #define ICOND_JLE 0x0e
  33. #define ICOND_JG 0x0f
  34. #define IOP_JMP 0xeb
  35. // unified conditions (we just use rel8 jump instructions for x86)
  36. #define DCOND_EQ ICOND_JE
  37. #define DCOND_NE ICOND_JNE
  38. #define DCOND_MI ICOND_JS // MInus
  39. #define DCOND_PL ICOND_JNS // PLus or zero
  40. #define DCOND_HI ICOND_JA // higher (unsigned)
  41. #define DCOND_HS ICOND_JAE // higher || same (unsigned)
  42. #define DCOND_LO ICOND_JB // lower (unsigned)
  43. #define DCOND_LS ICOND_JBE // lower || same (unsigned)
  44. #define DCOND_GE ICOND_JGE // greater || equal (signed)
  45. #define DCOND_GT ICOND_JG // greater (signed)
  46. #define DCOND_LE ICOND_JLE // less || equal (signed)
  47. #define DCOND_LT ICOND_JL // less (signed)
  48. #define DCOND_VS ICOND_JO // oVerflow Set
  49. #define DCOND_VC ICOND_JNO // oVerflow Clear
  50. #define DCOND_CS ICOND_JB // carry set
  51. #define DCOND_CC ICOND_JAE // carry clear
  52. #define EMIT_PTR(ptr, val, type) \
  53. *(type *)(ptr) = val
  54. #define EMIT(val, type) do { \
  55. EMIT_PTR(tcache_ptr, val, type); \
  56. tcache_ptr += sizeof(type); \
  57. } while (0)
  58. #define EMIT_OP(op) do { \
  59. COUNT_OP; \
  60. if ((op) > 0xff) EMIT((op) >> 8, u8); \
  61. EMIT((u8)(op), u8); \
  62. } while (0)
  63. #define EMIT_MODRM(mod, r, rm) do { \
  64. assert((mod) < 4u); \
  65. assert((r) < 8u); \
  66. assert((rm) < 8u); \
  67. EMIT(((mod)<<6) | ((r)<<3) | (rm), u8); \
  68. } while (0)
  69. #define EMIT_SIB(scale, index, base) do { \
  70. assert((scale) < 4u); \
  71. assert((index) < 8u); \
  72. assert((base) < 8u); \
  73. EMIT(((scale)<<6) | ((index)<<3) | (base), u8); \
  74. } while (0)
  75. #define EMIT_SIB64(scale, index, base) \
  76. EMIT_SIB(scale, (index) & ~8u, (base) & ~8u)
  77. #define EMIT_REX(w,r,x,b) \
  78. EMIT(0x40 | ((w)<<3) | ((r)<<2) | ((x)<<1) | (b), u8)
  79. #define EMIT_OP_MODRM(op,mod,r,rm) do { \
  80. EMIT_OP(op); \
  81. EMIT_MODRM(mod, (r), rm); \
  82. } while (0)
  83. // 64bit friendly, rm when everything is converted
  84. #define EMIT_OP_MODRM64(op, mod, r, rm) \
  85. EMIT_OP_MODRM(op, mod, (r) & ~8u, (rm) & ~8u)
  86. #define JMP8_POS(ptr) \
  87. ptr = tcache_ptr; \
  88. tcache_ptr += 2
  89. #define JMP8_EMIT(op, ptr) \
  90. EMIT_PTR(ptr, 0x70|(op), u8); \
  91. EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
  92. #define JMP8_EMIT_NC(ptr) \
  93. EMIT_PTR(ptr, IOP_JMP, u8); \
  94. EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
  95. // _r_r
  96. #define emith_move_r_r(dst, src) do {\
  97. EMIT_REX_IF(0, dst, src); \
  98. EMIT_OP_MODRM64(0x8b, 3, dst, src); \
  99. } while (0)
  100. #define emith_move_r_r_ptr(dst, src) do { \
  101. EMIT_REX_IF(1, dst, src); \
  102. EMIT_OP_MODRM64(0x8b, 3, dst, src); \
  103. } while (0)
  104. #define emith_add_r_r(d, s) do { \
  105. EMIT_REX_IF(0, s, d); \
  106. EMIT_OP_MODRM64(0x01, 3, s, d); \
  107. } while (0)
  108. #define emith_add_r_r_ptr(d, s) do { \
  109. EMIT_REX_IF(1, s, d); \
  110. EMIT_OP_MODRM64(0x01, 3, s, d); \
  111. } while (0)
  112. #define emith_sub_r_r(d, s) do {\
  113. EMIT_REX_IF(0, s, d); \
  114. EMIT_OP_MODRM64(0x29, 3, s, d); \
  115. } while (0)
  116. #define emith_adc_r_r(d, s) do { \
  117. EMIT_REX_IF(0, s, d); \
  118. EMIT_OP_MODRM64(0x11, 3, s, d); \
  119. } while (0)
  120. #define emith_sbc_r_r(d, s) do { \
  121. EMIT_REX_IF(0, s, d); \
  122. EMIT_OP_MODRM64(0x19, 3, s, d); /* SBB */ \
  123. } while (0)
  124. #define emith_or_r_r(d, s) do { \
  125. EMIT_REX_IF(0, s, d); \
  126. EMIT_OP_MODRM64(0x09, 3, s, d); \
  127. } while (0)
  128. #define emith_and_r_r(d, s) do { \
  129. EMIT_REX_IF(0, s, d); \
  130. EMIT_OP_MODRM64(0x21, 3, s, d); \
  131. } while (0)
  132. #define emith_eor_r_r(d, s) do { \
  133. EMIT_REX_IF(0, s, d); \
  134. EMIT_OP_MODRM64(0x31, 3, s, d); /* XOR */ \
  135. } while (0)
  136. #define emith_tst_r_r(d, s) do { \
  137. EMIT_REX_IF(0, s, d); \
  138. EMIT_OP_MODRM64(0x85, 3, s, d); /* TEST */ \
  139. } while (0)
  140. #define emith_tst_r_r_ptr(d, s) do { \
  141. EMIT_REX_IF(1, s, d); \
  142. EMIT_OP_MODRM64(0x85, 3, s, d); /* TEST */ \
  143. } while (0)
  144. #define emith_cmp_r_r(d, s) do { \
  145. EMIT_REX_IF(0, s, d); \
  146. EMIT_OP_MODRM64(0x39, 3, s, d); \
  147. } while (0)
  148. // fake teq - test equivalence - get_flags(d ^ s)
  149. #define emith_teq_r_r(d, s) do { \
  150. emith_push(d); \
  151. emith_eor_r_r(d, s); \
  152. emith_pop(d); \
  153. } while (0)
  154. #define emith_mvn_r_r(d, s) do { \
  155. if (d != s) \
  156. emith_move_r_r(d, s); \
  157. EMIT_REX_IF(0, 0, d); \
  158. EMIT_OP_MODRM64(0xf7, 3, 2, d); /* NOT d */ \
  159. } while (0)
  160. #define emith_negc_r_r(d, s) do { \
  161. int tmp_ = rcache_get_tmp(); \
  162. emith_move_r_imm(tmp_, 0); \
  163. emith_sbc_r_r(tmp_, s); \
  164. emith_move_r_r(d, tmp_); \
  165. rcache_free_tmp(tmp_); \
  166. } while (0)
  167. #define emith_neg_r_r(d, s) do { \
  168. if (d != s) \
  169. emith_move_r_r(d, s); \
  170. EMIT_REX_IF(0, 0, d); \
  171. EMIT_OP_MODRM64(0xf7, 3, 3, d); /* NEG d */ \
  172. } while (0)
  173. // _r_r_r
  174. #define emith_add_r_r_r(d, s1, s2) do { \
  175. if (d == s1) { \
  176. emith_add_r_r(d, s2); \
  177. } else if (d == s2) { \
  178. emith_add_r_r(d, s1); \
  179. } else { \
  180. emith_move_r_r(d, s1); \
  181. emith_add_r_r(d, s2); \
  182. } \
  183. } while (0)
  184. #define emith_add_r_r_r_ptr(d, s1, s2) do { \
  185. if (d == s1) { \
  186. emith_add_r_r_ptr(d, s2); \
  187. } else if (d == s2) { \
  188. emith_add_r_r_ptr(d, s1); \
  189. } else { \
  190. emith_move_r_r_ptr(d, s1); \
  191. emith_add_r_r_ptr(d, s2); \
  192. } \
  193. } while (0)
  194. #define emith_sub_r_r_r(d, s1, s2) do { \
  195. if (d == s1) { \
  196. emith_sub_r_r(d, s2); \
  197. } else if (d == s2) { \
  198. emith_sub_r_r(d, s1); \
  199. } else { \
  200. emith_move_r_r(d, s1); \
  201. emith_sub_r_r(d, s2); \
  202. } \
  203. } while (0)
  204. #define emith_adc_r_r_r(d, s1, s2) do { \
  205. if (d == s1) { \
  206. emith_adc_r_r(d, s2); \
  207. } else if (d == s2) { \
  208. emith_adc_r_r(d, s1); \
  209. } else { \
  210. emith_move_r_r(d, s1); \
  211. emith_adc_r_r(d, s2); \
  212. } \
  213. } while (0)
  214. #define emith_sbc_r_r_r(d, s1, s2) do { \
  215. if (d == s1) { \
  216. emith_sbc_r_r(d, s2); \
  217. } else if (d == s2) { \
  218. emith_sbc_r_r(d, s1); \
  219. } else { \
  220. emith_move_r_r(d, s1); \
  221. emith_sbc_r_r(d, s2); \
  222. } \
  223. } while (0)
  224. #define emith_and_r_r_r(d, s1, s2) do { \
  225. if (d == s1) { \
  226. emith_and_r_r(d, s2); \
  227. } else if (d == s2) { \
  228. emith_and_r_r(d, s1); \
  229. } else { \
  230. emith_move_r_r(d, s1); \
  231. emith_and_r_r(d, s2); \
  232. } \
  233. } while (0)
  234. #define emith_or_r_r_r(d, s1, s2) do { \
  235. if (d == s1) { \
  236. emith_or_r_r(d, s2); \
  237. } else if (d == s2) { \
  238. emith_or_r_r(d, s1); \
  239. } else { \
  240. emith_move_r_r(d, s1); \
  241. emith_or_r_r(d, s2); \
  242. } \
  243. } while (0)
  244. #define emith_eor_r_r_r(d, s1, s2) do { \
  245. if (d == s1) { \
  246. emith_eor_r_r(d, s2); \
  247. } else if (d == s2) { \
  248. emith_eor_r_r(d, s1); \
  249. } else { \
  250. emith_move_r_r(d, s1); \
  251. emith_eor_r_r(d, s2); \
  252. } \
  253. } while (0)
  254. // _r_r_r_shift
  255. #define emith_add_r_r_r_lsl(d, s1, s2, lslimm) do { \
  256. if (lslimm) { \
  257. int tmp_ = rcache_get_tmp(); \
  258. emith_lsl(tmp_, s2, lslimm); \
  259. emith_add_r_r_r(d, s1, tmp_); \
  260. rcache_free_tmp(tmp_); \
  261. } else emith_add_r_r_r(d, s1, s2); \
  262. } while (0)
  263. #define emith_add_r_r_r_lsl_ptr(d, s1, s2, lslimm) do { \
  264. if (lslimm) { \
  265. int tmp_ = rcache_get_tmp(); \
  266. emith_lsl(tmp_, s2, lslimm); \
  267. emith_add_r_r_r_ptr(d, s1, tmp_); \
  268. rcache_free_tmp(tmp_); \
  269. } else emith_add_r_r_r_ptr(d, s1, s2); \
  270. } while (0)
  271. #define emith_add_r_r_r_lsr(d, s1, s2, lsrimm) do { \
  272. if (lsrimm) { \
  273. int tmp_ = rcache_get_tmp(); \
  274. emith_lsr(tmp_, s2, lsrimm); \
  275. emith_add_r_r_r(d, s1, tmp_); \
  276. rcache_free_tmp(tmp_); \
  277. } else emith_add_r_r_r(d, s1, s2); \
  278. } while (0)
  279. #define emith_sub_r_r_r_lsl(d, s1, s2, lslimm) do { \
  280. if (lslimm) { \
  281. int tmp_ = rcache_get_tmp(); \
  282. emith_lsl(tmp_, s2, lslimm); \
  283. emith_sub_r_r_r(d, s1, tmp_); \
  284. rcache_free_tmp(tmp_); \
  285. } else emith_sub_r_r_r(d, s1, s2); \
  286. } while (0)
  287. #define emith_or_r_r_r_lsl(d, s1, s2, lslimm) do { \
  288. if (lslimm) { \
  289. int tmp_ = rcache_get_tmp(); \
  290. emith_lsl(tmp_, s2, lslimm); \
  291. emith_or_r_r_r(d, s1, tmp_); \
  292. rcache_free_tmp(tmp_); \
  293. } else emith_or_r_r_r(d, s1, s2); \
  294. } while (0)
  295. #define emith_or_r_r_r_lsr(d, s1, s2, lsrimm) do { \
  296. if (lsrimm) { \
  297. int tmp_ = rcache_get_tmp(); \
  298. emith_lsr(tmp_, s2, lsrimm); \
  299. emith_or_r_r_r(d, s1, tmp_); \
  300. rcache_free_tmp(tmp_); \
  301. } else emith_or_r_r_r(d, s1, s2); \
  302. } while (0)
  303. // _r_r_shift
  304. #define emith_or_r_r_lsl(d, s, lslimm) \
  305. emith_or_r_r_r_lsl(d, d, s, lslimm)
  306. #define emith_or_r_r_lsr(d, s, lsrimm) \
  307. emith_or_r_r_r_lsr(d, d, s, lsrimm)
  308. #define emith_eor_r_r_lsl(d, s, lslimm) do { \
  309. if (lslimm) { \
  310. int tmp_ = rcache_get_tmp(); \
  311. emith_lsl(tmp_, s, lslimm); \
  312. emith_eor_r_r(d, tmp_); \
  313. rcache_free_tmp(tmp_); \
  314. } else emith_eor_r_r(d, s); \
  315. } while (0)
  316. #define emith_eor_r_r_lsr(d, s, lsrimm) do { \
  317. if (lsrimm) { \
  318. int tmp_ = rcache_get_tmp(); \
  319. emith_lsr(tmp_, s, lsrimm); \
  320. emith_eor_r_r(d, tmp_); \
  321. rcache_free_tmp(tmp_); \
  322. } else emith_eor_r_r(d, s); \
  323. } while (0)
  324. // _r_imm
  325. #define emith_move_r_imm(r, imm) do { \
  326. EMIT_REX_IF(0, 0, r); \
  327. EMIT_OP(0xb8 + ((r)&7)); \
  328. EMIT(imm, u32); \
  329. } while (0)
  330. #define emith_move_r_ptr_imm(r, imm) do { \
  331. if ((uintptr_t)(imm) <= UINT32_MAX) \
  332. emith_move_r_imm(r, (uintptr_t)(imm)); \
  333. else { \
  334. EMIT_REX_IF(1, 0, r); \
  335. EMIT_OP(0xb8 + ((r)&7)); \
  336. EMIT((uintptr_t)(imm), uint64_t); \
  337. } \
  338. } while (0)
  339. #define emith_move_r_imm_s8_patchable(r, imm) do { \
  340. EMIT_REX_IF(0, 0, r); \
  341. EMIT_OP(0xb8 + ((r)&7)); \
  342. EMIT((s8)(imm), u32); \
  343. } while (0)
  344. #define emith_move_r_imm_s8_patch(ptr, imm) do { \
  345. u8 *ptr_ = ptr; \
  346. while ((*ptr_ & 0xf8) != 0xb8) ptr_++; \
  347. EMIT_PTR(ptr_ + 1, (s8)(imm), u32); \
  348. } while (0)
  349. #define emith_arith_r_imm(op, r, imm) do { \
  350. EMIT_REX_IF(0, 0, r); \
  351. EMIT_OP_MODRM64(0x81, 3, op, r); \
  352. EMIT(imm, u32); \
  353. } while (0)
  354. #define emith_add_r_imm(r, imm) \
  355. emith_arith_r_imm(0, r, imm)
  356. #define emith_or_r_imm(r, imm) \
  357. emith_arith_r_imm(1, r, imm)
  358. #define emith_adc_r_imm(r, imm) \
  359. emith_arith_r_imm(2, r, imm)
  360. #define emith_sbc_r_imm(r, imm) \
  361. emith_arith_r_imm(3, r, imm) // sbb
  362. #define emith_and_r_imm(r, imm) \
  363. emith_arith_r_imm(4, r, imm)
  364. #define emith_sub_r_imm(r, imm) \
  365. emith_arith_r_imm(5, r, imm)
  366. #define emith_eor_r_imm(r, imm) \
  367. emith_arith_r_imm(6, r, imm)
  368. #define emith_cmp_r_imm(r, imm) \
  369. emith_arith_r_imm(7, r, imm)
  370. #define emith_eor_r_imm_ptr(r, imm) do { \
  371. EMIT_REX_IF(1, 0, r); \
  372. EMIT_OP_MODRM64(0x81, 3, 6, r); \
  373. EMIT(imm, u32); \
  374. } while (0)
  375. #define emith_tst_r_imm(r, imm) do { \
  376. EMIT_REX_IF(0, 0, r); \
  377. EMIT_OP_MODRM64(0xf7, 3, 0, r); \
  378. EMIT(imm, u32); \
  379. } while (0)
  380. // fake
  381. #define emith_bic_r_imm(r, imm) \
  382. emith_arith_r_imm(4, r, ~(imm))
  383. // fake conditionals (using SJMP instead)
  384. #define emith_move_r_imm_c(cond, r, imm) \
  385. emith_move_r_imm(r, imm)
  386. #define emith_add_r_imm_c(cond, r, imm) \
  387. emith_add_r_imm(r, imm)
  388. #define emith_sub_r_imm_c(cond, r, imm) \
  389. emith_sub_r_imm(r, imm)
  390. #define emith_or_r_imm_c(cond, r, imm) \
  391. emith_or_r_imm(r, imm)
  392. #define emith_eor_r_imm_c(cond, r, imm) \
  393. emith_eor_r_imm(r, imm)
  394. #define emith_eor_r_imm_ptr_c(cond, r, imm) \
  395. emith_eor_r_imm_ptr(r, imm)
  396. #define emith_bic_r_imm_c(cond, r, imm) \
  397. emith_bic_r_imm(r, imm)
  398. #define emith_tst_r_imm_c(cond, r, imm) \
  399. emith_tst_r_imm(r, imm)
  400. #define emith_move_r_r_ptr_c(cond, d, s) \
  401. emith_move_r_r_ptr(d, s)
  402. #define emith_ror_c(cond, d, s, cnt) \
  403. emith_ror(d, s, cnt)
  404. #define emith_and_r_r_c(cond, d, s) \
  405. emith_and_r_r(d, s)
  406. #define emith_add_r_r_imm_c(cond, d, s, imm) \
  407. emith_add_r_r_imm(d, s, imm)
  408. #define emith_sub_r_r_imm_c(cond, d, s, imm) \
  409. emith_sub_r_r_imm(d, s, imm)
  410. #define emith_read8_r_r_r_c(cond, r, rs, rm) \
  411. emith_read8_r_r_r(r, rs, rm)
  412. #define emith_read8s_r_r_r_c(cond, r, rs, rm) \
  413. emith_read8s_r_r_r(r, rs, rm)
  414. #define emith_read16_r_r_r_c(cond, r, rs, rm) \
  415. emith_read16_r_r_r(r, rs, rm)
  416. #define emith_read16s_r_r_r_c(cond, r, rs, rm) \
  417. emith_read16s_r_r_r(r, rs, rm)
  418. #define emith_read_r_r_r_c(cond, r, rs, rm) \
  419. emith_read_r_r_r(r, rs, rm)
  420. #define emith_read_r_r_offs_c(cond, r, rs, offs) \
  421. emith_read_r_r_offs(r, rs, offs)
  422. #define emith_read_r_r_offs_ptr_c(cond, r, rs, offs) \
  423. emith_read_r_r_offs_ptr(r, rs, offs)
  424. #define emith_write_r_r_offs_c(cond, r, rs, offs) \
  425. emith_write_r_r_offs(r, rs, offs)
  426. #define emith_write_r_r_offs_ptr_c(cond, r, rs, offs) \
  427. emith_write_r_r_offs_ptr(r, rs, offs)
  428. #define emith_read8_r_r_offs_c(cond, r, rs, offs) \
  429. emith_read8_r_r_offs(r, rs, offs)
  430. #define emith_write8_r_r_offs_c(cond, r, rs, offs) \
  431. emith_write8_r_r_offs(r, rs, offs)
  432. #define emith_read16_r_r_offs_c(cond, r, rs, offs) \
  433. emith_read16_r_r_offs(r, rs, offs)
  434. #define emith_write16_r_r_offs_c(cond, r, rs, offs) \
  435. emith_write16_r_r_offs(r, rs, offs)
  436. #define emith_jump_reg_c(cond, r) \
  437. emith_jump_reg(r)
  438. #define emith_jump_ctx_c(cond, offs) \
  439. emith_jump_ctx(offs)
  440. #define emith_ret_c(cond) \
  441. emith_ret()
  442. // _r_r_imm - use lea
  443. #define emith_add_r_r_imm(d, s, imm) do { \
  444. EMIT_REX_IF(0, d, s); \
  445. emith_deref_modrm(0x8d, 2, d, s); \
  446. EMIT(imm, s32); \
  447. } while (0)
  448. #define emith_add_r_r_ptr_imm(d, s, imm) do { \
  449. EMIT_REX_IF(1, d, s); \
  450. emith_deref_modrm(0x8d, 2, d, s); \
  451. EMIT(imm, s32); \
  452. } while (0)
  453. #define emith_sub_r_r_imm(d, s, imm) do { \
  454. if (d != s) \
  455. emith_move_r_r(d, s); \
  456. if ((s32)(imm) != 0) \
  457. emith_sub_r_imm(d, imm); \
  458. } while (0)
  459. #define emith_and_r_r_imm(d, s, imm) do { \
  460. if (d != s) \
  461. emith_move_r_r(d, s); \
  462. if ((s32)(imm) != -1) \
  463. emith_and_r_imm(d, imm); \
  464. } while (0)
  465. #define emith_or_r_r_imm(d, s, imm) do { \
  466. if (d != s) \
  467. emith_move_r_r(d, s); \
  468. if ((s32)(imm) != 0) \
  469. emith_or_r_imm(d, imm); \
  470. } while (0)
  471. #define emith_eor_r_r_imm(d, s, imm) do { \
  472. if (d != s) \
  473. emith_move_r_r(d, s); \
  474. if ((s32)(imm) != 0) \
  475. emith_eor_r_imm(d, imm); \
  476. } while (0)
  477. // shift
  478. #define emith_shift(op, d, s, cnt) do { \
  479. if (d != s) \
  480. emith_move_r_r(d, s); \
  481. EMIT_REX_IF(0, 0, d); \
  482. EMIT_OP_MODRM64(0xc1, 3, op, d); \
  483. EMIT(cnt, u8); \
  484. } while (0)
  485. #define emith_lsl(d, s, cnt) \
  486. emith_shift(4, d, s, cnt)
  487. #define emith_lsr(d, s, cnt) \
  488. emith_shift(5, d, s, cnt)
  489. #define emith_asr(d, s, cnt) \
  490. emith_shift(7, d, s, cnt)
  491. #define emith_rol(d, s, cnt) \
  492. emith_shift(0, d, s, cnt)
  493. #define emith_ror(d, s, cnt) \
  494. emith_shift(1, d, s, cnt)
  495. #define emith_rolc(r) do { \
  496. EMIT_REX_IF(0, 0, r); \
  497. EMIT_OP_MODRM64(0xd1, 3, 2, r); \
  498. } while (0)
  499. #define emith_rorc(r) do { \
  500. EMIT_REX_IF(0, 0, r); \
  501. EMIT_OP_MODRM64(0xd1, 3, 3, r); \
  502. } while (0)
  503. // misc
  504. #define emith_push(r) do { \
  505. EMIT_REX_IF(0, 0, r); \
  506. EMIT_OP(0x50 + ((r)&7)); \
  507. } while (0)
  508. #define emith_push_imm(imm) do { \
  509. EMIT_OP(0x68); \
  510. EMIT(imm, u32); \
  511. } while (0)
  512. #define emith_pop(r) do { \
  513. EMIT_REX_IF(0, 0, r); \
  514. EMIT_OP(0x58 + ((r)&7)); \
  515. } while (0)
  516. #define emith_neg_r(r) do { \
  517. EMIT_REX_IF(0, 0, r); \
  518. EMIT_OP_MODRM64(0xf7, 3, 3, r); \
  519. } while (0)
  520. #define emith_clear_msb(d, s, count) do { \
  521. u32 t = (u32)-1; \
  522. t >>= count; \
  523. if (d != s) \
  524. emith_move_r_r(d, s); \
  525. emith_and_r_imm(d, t); \
  526. } while (0)
  527. #define emith_clear_msb_c(cond, d, s, count) do { \
  528. (void)(cond); \
  529. emith_clear_msb(d, s, count); \
  530. } while (0)
  531. #define emith_sext(d, s, bits) do { \
  532. emith_lsl(d, s, 32 - (bits)); \
  533. emith_asr(d, d, 32 - (bits)); \
  534. } while (0)
  535. #define emith_uext_ptr(r) /**/
  536. #define emith_setc(r) do { \
  537. assert(is_abcdx(r)); \
  538. EMIT_REX_IF(0, 0, r); \
  539. EMIT_OP_MODRM64(0x0f92, 3, 0, r); /* SETC r */ \
  540. } while (0)
  541. // XXX: stupid mess
  542. #define emith_mul_(op, dlo, dhi, s1, s2) do { \
  543. int rmr; \
  544. if (dlo != xAX && dhi != xAX && rcache_is_hreg_used(xAX)) \
  545. emith_push(xAX); \
  546. if (dlo != xDX && dhi != xDX && rcache_is_hreg_used(xDX)) \
  547. emith_push(xDX); \
  548. if ((s1) == xAX) \
  549. rmr = s2; \
  550. else if ((s2) == xAX) \
  551. rmr = s1; \
  552. else { \
  553. emith_move_r_r(xAX, s1); \
  554. rmr = s2; \
  555. } \
  556. EMIT_REX_IF(0, 0, rmr); \
  557. EMIT_OP_MODRM64(0xf7, 3, op, rmr); /* xMUL rmr */ \
  558. if (dlo != xAX) { \
  559. EMIT_REX_IF(0, 0, dlo); \
  560. EMIT_OP(0x90 + ((dlo)&7)); /* XCHG eax, dlo */ \
  561. } \
  562. if (dhi != xDX && dhi != -1 && !(dhi == xAX && dlo == xDX)) \
  563. emith_move_r_r(dhi, (dlo == xDX ? xAX : xDX)); \
  564. if (dlo != xDX && dhi != xDX && rcache_is_hreg_used(xDX)) \
  565. emith_pop(xDX); \
  566. if (dlo != xAX && dhi != xAX && rcache_is_hreg_used(xAX)) \
  567. emith_pop(xAX); \
  568. } while (0)
  569. #define emith_mul_u64(dlo, dhi, s1, s2) \
  570. emith_mul_(4, dlo, dhi, s1, s2) /* MUL */
  571. #define emith_mul_s64(dlo, dhi, s1, s2) \
  572. emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */
  573. #define emith_mul(d, s1, s2) do { \
  574. if (d == s1) { \
  575. EMIT_REX_IF(0, d, s2); \
  576. EMIT_OP_MODRM64(0x0faf, 3, d, s2); \
  577. } else if (d == s2) { \
  578. EMIT_REX_IF(0, d, s1); \
  579. EMIT_OP_MODRM64(0x0faf, 3, d, s1); \
  580. } else { \
  581. emith_move_r_r(d, s1); \
  582. EMIT_REX_IF(0, d, s2); \
  583. EMIT_OP_MODRM64(0x0faf, 3, d, s2); \
  584. } \
  585. } while (0)
  586. // (dlo,dhi) += signed(s1) * signed(s2)
  587. #define emith_mula_s64(dlo, dhi, s1, s2) do { \
  588. emith_push(dhi); \
  589. emith_push(dlo); \
  590. emith_mul_(5, dlo, dhi, s1, s2); \
  591. EMIT_REX_IF(0, dlo, xSP); \
  592. emith_deref_modrm(0x03, 0, dlo, xSP); /* add dlo, [xsp] */ \
  593. EMIT_REX_IF(0, dhi, xSP); \
  594. emith_deref_modrm(0x13, 1, dhi, xSP); /* adc dhi, [xsp+{4,8}] */ \
  595. EMIT(sizeof(void *), u8); \
  596. emith_add_r_r_ptr_imm(xSP, xSP, sizeof(void *) * 2); \
  597. } while (0)
  598. // "flag" instructions are the same
  599. #define emith_adcf_r_imm emith_adc_r_imm
  600. #define emith_subf_r_imm emith_sub_r_imm
  601. #define emith_addf_r_r emith_add_r_r
  602. #define emith_subf_r_r emith_sub_r_r
  603. #define emith_adcf_r_r emith_adc_r_r
  604. #define emith_sbcf_r_r emith_sbc_r_r
  605. #define emith_eorf_r_r emith_eor_r_r
  606. #define emith_negcf_r_r emith_negc_r_r
  607. #define emith_subf_r_r_imm emith_sub_r_r_imm
  608. #define emith_addf_r_r_r emith_add_r_r_r
  609. #define emith_subf_r_r_r emith_sub_r_r_r
  610. #define emith_adcf_r_r_r emith_adc_r_r_r
  611. #define emith_sbcf_r_r_r emith_sbc_r_r_r
  612. #define emith_eorf_r_r_r emith_eor_r_r_r
  613. #define emith_addf_r_r_r_lsr emith_add_r_r_r_lsr
  614. #define emith_lslf emith_lsl
  615. #define emith_lsrf emith_lsr
  616. #define emith_asrf emith_asr
  617. #define emith_rolf emith_rol
  618. #define emith_rorf emith_ror
  619. #define emith_rolcf emith_rolc
  620. #define emith_rorcf emith_rorc
  621. #define emith_deref_modrm(op, m, r, rs) do { \
  622. if (((rs) & 7) == 5 && m == 0) { /* xBP,xR13 not in mod 0, use mod 1 */\
  623. EMIT_OP_MODRM64(op, 1, r, rs); \
  624. EMIT(0, u8); \
  625. } else if (((rs) & 7) == 4) { /* xSP,xR12 must use SIB */ \
  626. EMIT_OP_MODRM64(op, m, r, 4); \
  627. EMIT_SIB64(0, 4, rs); \
  628. } else \
  629. EMIT_OP_MODRM64(op, m, r, rs); \
  630. } while (0)
  631. #define emith_deref_op(op, r, rs, offs) do { \
  632. /* mov r <-> [ebp+#offs] */ \
  633. if ((offs) == 0) { \
  634. emith_deref_modrm(op, 0, r, rs); \
  635. } else if ((s32)(offs) < -0x80 || (s32)(offs) >= 0x80) { \
  636. emith_deref_modrm(op, 2, r, rs); \
  637. EMIT(offs, u32); \
  638. } else { \
  639. emith_deref_modrm(op, 1, r, rs); \
  640. EMIT((u8)offs, u8); \
  641. } \
  642. } while (0)
  643. #define is_abcdx(r) !((r) & ~0x3)
  644. #define emith_read_r_r_offs(r, rs, offs) do { \
  645. EMIT_REX_IF(0, r, rs); \
  646. emith_deref_op(0x8b, r, rs, offs); \
  647. } while (0)
  648. #define emith_read_r_r_offs_ptr(r, rs, offs) do { \
  649. EMIT_REX_IF(1, r, rs); \
  650. emith_deref_op(0x8b, r, rs, offs); \
  651. } while (0)
  652. #define emith_write_r_r_offs(r, rs, offs) do { \
  653. EMIT_REX_IF(0, r, rs); \
  654. emith_deref_op(0x89, r, rs, offs); \
  655. } while (0)
  656. #define emith_write_r_r_offs_ptr(r, rs, offs) do { \
  657. EMIT_REX_IF(1, r, rs); \
  658. emith_deref_op(0x89, r, rs, offs); \
  659. } while (0)
  660. #define emith_read8_r_r_offs(r, rs, offs) do { \
  661. EMIT_REX_IF(0, r, rs); \
  662. emith_deref_op(0x0fb6, r, rs, offs); \
  663. } while (0)
  664. #define emith_read8s_r_r_offs(r, rs, offs) do { \
  665. EMIT_REX_IF(0, r, rs); \
  666. emith_deref_op(0x0fbe, r, rs, offs); \
  667. } while (0)
  668. #define emith_write8_r_r_offs(r, rs, offs) do {\
  669. EMIT_REX_IF(0, r, rs); \
  670. emith_deref_op(0x88, r, rs, offs); \
  671. } while (0)
  672. #define emith_read16_r_r_offs(r, rs, offs) do { \
  673. EMIT_REX_IF(0, r, rs); \
  674. emith_deref_op(0x0fb7, r, rs, offs); \
  675. } while (0)
  676. #define emith_read16s_r_r_offs(r, rs, offs) do { \
  677. EMIT_REX_IF(0, r, rs); \
  678. emith_deref_op(0x0fbf, r, rs, offs); \
  679. } while (0)
  680. #define emith_write16_r_r_offs(r, rs, offs) do { \
  681. EMIT(0x66, u8); /* Intel SDM Vol 2a: REX must be closest to opcode */ \
  682. EMIT_REX_IF(0, r, rs); \
  683. emith_deref_op(0x89, r, rs, offs); \
  684. } while (0)
  685. #define emith_read8_r_r_r(r, rs, rm) do { \
  686. EMIT_XREX_IF(0, r, rm, rs); \
  687. EMIT_OP_MODRM64(0x0fb6, 0, r, 4); \
  688. EMIT_SIB64(0, rs, rm); /* mov r, [rm + rs * 1] */ \
  689. } while (0)
  690. #define emith_read8s_r_r_r(r, rs, rm) do { \
  691. EMIT_XREX_IF(0, r, rm, rs); \
  692. EMIT_OP_MODRM64(0x0fbe, 0, r, 4); \
  693. EMIT_SIB64(0, rs, rm); /* mov r, [rm + rs * 1] */ \
  694. } while (0)
  695. #define emith_read16_r_r_r(r, rs, rm) do { \
  696. EMIT_XREX_IF(0, r, rm, rs); \
  697. EMIT_OP_MODRM64(0x0fb7, 0, r, 4); \
  698. EMIT_SIB64(0, rs, rm); /* mov r, [rm + rs * 1] */ \
  699. } while (0)
  700. #define emith_read16s_r_r_r(r, rs, rm) do { \
  701. EMIT_XREX_IF(0, r, rm, rs); \
  702. EMIT_OP_MODRM64(0x0fbf, 0, r, 4); \
  703. EMIT_SIB64(0, rs, rm); /* mov r, [rm + rs * 1] */ \
  704. } while (0)
  705. #define emith_read_r_r_r(r, rs, rm) do { \
  706. EMIT_XREX_IF(0, r, rm, rs); \
  707. EMIT_OP_MODRM64(0x8b, 0, r, 4); \
  708. EMIT_SIB64(0, rs, rm); /* mov r, [rm + rs * 1] */ \
  709. } while (0)
  710. #define emith_read_r_r_r_ptr(r, rs, rm) do { \
  711. EMIT_XREX_IF(1, r, rm, rs); \
  712. EMIT_OP_MODRM64(0x8b, 0, r, 4); \
  713. EMIT_SIB64(0, rs, rm); /* mov r, [rm + rs * 1] */ \
  714. } while (0)
  715. #define emith_write_r_r_r(r, rs, rm) do { \
  716. EMIT_XREX_IF(0, r, rm, rs); \
  717. EMIT_OP_MODRM64(0x89, 0, r, 4); \
  718. EMIT_SIB64(0, rs, rm); /* mov [rm + rs * 1], r */ \
  719. } while (0)
  720. #define emith_write_r_r_r_ptr(r, rs, rm) do { \
  721. EMIT_XREX_IF(1, r, rm, rs); \
  722. EMIT_OP_MODRM64(0x89, 0, r, 4); \
  723. EMIT_SIB64(0, rs, rm); /* mov [rm + rs * 1], r */ \
  724. } while (0)
  725. #define emith_ctx_read(r, offs) \
  726. emith_read_r_r_offs(r, CONTEXT_REG, offs)
  727. #define emith_ctx_read_c(cond, r, offs) \
  728. emith_ctx_read(r, offs)
  729. #define emith_ctx_read_ptr(r, offs) do { \
  730. EMIT_REX_IF(1, r, CONTEXT_REG); \
  731. emith_deref_op(0x8b, r, CONTEXT_REG, offs); \
  732. } while (0)
  733. #define emith_ctx_write(r, offs) \
  734. emith_write_r_r_offs(r, CONTEXT_REG, offs)
  735. #define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
  736. int r_ = r, offs_ = offs, cnt_ = cnt; \
  737. for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
  738. emith_ctx_read(r_, offs_); \
  739. } while (0)
  740. #define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
  741. int r_ = r, offs_ = offs, cnt_ = cnt; \
  742. for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
  743. emith_ctx_write(r_, offs_); \
  744. } while (0)
  745. #define emith_ret_to_ctx(offs) do { \
  746. int tmp_ = rcache_get_tmp(); \
  747. emith_pop(tmp_); \
  748. emith_ctx_write(tmp_, offs); \
  749. rcache_free_tmp(tmp_); \
  750. } while (0)
  751. #define emith_jump(ptr) do { \
  752. u32 disp = (u8 *)(ptr) - ((u8 *)tcache_ptr + 5); \
  753. EMIT_OP(0xe9); \
  754. EMIT(disp, u32); \
  755. } while (0)
  756. #define emith_jump_patchable(target) \
  757. emith_jump(target)
  758. #define emith_jump_cond(cond, ptr) do { \
  759. u32 disp = (u8 *)(ptr) - ((u8 *)tcache_ptr + 6); \
  760. EMIT_OP(0x0f80 | (cond)); \
  761. EMIT(disp, u32); \
  762. } while (0)
  763. #define emith_jump_cond_inrange(ptr) !0
  764. #define emith_jump_cond_patchable(cond, target) \
  765. emith_jump_cond(cond, target)
  766. #define emith_jump_patch(ptr, target, pos) do { \
  767. u32 disp_ = (u8 *)(target) - ((u8 *)(ptr) + 4); \
  768. u32 offs_ = (*(u8 *)(ptr) == 0x0f) ? 2 : 1; \
  769. EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
  770. if ((void *)(pos) != NULL) *(u8 **)(pos) = (u8 *)ptr + offs_; \
  771. } while (0)
  772. #define emith_jump_patch_size() 4
  773. #define emith_jump_patch_inrange(ptr, target) !0
  774. #define emith_jump_at(ptr, target) do { \
  775. u32 disp_ = (u8 *)(target) - ((u8 *)(ptr) + 5); \
  776. EMIT_PTR(ptr, 0xe9, u8); \
  777. EMIT_PTR((u8 *)(ptr) + 1, disp_, u32); \
  778. } while (0)
  779. #define emith_jump_at_size() 5
  780. #define emith_call(ptr) do { \
  781. u32 disp = (u8 *)(ptr) - ((u8 *)tcache_ptr + 5); \
  782. EMIT_OP(0xe8); \
  783. EMIT(disp, u32); \
  784. } while (0)
  785. #define emith_call_cond(cond, ptr) \
  786. emith_call(ptr)
  787. #define emith_call_reg(r) \
  788. EMIT_OP_MODRM(0xff, 3, 2, r)
  789. #define emith_call_ctx(offs) do { \
  790. EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
  791. EMIT(offs, u32); \
  792. } while (0)
  793. #define emith_call_cleanup() \
  794. emith_add_r_r_ptr_imm(xSP, xSP, sizeof(void *)); // remove return addr
  795. #define emith_ret() \
  796. EMIT_OP(0xc3)
  797. #define emith_add_r_ret(r) do { \
  798. EMIT_REX_IF(1, r, xSP); \
  799. emith_deref_modrm(0x03, 0, r, xSP); /* add r, [xsp] */ \
  800. } while (0)
  801. #define emith_jump_reg(r) \
  802. EMIT_OP_MODRM(0xff, 3, 4, r)
  803. #define emith_jump_ctx(offs) do { \
  804. EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
  805. EMIT(offs, u32); \
  806. } while (0)
  807. #define emith_push_ret(r) do { \
  808. int r_ = (r >= 0 ? r : xSI); \
  809. emith_push(r_); /* always push to align */ \
  810. emith_add_r_r_ptr_imm(xSP, xSP, -8*4); /* args shadow space */ \
  811. } while (0)
  812. #define emith_pop_and_ret(r) do { \
  813. int r_ = (r >= 0 ? r : xSI); \
  814. emith_add_r_r_ptr_imm(xSP, xSP, 8*4); /* args shadow space */ \
  815. emith_pop(r_); \
  816. emith_ret(); \
  817. } while (0)
  818. #define EMITH_JMP_START(cond) { \
  819. u8 *cond_ptr; \
  820. JMP8_POS(cond_ptr)
  821. #define EMITH_JMP_END(cond) \
  822. JMP8_EMIT(cond, cond_ptr); \
  823. }
  824. #define EMITH_JMP3_START(cond) { \
  825. u8 *cond_ptr, *else_ptr; \
  826. JMP8_POS(cond_ptr)
  827. #define EMITH_JMP3_MID(cond) \
  828. JMP8_POS(else_ptr); \
  829. JMP8_EMIT(cond, cond_ptr);
  830. #define EMITH_JMP3_END() \
  831. JMP8_EMIT_NC(else_ptr); \
  832. }
  833. // "simple" jump (no more than a few insns)
  834. // ARM will use conditional instructions here
  835. #define EMITH_SJMP_START EMITH_JMP_START
  836. #define EMITH_SJMP_END EMITH_JMP_END
  837. #define EMITH_SJMP3_START EMITH_JMP3_START
  838. #define EMITH_SJMP3_MID EMITH_JMP3_MID
  839. #define EMITH_SJMP3_END EMITH_JMP3_END
  840. #define EMITH_SJMP2_START(cond) \
  841. EMITH_SJMP3_START(cond)
  842. #define EMITH_SJMP2_MID(cond) \
  843. EMITH_SJMP3_MID(cond)
  844. #define EMITH_SJMP2_END(cond) \
  845. EMITH_SJMP3_END()
  846. #define EMITH_HINT_COND(cond) /**/
  847. #define emith_pass_arg_r(arg, reg) do { \
  848. int rd = 7; \
  849. host_arg2reg(rd, arg); \
  850. emith_move_r_r_ptr(rd, reg); \
  851. } while (0)
  852. #define emith_pass_arg_imm(arg, imm) do { \
  853. int rd = 7; \
  854. host_arg2reg(rd, arg); \
  855. emith_move_r_imm(rd, imm); \
  856. } while (0)
  857. #define host_instructions_updated(base, end) (void)(base),(void)(end)
  858. #define emith_update_cache() /**/
  859. // NB this MUST be <0x40000000 to avoid overflow in address calculations
  860. #define emith_rw_offs_max() 0xfffffff // for better perfomance: <0x10000000
  861. #ifdef __x86_64__
  862. #define HOST_REGS 16
  863. #define PTR_SCALE 3
  864. #define EMIT_XREX_IF(w, r, rm, rs) do { \
  865. int xr_ = (r) > 7 ? 1 : 0; \
  866. int xb_ = (rm) > 7 ? 1 : 0; \
  867. int xx_ = (rs) > 7 ? 1 : 0; \
  868. if ((w) | xr_ | xx_ | xb_) \
  869. EMIT_REX(w, xr_, xx_, xb_); \
  870. } while (0)
  871. #define EMIT_REX_IF(w, r, rm) \
  872. EMIT_XREX_IF(w, r, rm, 0)
  873. #ifndef _WIN32
  874. // SystemV ABI conventions:
  875. // rbx,rbp,r12-r15 are preserved, rax,rcx,rdx,rsi,rdi,r8-r11 are temporaries
  876. // parameters in rdi,rsi,rdx,rcx,r8,r9, return values in rax,rdx
  877. #define PARAM_REGS { xDI, xSI, xDX, xCX, xR8, xR9 }
  878. #define PRESERVED_REGS { xR12, xR13, xR14, xR15, xBX, xBP }
  879. #define TEMPORARY_REGS { xAX, xR10, xR11 }
  880. #define STATIC_SH2_REGS { SHR_SR,xBX , SHR_R0,xR15 }
  881. #define host_arg2reg(rd, arg) \
  882. switch (arg) { \
  883. case 0: rd = xDI; break; \
  884. case 1: rd = xSI; break; \
  885. case 2: rd = xDX; break; \
  886. default: rd = xCX; break; \
  887. }
  888. #define emith_sh2_drc_entry() do { \
  889. emith_push(xBX); \
  890. emith_push(xBP); \
  891. emith_push(xR12); \
  892. emith_push(xR13); \
  893. emith_push(xR14); \
  894. emith_push(xR15); \
  895. emith_push(xSI); /* to align */ \
  896. } while (0)
  897. #define emith_sh2_drc_exit() do { \
  898. emith_pop(xSI); \
  899. emith_pop(xR15); \
  900. emith_pop(xR14); \
  901. emith_pop(xR13); \
  902. emith_pop(xR12); \
  903. emith_pop(xBP); \
  904. emith_pop(xBX); \
  905. emith_ret(); \
  906. } while (0)
  907. #else // _WIN32
  908. // M$ ABI conventions:
  909. // rbx,rbp,rsi,rdi,r12-r15 are preserved, rcx,rdx,rax,r8,r9,r10,r11 temporaries
  910. // parameters in rcx,rdx,r8,r9, return values in rax,rdx
  911. #define PARAM_REGS { xCX, xDX, xR8, xR9 }
  912. #define PRESERVED_REGS { xSI, xDI, xR12, xR13, xR14, xR15, xBX, xBP }
  913. #define TEMPORARY_REGS { xAX, xR10, xR11 }
  914. #define STATIC_SH2_REGS { SHR_SR,xBX , SHR_R(0),xR15 , SHR_R(1),xR14 }
  915. #define host_arg2reg(rd, arg) \
  916. switch (arg) { \
  917. case 0: rd = xCX; break; \
  918. case 1: rd = xDX; break; \
  919. case 2: rd = xR8; break; \
  920. default: rd = xR9; break; \
  921. }
  922. #define emith_sh2_drc_entry() do { \
  923. emith_push(xBX); \
  924. emith_push(xBP); \
  925. emith_push(xR12); \
  926. emith_push(xR13); \
  927. emith_push(xR14); \
  928. emith_push(xR15); \
  929. emith_push(xSI); \
  930. emith_push(xDI); \
  931. emith_add_r_r_ptr_imm(xSP, xSP, -8*5); /* align + args shadow space */ \
  932. } while (0)
  933. #define emith_sh2_drc_exit() do { \
  934. emith_add_r_r_ptr_imm(xSP, xSP, 8*5); \
  935. emith_pop(xDI); \
  936. emith_pop(xSI); \
  937. emith_pop(xR15); \
  938. emith_pop(xR14); \
  939. emith_pop(xR13); \
  940. emith_pop(xR12); \
  941. emith_pop(xBP); \
  942. emith_pop(xBX); \
  943. emith_ret(); \
  944. } while (0)
  945. #endif // _WIN32
  946. #else // !__x86_64__
  947. #define HOST_REGS 8
  948. #define PTR_SCALE 2
  949. #define EMIT_REX_IF(w, r, rm) do { \
  950. assert((u32)(r) < 8u); \
  951. assert((u32)(rm) < 8u); \
  952. } while (0)
  953. #define EMIT_XREX_IF(w, r, rs, rm) do { \
  954. assert((u32)(r) < 8u); \
  955. assert((u32)(rs) < 8u); \
  956. assert((u32)(rm) < 8u); \
  957. } while (0)
  958. // MS/SystemV ABI: ebx,esi,edi,ebp are preserved, eax,ecx,edx are temporaries
  959. // DRC uses REGPARM to pass upto 3 parameters in registers eax,ecx,edx.
  960. // To avoid conflicts with param passing ebx must be declared temp here.
  961. #define PARAM_REGS { xAX, xDX, xCX }
  962. #define PRESERVED_REGS { xSI, xDI, xBP }
  963. #define TEMPORARY_REGS { xBX }
  964. #define STATIC_SH2_REGS { SHR_SR,xDI , SHR_R0,xSI }
  965. #define host_arg2reg(rd, arg) \
  966. switch (arg) { \
  967. case 0: rd = xAX; break; \
  968. case 1: rd = xDX; break; \
  969. case 2: rd = xCX; break; \
  970. default: rd = xBX; break; \
  971. }
  972. #define emith_sh2_drc_entry() do { \
  973. emith_push(xBX); \
  974. emith_push(xBP); \
  975. emith_push(xSI); \
  976. emith_push(xDI); \
  977. } while (0)
  978. #define emith_sh2_drc_exit() do { \
  979. emith_pop(xDI); \
  980. emith_pop(xSI); \
  981. emith_pop(xBP); \
  982. emith_pop(xBX); \
  983. emith_ret(); \
  984. } while (0)
  985. #endif
  986. #define emith_save_caller_regs(mask) do { \
  987. int _c; u32 _m = mask & 0xfc7; /* AX, CX, DX, SI, DI, 8, 9, 10, 11 */ \
  988. if (__builtin_parity(_m) == 1) _m |= 0x8; /* BX for ABI align */ \
  989. for (_c = HOST_REGS-1; _m && _c >= 0; _m &= ~(1 << _c), _c--) \
  990. if (_m & (1 << _c)) emith_push(_c); \
  991. } while (0)
  992. #define emith_restore_caller_regs(mask) do { \
  993. int _c; u32 _m = mask & 0xfc7; \
  994. if (__builtin_parity(_m) == 1) _m |= 0x8; /* BX for ABI align */ \
  995. for (_c = 0; _m && _c < HOST_REGS; _m &= ~(1 << _c), _c++) \
  996. if (_m & (1 << _c)) emith_pop(_c); \
  997. } while (0)
  998. #define emith_sh2_rcall(a, tab, func, mask) do { \
  999. emith_lsr(mask, a, SH2_READ_SHIFT); \
  1000. EMIT_XREX_IF(1, tab, tab, mask); \
  1001. EMIT_OP_MODRM64(0x8d, 0, tab, 4); \
  1002. EMIT_SIB64(PTR_SCALE, mask, tab); /* lea tab, [tab + mask * {4,8}] */ \
  1003. EMIT_XREX_IF(1, tab, tab, mask); \
  1004. EMIT_OP_MODRM64(0x8d, 0, tab, 4); \
  1005. EMIT_SIB64(PTR_SCALE, mask, tab); /* lea tab, [tab + mask * {4,8}] */ \
  1006. EMIT_REX_IF(1, func, tab); \
  1007. emith_deref_modrm(0x8b, 0, func, tab); /* mov func, [tab] */ \
  1008. EMIT_REX_IF(0, mask, tab); \
  1009. emith_deref_modrm(0x8b, 1, mask, tab); \
  1010. EMIT(1 << PTR_SCALE, u8); /* mov mask, [tab + {4,8}] */ \
  1011. emith_add_r_r_ptr(func, func); \
  1012. } while (0)
  1013. #define emith_sh2_wcall(a, val, tab, func) do { \
  1014. int arg2_; \
  1015. host_arg2reg(arg2_, 2); \
  1016. emith_lsr(func, a, SH2_WRITE_SHIFT); /* tmp = a >> WRT_SHIFT */ \
  1017. EMIT_XREX_IF(1, func, tab, func); \
  1018. EMIT_OP_MODRM64(0x8b, 0, func, 4); \
  1019. EMIT_SIB64(PTR_SCALE, func, tab); /* mov tmp, [tab + tmp * {4,8}] */ \
  1020. emith_move_r_r_ptr(arg2_, CONTEXT_REG); \
  1021. emith_jump_reg(func); \
  1022. } while (0)
  1023. #define emith_sh2_dtbf_loop() do { \
  1024. u8 *jmp0; /* negative cycles check */ \
  1025. u8 *jmp1; /* unsinged overflow check */ \
  1026. int cr, rn; \
  1027. int tmp_ = rcache_get_tmp(); \
  1028. cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
  1029. rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
  1030. emith_sub_r_imm(rn, 1); \
  1031. emith_sub_r_imm(cr, (cycles+1) << 12); \
  1032. cycles = 0; \
  1033. emith_asr(tmp_, cr, 2+12); \
  1034. JMP8_POS(jmp0); /* no negative cycles */ \
  1035. emith_move_r_imm(tmp_, 0); \
  1036. JMP8_EMIT(ICOND_JNS, jmp0); \
  1037. emith_and_r_imm(cr, 0xffe); \
  1038. emith_subf_r_r(rn, tmp_); \
  1039. JMP8_POS(jmp1); /* no overflow */ \
  1040. emith_neg_r(rn); /* count left */ \
  1041. emith_lsl(rn, rn, 2+12); \
  1042. emith_or_r_r(cr, rn); \
  1043. emith_or_r_imm(cr, 1); \
  1044. emith_move_r_imm(rn, 0); \
  1045. JMP8_EMIT(ICOND_JA, jmp1); \
  1046. rcache_free_tmp(tmp_); \
  1047. } while (0)
  1048. #define emith_sh2_delay_loop(cycles, reg) do { \
  1049. int sr = rcache_get_reg(SHR_SR, RC_GR_RMW, NULL); \
  1050. int t1 = rcache_get_tmp(); \
  1051. int t2 = rcache_get_tmp(); \
  1052. int t3 = rcache_get_tmp(); \
  1053. if (t3 == xAX) { t3 = t1; t1 = xAX; } /* for MUL */ \
  1054. if (t3 == xDX) { t3 = t2; t2 = xDX; } \
  1055. /* if (sr < 0) return */ \
  1056. emith_asrf(t2, sr, 12); \
  1057. EMITH_JMP_START(DCOND_LE); \
  1058. /* turns = sr.cycles / cycles */ \
  1059. emith_move_r_imm(t3, (u32)((1ULL<<32) / (cycles)) + 1); \
  1060. emith_mul_u64(t1, t2, t2, t3); /* multiply by 1/x */ \
  1061. rcache_free_tmp(t3); \
  1062. if (reg >= 0) { \
  1063. /* if (reg <= turns) turns = reg-1 */ \
  1064. t3 = rcache_get_reg(reg, RC_GR_RMW, NULL); \
  1065. emith_cmp_r_r(t3, t2); \
  1066. EMITH_SJMP_START(DCOND_HI); \
  1067. emith_sub_r_r_imm_c(DCOND_LS, t2, t3, 1); \
  1068. EMITH_SJMP_END(DCOND_HI); \
  1069. /* if (reg <= 1) turns = 0 */ \
  1070. emith_cmp_r_imm(t3, 1); \
  1071. EMITH_SJMP_START(DCOND_HI); \
  1072. emith_move_r_imm_c(DCOND_LS, t2, 0); \
  1073. EMITH_SJMP_END(DCOND_HI); \
  1074. /* reg -= turns */ \
  1075. emith_sub_r_r(t3, t2); \
  1076. } \
  1077. /* sr.cycles -= turns * cycles; */ \
  1078. emith_move_r_imm(t1, cycles); \
  1079. emith_mul_u64(t1, t2, t1, t2); \
  1080. emith_sub_r_r_r_lsl(sr, sr, t1, 12); \
  1081. EMITH_JMP_END(DCOND_LE); \
  1082. rcache_free_tmp(t1); \
  1083. rcache_free_tmp(t2); \
  1084. } while (0)
  1085. #define emith_write_sr(sr, srcr) do { \
  1086. int tmp_ = rcache_get_tmp(); \
  1087. emith_clear_msb(tmp_, srcr, 22); \
  1088. emith_bic_r_imm(sr, 0x3ff); \
  1089. emith_or_r_r(sr, tmp_); \
  1090. rcache_free_tmp(tmp_); \
  1091. } while (0)
  1092. #define emith_carry_to_t(sr, is_sub) do { \
  1093. emith_rorc(sr); \
  1094. emith_rol(sr, sr, 1); \
  1095. } while (0)
  1096. #define emith_t_to_carry(sr, is_sub) do { \
  1097. emith_ror(sr, sr, 1); \
  1098. emith_rol(sr, sr, 1); \
  1099. } while (0)
  1100. #define emith_tpop_carry(sr, is_sub) \
  1101. emith_lsr(sr, sr, 1)
  1102. #define emith_tpush_carry(sr, is_sub) \
  1103. emith_adc_r_r(sr, sr)
  1104. /*
  1105. * T = carry(Rn = (Rn << 1) | T)
  1106. * if Q
  1107. * t = carry(Rn += Rm)
  1108. * else
  1109. * t = carry(Rn -= Rm)
  1110. * T = !(T ^ t)
  1111. */
  1112. #define emith_sh2_div1_step(rn, rm, sr) do { \
  1113. u8 *jmp0, *jmp1; \
  1114. int tmp_ = rcache_get_tmp(); \
  1115. emith_tpop_carry(sr, 0); /* Rn = 2*Rn+T */\
  1116. emith_adcf_r_r_r(rn, rn, rn); \
  1117. emith_tpush_carry(sr, 0); /* T = C1 */ \
  1118. emith_eor_r_r(tmp_, tmp_); \
  1119. emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
  1120. JMP8_POS(jmp0); /* je do_sub */ \
  1121. emith_add_r_r(rn, rm); \
  1122. JMP8_POS(jmp1); /* jmp done */ \
  1123. JMP8_EMIT(ICOND_JE, jmp0); /* do_sub: */ \
  1124. emith_sub_r_r(rn, rm); \
  1125. JMP8_EMIT_NC(jmp1); /* done: */ \
  1126. emith_adc_r_r(tmp_, tmp_); \
  1127. emith_eor_r_r(sr, tmp_);/* T = !(C1^C2) */\
  1128. emith_eor_r_imm(sr, T); \
  1129. rcache_free_tmp(tmp_); \
  1130. } while (0)
  1131. /* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
  1132. #define emith_sh2_macl(ml, mh, rn, rm, sr) do { \
  1133. emith_tst_r_imm(sr, S); \
  1134. EMITH_SJMP_START(DCOND_EQ); \
  1135. /* MACH top 16 bits unused if saturated. sign ext for overfl detect */ \
  1136. emith_sext(mh, mh, 16); \
  1137. EMITH_SJMP_END(DCOND_EQ); \
  1138. emith_mula_s64(ml, mh, rn, rm); \
  1139. emith_tst_r_imm(sr, S); \
  1140. EMITH_SJMP_START(DCOND_EQ); \
  1141. /* overflow if top 17 bits of MACH aren't all 1 or 0 */ \
  1142. /* to check: add MACH[15] to MACH[31:16]. this is 0 if no overflow */ \
  1143. emith_asrf(rn, mh, 16); /* sum = (MACH>>16) + ((MACH>>15)&1) */ \
  1144. emith_adcf_r_imm(rn, 0); /* (MACH>>15) is in carry after shift */ \
  1145. EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> ov */ \
  1146. emith_move_r_imm_c(DCOND_NE, ml, 0x0000); /* -overflow */ \
  1147. emith_move_r_imm_c(DCOND_NE, mh, 0x8000); \
  1148. EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> +ovl */ \
  1149. emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0xffffffff */ \
  1150. emith_sub_r_imm_c(DCOND_GT, mh, 1); /* 0x00007fff */ \
  1151. EMITH_SJMP_END(DCOND_LE); \
  1152. EMITH_SJMP_END(DCOND_EQ); \
  1153. EMITH_SJMP_END(DCOND_EQ); \
  1154. } while (0)
  1155. /* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
  1156. #define emith_sh2_macw(ml, mh, rn, rm, sr) do { \
  1157. emith_tst_r_imm(sr, S); \
  1158. EMITH_SJMP_START(DCOND_EQ); \
  1159. /* XXX: MACH should be untouched when S is set? */ \
  1160. emith_asr(mh, ml, 31); /* sign ext MACL to MACH for ovrfl check */ \
  1161. EMITH_SJMP_END(DCOND_EQ); \
  1162. emith_mula_s64(ml, mh, rn, rm); \
  1163. emith_tst_r_imm(sr, S); \
  1164. EMITH_SJMP_START(DCOND_EQ); \
  1165. /* overflow if top 33 bits of MACH:MACL aren't all 1 or 0 */ \
  1166. /* to check: add MACL[31] to MACH. this is 0 if no overflow */ \
  1167. emith_lsr(rn, ml, 31); \
  1168. emith_addf_r_r(rn, mh); /* sum = MACH + ((MACL>>31)&1) */ \
  1169. EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> overflow */ \
  1170. /* XXX: LSB signalling only in SH1, or in SH2 too? */ \
  1171. emith_move_r_imm_c(DCOND_NE, mh, 0x00000001); /* LSB of MACH */ \
  1172. emith_move_r_imm_c(DCOND_NE, ml, 0x80000000); /* negative ovrfl */ \
  1173. EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> positive ovrfl */ \
  1174. emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0x7fffffff */ \
  1175. EMITH_SJMP_END(DCOND_LE); \
  1176. EMITH_SJMP_END(DCOND_EQ); \
  1177. EMITH_SJMP_END(DCOND_EQ); \
  1178. } while (0)
  1179. #define emith_pool_check() /**/
  1180. #define emith_pool_commit(j) /**/
  1181. #define emith_insn_ptr() ((u8 *)tcache_ptr)
  1182. #define emith_flush() /**/
  1183. #ifdef T
  1184. // T bit handling
  1185. #define emith_invert_cond(cond) \
  1186. ((cond) ^ 1)
  1187. static void emith_clr_t_cond(int sr)
  1188. {
  1189. emith_bic_r_imm(sr, T);
  1190. }
  1191. static void emith_set_t_cond(int sr, int cond)
  1192. {
  1193. EMITH_SJMP_START(emith_invert_cond(cond));
  1194. emith_or_r_imm_c(cond, sr, T);
  1195. EMITH_SJMP_END(emith_invert_cond(cond));
  1196. }
  1197. #define emith_get_t_cond() -1
  1198. #define emith_sync_t(sr) ((void)sr)
  1199. #define emith_invalidate_t()
  1200. static void emith_set_t(int sr, int val)
  1201. {
  1202. if (val)
  1203. emith_or_r_imm(sr, T);
  1204. else
  1205. emith_bic_r_imm(sr, T);
  1206. }
  1207. static int emith_tst_t(int sr, int tf)
  1208. {
  1209. emith_tst_r_imm(sr, T);
  1210. return tf ? DCOND_NE: DCOND_EQ;
  1211. }
  1212. #endif