videoport.c 31 KB

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  1. /*
  2. * PicoDrive
  3. * (c) Copyright Dave, 2004
  4. * (C) notaz, 2006-2009
  5. * (C) kub, 2020
  6. *
  7. * This work is licensed under the terms of MAME license.
  8. * See COPYING file in the top-level directory.
  9. */
  10. #include "pico_int.h"
  11. #define NEED_DMA_SOURCE
  12. #include "memory.h"
  13. extern const unsigned char hcounts_32[], hcounts_40[];
  14. extern const unsigned char vdpcyc2sl_32_bl[], vdpcyc2sl_40_bl[];
  15. extern const unsigned char vdpcyc2sl_32[], vdpcyc2sl_40[];
  16. extern const unsigned short vdpsl2cyc_32_bl[], vdpsl2cyc_40_bl[];
  17. extern const unsigned short vdpsl2cyc_32[], vdpsl2cyc_40[];
  18. static int blankline; // display disabled for this line
  19. unsigned SATaddr, SATmask; // VRAM addr of sprite attribute table
  20. int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned int *mask) = NULL;
  21. /* VDP FIFO implementation
  22. *
  23. * fifo_slot: last slot executed in this scanline
  24. * fifo_cnt: #slots remaining for active FIFO write (#writes<<#bytep)
  25. * fifo_total: #total FIFO entries pending
  26. * fifo_data: last values transferred through fifo
  27. * fifo_queue: fifo transfer queue (#writes, flags)
  28. *
  29. * FIFO states: empty total=0
  30. * inuse total>0 && total<4
  31. * full total==4
  32. * wait total>4
  33. * Conditions:
  34. * fifo_slot is always behind slot2cyc[cycles]. Advancing it beyond cycles
  35. * implies blocking the 68k up to that slot.
  36. *
  37. * A FIFO write goes to the end of the FIFO queue, but DMA running in background
  38. * is always the last queue entry (transfers by CPU intervene and come 1st).
  39. * There can be more pending writes than FIFO slots, but the CPU will be blocked
  40. * until FIFO level (without background DMA) <= 4.
  41. * This is only about correct timing, data xfer must be handled by the caller.
  42. * Blocking the CPU means burning cycles via SekCyclesBurn*(), which is to be
  43. * executed by the caller.
  44. *
  45. * FIFOSync "executes" FIFO write slots up to the given cycle in the current
  46. * scanline. A queue entry completely executed is removed from the queue.
  47. * FIFOWrite pushes writes to the transfer queue. If it's a blocking write, 68k
  48. * is blocked if more than 4 FIFO writes are pending.
  49. * FIFORead executes a 68k read. 68k is blocked until the next transfer slot.
  50. */
  51. // NB code assumes fifo_* arrays have size 2^n
  52. static struct VdpFIFO { // XXX this must go into save file!
  53. // last transferred FIFO data, ...x = index XXX currently only CPU
  54. unsigned short fifo_data[4], fifo_dx;
  55. // queued FIFO transfers, ...x = index, ...l = queue length
  56. // each entry has 2 values: [n]>>3 = #writes, [n]&7 = flags (FQ_*)
  57. unsigned int fifo_queue[8], fifo_qx, fifo_ql;
  58. int fifo_total; // total# of pending FIFO entries (w/o BGDMA)
  59. unsigned short fifo_slot; // last executed slot in current scanline
  60. unsigned short fifo_maxslot;// #slots in scanline
  61. const unsigned char *fifo_cyc2sl;
  62. const unsigned short *fifo_sl2cyc;
  63. } VdpFIFO;
  64. enum { FQ_BYTE = 1, FQ_BGDMA = 2, FQ_FGDMA = 4 }; // queue flags, NB: BYTE = 1!
  65. // do the FIFO math
  66. static __inline int AdvanceFIFOEntry(struct VdpFIFO *vf, struct PicoVideo *pv, int slots)
  67. {
  68. int l = slots, b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;
  69. int cnt = pv->fifo_cnt;
  70. // advance currently active FIFO entry
  71. if (l > cnt)
  72. l = cnt;
  73. if (!(vf->fifo_queue[vf->fifo_qx] & FQ_BGDMA))
  74. if ((vf->fifo_total -= ((cnt & b) + l) >> b) < 0) vf->fifo_total = 0;
  75. cnt -= l;
  76. // if entry has been processed...
  77. if (cnt == 0) {
  78. // remove entry from FIFO
  79. if (vf->fifo_ql) {
  80. vf->fifo_queue[vf->fifo_qx] = 0;
  81. vf->fifo_qx = (vf->fifo_qx+1) & 7, vf->fifo_ql --;
  82. }
  83. // start processing for next entry if there is one
  84. if (vf->fifo_ql) {
  85. b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;
  86. cnt = (vf->fifo_queue[vf->fifo_qx] >> 3) << b;
  87. } else { // FIFO empty
  88. pv->status &= ~PVS_FIFORUN;
  89. vf->fifo_total = 0;
  90. }
  91. }
  92. pv->fifo_cnt = cnt;
  93. return l;
  94. }
  95. static __inline void SetFIFOState(struct VdpFIFO *vf, struct PicoVideo *pv)
  96. {
  97. unsigned int st = pv->status, cmd = pv->command;
  98. // release CPU and terminate DMA if FIFO isn't blocking the 68k anymore
  99. if (vf->fifo_total <= 4) {
  100. st &= ~PVS_CPUWR;
  101. if (!(st & (PVS_DMABG|PVS_DMAFILL))) {
  102. st &= ~SR_DMA;
  103. cmd &= ~0x80;
  104. }
  105. }
  106. if (pv->fifo_cnt == 0) {
  107. st &= ~PVS_CPURD;
  108. // terminate DMA if applicable
  109. if (!(st & (PVS_FIFORUN|PVS_DMAFILL))) {
  110. st &= ~(SR_DMA|PVS_DMABG);
  111. cmd &= ~0x80;
  112. }
  113. }
  114. pv->status = st;
  115. pv->command = cmd;
  116. }
  117. // sync FIFO to cycles
  118. void PicoVideoFIFOSync(int cycles)
  119. {
  120. struct VdpFIFO *vf = &VdpFIFO;
  121. struct PicoVideo *pv = &Pico.video;
  122. int slots, done;
  123. // calculate #slots since last executed slot
  124. slots = vf->fifo_cyc2sl[cycles>>1] - vf->fifo_slot;
  125. // advance FIFO queue by #done slots
  126. done = slots;
  127. while (done > 0 && pv->fifo_cnt) {
  128. int l = AdvanceFIFOEntry(vf, pv, done);
  129. vf->fifo_slot += l;
  130. done -= l;
  131. }
  132. if (done != slots)
  133. SetFIFOState(vf, pv);
  134. }
  135. // drain FIFO, blocking 68k on the way. FIFO must be synced prior to drain.
  136. static int PicoVideoFIFODrain(int level, int cycles, int bgdma)
  137. {
  138. struct VdpFIFO *vf = &VdpFIFO;
  139. struct PicoVideo *pv = &Pico.video;
  140. unsigned ocyc = cycles;
  141. int burn = 0;
  142. //int osl = fifo_slot;
  143. // process FIFO entries until low level is reached
  144. while (vf->fifo_slot <= vf->fifo_maxslot && cycles < 488 &&
  145. ((vf->fifo_total > level) | (vf->fifo_queue[vf->fifo_qx] & bgdma))) {
  146. int b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;
  147. int cnt = bgdma ? pv->fifo_cnt : ((vf->fifo_total-level)<<b) - (pv->fifo_cnt&b);
  148. int slot = (pv->fifo_cnt<cnt ? pv->fifo_cnt:cnt) + vf->fifo_slot;
  149. if (slot > vf->fifo_maxslot) {
  150. // target slot in later scanline, advance to eol
  151. slot = vf->fifo_maxslot;
  152. cycles = 488;
  153. } else {
  154. // advance FIFO to target slot and CPU to cycles at that slot
  155. cycles = vf->fifo_sl2cyc[slot]<<1;
  156. }
  157. if (slot > vf->fifo_slot) {
  158. AdvanceFIFOEntry(vf, pv, slot - vf->fifo_slot);
  159. vf->fifo_slot = slot;
  160. }
  161. }
  162. if (cycles > ocyc)
  163. burn = cycles - ocyc;
  164. SetFIFOState(vf, pv);
  165. return burn;
  166. }
  167. // read VDP data port
  168. static int PicoVideoFIFORead(void)
  169. {
  170. struct VdpFIFO *vf = &VdpFIFO;
  171. struct PicoVideo *pv = &Pico.video;
  172. int lc = SekCyclesDone()-Pico.t.m68c_line_start;
  173. int burn = 0;
  174. if (pv->fifo_cnt) {
  175. PicoVideoFIFOSync(lc);
  176. // advance FIFO and CPU until FIFO is empty
  177. burn = PicoVideoFIFODrain(0, lc, FQ_BGDMA);
  178. lc += burn;
  179. }
  180. if (pv->fifo_cnt)
  181. pv->status |= PVS_CPURD; // target slot is in later scanline
  182. else {
  183. // use next VDP access slot for reading, block 68k until then
  184. vf->fifo_slot = vf->fifo_cyc2sl[lc>>1] + 1;
  185. burn += (vf->fifo_sl2cyc[vf->fifo_slot]<<1) - lc;
  186. }
  187. return burn;
  188. }
  189. // write VDP data port
  190. int PicoVideoFIFOWrite(int count, int flags, unsigned sr_mask,unsigned sr_flags)
  191. {
  192. struct VdpFIFO *vf = &VdpFIFO;
  193. struct PicoVideo *pv = &Pico.video;
  194. int lc = SekCyclesDone()-Pico.t.m68c_line_start;
  195. int burn = 0;
  196. if (pv->fifo_cnt)
  197. PicoVideoFIFOSync(lc);
  198. pv->status = (pv->status & ~sr_mask) | sr_flags;
  199. if (count && vf->fifo_ql < 8) {
  200. // determine queue position for entry
  201. int x = (vf->fifo_qx + vf->fifo_ql - 1) & 7;
  202. if (unlikely(vf->fifo_queue[x] & FQ_BGDMA)) {
  203. // CPU FIFO writes have priority over a background DMA Fill/Copy
  204. // XXX if interrupting a DMA fill, fill data changes
  205. if (x == vf->fifo_qx) { // overtaking to queue head?
  206. int f = vf->fifo_queue[x] & 7;
  207. vf->fifo_queue[(x+1) & 7] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;
  208. pv->status &= ~PVS_FIFORUN;
  209. } else
  210. // push background DMA back
  211. vf->fifo_queue[(x+1) & 7] = vf->fifo_queue[x];
  212. x = (x-1) & 7;
  213. }
  214. if ((pv->status & PVS_FIFORUN) && (vf->fifo_queue[x] & 7) == flags) {
  215. // amalgamate entries if of same type
  216. vf->fifo_queue[x] += (count << 3);
  217. if (x == vf->fifo_qx)
  218. pv->fifo_cnt += count << (flags & FQ_BYTE);
  219. } else {
  220. // create new xfer queue entry
  221. vf->fifo_ql ++;
  222. x = (x+1) & 7;
  223. vf->fifo_queue[x] = (count << 3) | flags;
  224. }
  225. // update FIFO state if it was empty
  226. if (!(pv->status & PVS_FIFORUN)) {
  227. vf->fifo_slot = vf->fifo_cyc2sl[(lc+8)>>1]; // FIFO latency ~3 vdp slots
  228. pv->status |= PVS_FIFORUN;
  229. pv->fifo_cnt = count << (flags & FQ_BYTE);
  230. }
  231. if (!(flags & FQ_BGDMA))
  232. vf->fifo_total += count;
  233. }
  234. // if CPU is waiting for the bus, advance CPU and FIFO until bus is free
  235. if (pv->status & PVS_CPUWR)
  236. burn = PicoVideoFIFODrain(4, lc, 0);
  237. return burn;
  238. }
  239. // at HINT, advance FIFO to new scanline
  240. int PicoVideoFIFOHint(void)
  241. {
  242. struct VdpFIFO *vf = &VdpFIFO;
  243. struct PicoVideo *pv = &Pico.video;
  244. int burn = 0;
  245. // reset slot to start of scanline
  246. vf->fifo_slot = 0;
  247. // if CPU is waiting for the bus, advance CPU and FIFO until bus is free
  248. if (pv->status & PVS_CPUWR)
  249. burn = PicoVideoFIFOWrite(0, 0, 0, 0);
  250. else if (pv->status & PVS_CPURD)
  251. burn = PicoVideoFIFORead();
  252. return burn;
  253. }
  254. // switch FIFO mode between active/inactive display
  255. void PicoVideoFIFOMode(int active, int h40)
  256. {
  257. static const unsigned char *vdpcyc2sl[2][2] =
  258. { {vdpcyc2sl_32_bl, vdpcyc2sl_40_bl} , {vdpcyc2sl_32, vdpcyc2sl_40} };
  259. static const unsigned short *vdpsl2cyc[2][2] =
  260. { {vdpsl2cyc_32_bl, vdpsl2cyc_40_bl} , {vdpsl2cyc_32, vdpsl2cyc_40} };
  261. struct VdpFIFO *vf = &VdpFIFO;
  262. struct PicoVideo *pv = &Pico.video;
  263. int lc = SekCyclesDone() - Pico.t.m68c_line_start;
  264. active = active && !(pv->status & PVS_VB2);
  265. if (vf->fifo_maxslot)
  266. PicoVideoFIFOSync(lc);
  267. vf->fifo_cyc2sl = vdpcyc2sl[active][h40];
  268. vf->fifo_sl2cyc = vdpsl2cyc[active][h40];
  269. // recalculate FIFO slot for new mode
  270. vf->fifo_slot = vf->fifo_cyc2sl[lc>>1]-1;
  271. vf->fifo_maxslot = vf->fifo_cyc2sl[488>>1];
  272. }
  273. // VDP memory rd/wr
  274. static __inline void AutoIncrement(void)
  275. {
  276. Pico.video.addr=(unsigned short)(Pico.video.addr+Pico.video.reg[0xf]);
  277. if (Pico.video.addr < Pico.video.reg[0xf]) Pico.video.addr_u ^= 1;
  278. }
  279. static NOINLINE void VideoWriteVRAM128(u32 a, u16 d)
  280. {
  281. // nasty
  282. u32 b = ((a & 2) >> 1) | ((a & 0x400) >> 9) | (a & 0x3FC) | ((a & 0x1F800) >> 1);
  283. ((u8 *)PicoMem.vram)[b] = d;
  284. if (!((u16)(b^SATaddr) & SATmask))
  285. Pico.est.rendstatus |= PDRAW_DIRTY_SPRITES;
  286. if (((a^SATaddr) & SATmask) == 0)
  287. UpdateSAT(a, d);
  288. }
  289. static void VideoWrite(u16 d)
  290. {
  291. unsigned int a = Pico.video.addr;
  292. switch (Pico.video.type)
  293. {
  294. case 1: if (a & 1)
  295. d = (u16)((d << 8) | (d >> 8));
  296. a |= Pico.video.addr_u << 16;
  297. VideoWriteVRAM(a, d);
  298. break;
  299. case 3: if (PicoMem.cram [(a >> 1) & 0x3f] != d) Pico.m.dirtyPal = 1;
  300. PicoMem.cram [(a >> 1) & 0x3f] = d & 0xeee; break;
  301. case 5: PicoMem.vsram[(a >> 1) & 0x3f] = d & 0x7ff; break;
  302. case 0x81:
  303. a |= Pico.video.addr_u << 16;
  304. VideoWriteVRAM128(a, d);
  305. break;
  306. //default:elprintf(EL_ANOMALY, "VDP write %04x with bad type %i", d, Pico.video.type); break;
  307. }
  308. AutoIncrement();
  309. }
  310. static unsigned int VideoRead(void)
  311. {
  312. unsigned int a, d = VdpFIFO.fifo_data[(VdpFIFO.fifo_dx+1)&3];
  313. a=Pico.video.addr; a>>=1;
  314. SekCyclesBurnRun(PicoVideoFIFORead());
  315. switch (Pico.video.type)
  316. {
  317. case 0: d=PicoMem.vram [a & 0x7fff]; break;
  318. case 8: d=PicoMem.cram [a & 0x003f] | (d & ~0x0eee); break;
  319. case 4: if ((a & 0x3f) >= 0x28) a = 0;
  320. d=PicoMem.vsram [a & 0x003f] | (d & ~0x07ff); break;
  321. case 12:a=PicoMem.vram [a & 0x7fff]; if (Pico.video.addr&1) a >>= 8;
  322. d=(a & 0x00ff) | (d & ~0x00ff); break;
  323. default:elprintf(EL_ANOMALY, "VDP read with bad type %i", Pico.video.type); break;
  324. }
  325. AutoIncrement();
  326. return d;
  327. }
  328. // VDP DMA
  329. static int GetDmaLength(void)
  330. {
  331. struct PicoVideo *pvid=&Pico.video;
  332. int len=0;
  333. // 16-bit words to transfer:
  334. len =pvid->reg[0x13];
  335. len|=pvid->reg[0x14]<<8;
  336. len = ((len - 1) & 0xffff) + 1;
  337. return len;
  338. }
  339. static void DmaSlow(int len, unsigned int source)
  340. {
  341. u32 inc = Pico.video.reg[0xf];
  342. u32 a = Pico.video.addr | (Pico.video.addr_u << 16);
  343. u16 *r, *base = NULL;
  344. u32 mask = 0x1ffff;
  345. elprintf(EL_VDPDMA, "DmaSlow[%i] %06x->%04x len %i inc=%i blank %i [%u] @ %06x",
  346. Pico.video.type, source, a, len, inc, (Pico.video.status&SR_VB)||!(Pico.video.reg[1]&0x40),
  347. SekCyclesDone(), SekPc);
  348. SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_FGDMA | (Pico.video.type == 1),
  349. PVS_DMABG, SR_DMA | PVS_CPUWR));
  350. if ((source & 0xe00000) == 0xe00000) { // Ram
  351. base = (u16 *)PicoMem.ram;
  352. mask = 0xffff;
  353. }
  354. else if (PicoIn.AHW & PAHW_MCD)
  355. {
  356. u8 r3 = Pico_mcd->s68k_regs[3];
  357. elprintf(EL_VDPDMA, "DmaSlow CD, r3=%02x", r3);
  358. if (source < 0x20000) { // Bios area
  359. base = (u16 *)Pico_mcd->bios;
  360. } else if ((source & 0xfc0000) == 0x200000) { // Word Ram
  361. if (!(r3 & 4)) { // 2M mode
  362. base = (u16 *)(Pico_mcd->word_ram2M + (source & 0x20000));
  363. } else {
  364. if (source < 0x220000) { // 1M mode
  365. int bank = r3 & 1;
  366. base = (u16 *)(Pico_mcd->word_ram1M[bank]);
  367. } else {
  368. DmaSlowCell(source - 2, a, len, inc);
  369. return;
  370. }
  371. }
  372. source -= 2;
  373. } else if ((source & 0xfe0000) == 0x020000) { // Prg Ram
  374. base = (u16 *)Pico_mcd->prg_ram_b[r3 >> 6];
  375. source -= 2; // XXX: test
  376. }
  377. }
  378. else
  379. {
  380. // if we have DmaHook, let it handle ROM because of possible DMA delay
  381. u32 source2;
  382. if (PicoDmaHook && (source2 = PicoDmaHook(source, len, &base, &mask)))
  383. source = source2;
  384. else // Rom
  385. base = m68k_dma_source(source);
  386. }
  387. if (!base) {
  388. elprintf(EL_VDPDMA|EL_ANOMALY, "DmaSlow[%i] %06x->%04x: invalid src", Pico.video.type, source, a);
  389. return;
  390. }
  391. // operate in words
  392. source >>= 1;
  393. mask >>= 1;
  394. switch (Pico.video.type)
  395. {
  396. case 1: // vram
  397. r = PicoMem.vram;
  398. if (inc == 2 && !(a & 1) && (a & ~0xffff) == ((a + len*2-1) & ~0xffff) &&
  399. ((a >= SATaddr+0x280) | ((a + len*2-1) < SATaddr)) &&
  400. (source & ~mask) == ((source + len-1) & ~mask))
  401. {
  402. // most used DMA mode
  403. memcpy((char *)r + a, base + (source & mask), len * 2);
  404. a += len * 2;
  405. break;
  406. }
  407. for(; len; len--)
  408. {
  409. u16 d = base[source++ & mask];
  410. if(a & 1) d=(d<<8)|(d>>8);
  411. VideoWriteVRAM(a, d);
  412. // AutoIncrement
  413. a = (a+inc) & ~0x20000;
  414. }
  415. break;
  416. case 3: // cram
  417. Pico.m.dirtyPal = 1;
  418. r = PicoMem.cram;
  419. for (; len; len--)
  420. {
  421. r[(a / 2) & 0x3f] = base[source++ & mask] & 0xeee;
  422. // AutoIncrement
  423. a = (a+inc) & ~0x20000;
  424. }
  425. break;
  426. case 5: // vsram
  427. r = PicoMem.vsram;
  428. for (; len; len--)
  429. {
  430. r[(a / 2) & 0x3f] = base[source++ & mask] & 0x7ff;
  431. // AutoIncrement
  432. a = (a+inc) & ~0x20000;
  433. }
  434. break;
  435. case 0x81: // vram 128k
  436. for(; len; len--)
  437. {
  438. u16 d = base[source++ & mask];
  439. VideoWriteVRAM128(a, d);
  440. // AutoIncrement
  441. a = (a+inc) & ~0x20000;
  442. }
  443. break;
  444. default:
  445. if (Pico.video.type != 0 || (EL_LOGMASK & EL_VDPDMA))
  446. elprintf(EL_VDPDMA|EL_ANOMALY, "DMA with bad type %i", Pico.video.type);
  447. break;
  448. }
  449. // remember addr
  450. Pico.video.addr = a;
  451. Pico.video.addr_u = a >> 16;
  452. }
  453. static void DmaCopy(int len)
  454. {
  455. u32 a = Pico.video.addr | (Pico.video.addr_u << 16);
  456. u8 *vr = (u8 *)PicoMem.vram;
  457. u8 inc = Pico.video.reg[0xf];
  458. int source;
  459. elprintf(EL_VDPDMA, "DmaCopy len %i [%u]", len, SekCyclesDone());
  460. // XXX implement VRAM 128k? Is this even working? xfer/count still FQ_BYTE?
  461. SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | FQ_BYTE,
  462. PVS_CPUWR, SR_DMA | PVS_DMABG));
  463. source =Pico.video.reg[0x15];
  464. source|=Pico.video.reg[0x16]<<8;
  465. for (; len; len--)
  466. {
  467. vr[(u16)a] = vr[(u16)(source++)];
  468. if (((a^SATaddr) & SATmask) == 0)
  469. UpdateSAT(a, ((u16 *)vr)[(u16)a >> 1]);
  470. // AutoIncrement
  471. a = (a+inc) & ~0x20000;
  472. }
  473. // remember addr
  474. Pico.video.addr = a;
  475. Pico.video.addr_u = a >> 16;
  476. }
  477. static NOINLINE void DmaFill(int data)
  478. {
  479. u32 a = Pico.video.addr | (Pico.video.addr_u << 16);
  480. u8 *vr = (u8 *)PicoMem.vram;
  481. u8 high = (u8)(data >> 8);
  482. u8 inc = Pico.video.reg[0xf];
  483. int source;
  484. int len, l;
  485. len = GetDmaLength();
  486. elprintf(EL_VDPDMA, "DmaFill len %i inc %i [%u]", len, inc, SekCyclesDone());
  487. SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | (Pico.video.type == 1),
  488. PVS_CPUWR | PVS_DMAFILL, SR_DMA | PVS_DMABG));
  489. switch (Pico.video.type)
  490. {
  491. case 1: // vram
  492. if (inc == 1 && (a & ~0xffff) == ((a + len-1) & ~0xffff) &&
  493. ((a >= SATaddr+0x280) | ((a + len-1) < SATaddr)))
  494. {
  495. // most used DMA mode
  496. memset(vr + (u16)a, high, len);
  497. a += len;
  498. break;
  499. }
  500. for (l = len; l; l--) {
  501. // Write upper byte to adjacent address
  502. // (here we are byteswapped, so address is already 'adjacent')
  503. vr[(u16)a] = high;
  504. if (((a^SATaddr) & SATmask) == 0)
  505. UpdateSAT(a, ((u16 *)vr)[(u16)a >> 1]);
  506. // Increment address register
  507. a = (a+inc) & ~0x20000;
  508. }
  509. break;
  510. case 3: // cram
  511. Pico.m.dirtyPal = 1;
  512. data &= 0xeee;
  513. for (l = len; l; l--) {
  514. PicoMem.cram[(a/2) & 0x3f] = data;
  515. // Increment address register
  516. a = (a+inc) & ~0x20000;
  517. }
  518. break;
  519. case 5: { // vsram
  520. data &= 0x7ff;
  521. for (l = len; l; l--) {
  522. PicoMem.vsram[(a/2) & 0x3f] = data;
  523. // Increment address register
  524. a = (a+inc) & ~0x20000;
  525. }
  526. break;
  527. }
  528. case 0x81: // vram 128k
  529. for (l = len; l; l--) {
  530. VideoWriteVRAM128(a, data);
  531. // Increment address register
  532. a = (a+inc) & ~0x20000;
  533. }
  534. break;
  535. default:
  536. a += len * inc;
  537. break;
  538. }
  539. // remember addr
  540. Pico.video.addr = a;
  541. Pico.video.addr_u = a >> 16;
  542. // register update
  543. Pico.video.reg[0x13] = Pico.video.reg[0x14] = 0;
  544. source = Pico.video.reg[0x15];
  545. source |= Pico.video.reg[0x16] << 8;
  546. source += len;
  547. Pico.video.reg[0x15] = source;
  548. Pico.video.reg[0x16] = source >> 8;
  549. }
  550. // VDP command handling
  551. static NOINLINE void CommandDma(void)
  552. {
  553. struct PicoVideo *pvid=&Pico.video;
  554. u32 len, method;
  555. u32 source;
  556. PicoVideoFIFOSync(SekCyclesDone()-Pico.t.m68c_line_start);
  557. if (pvid->status & SR_DMA) {
  558. elprintf(EL_VDPDMA, "Dma overlap, left=%d @ %06x",
  559. VdpFIFO.fifo_total, SekPc);
  560. pvid->fifo_cnt = VdpFIFO.fifo_total = VdpFIFO.fifo_ql = 0;
  561. pvid->status &= ~(PVS_FIFORUN|PVS_DMAFILL);
  562. }
  563. len = GetDmaLength();
  564. source =Pico.video.reg[0x15];
  565. source|=Pico.video.reg[0x16] << 8;
  566. source|=Pico.video.reg[0x17] << 16;
  567. method=pvid->reg[0x17]>>6;
  568. if (method < 2)
  569. DmaSlow(len, source << 1); // 68000 to VDP
  570. else if (method == 3)
  571. DmaCopy(len); // VRAM Copy
  572. else {
  573. pvid->status |= SR_DMA|PVS_DMAFILL;
  574. return;
  575. }
  576. source += len;
  577. Pico.video.reg[0x13] = Pico.video.reg[0x14] = 0;
  578. Pico.video.reg[0x15] = source;
  579. Pico.video.reg[0x16] = source >> 8;
  580. }
  581. static NOINLINE void CommandChange(struct PicoVideo *pvid)
  582. {
  583. unsigned int cmd, addr;
  584. cmd = pvid->command;
  585. // Get type of transfer 0xc0000030 (v/c/vsram read/write)
  586. pvid->type = (u8)(((cmd >> 2) & 0xc) | (cmd >> 30));
  587. if (pvid->type == 1) // vram
  588. pvid->type |= pvid->reg[1] & 0x80; // 128k
  589. // Get address 0x3fff0003
  590. addr = (cmd >> 16) & 0x3fff;
  591. addr |= (cmd << 14) & 0xc000;
  592. pvid->addr = (u16)addr;
  593. pvid->addr_u = (u8)((cmd >> 2) & 1);
  594. }
  595. // VDP interface
  596. static void DrawSync(int skip)
  597. {
  598. int lines = Pico.video.reg[1]&0x08 ? 240 : 224;
  599. int last = Pico.m.scanline - (skip || blankline == Pico.m.scanline);
  600. if (last < lines && !(PicoIn.opt & POPT_ALT_RENDERER) &&
  601. !PicoIn.skipFrame && Pico.est.DrawScanline <= last) {
  602. //elprintf(EL_ANOMALY, "sync");
  603. if (blankline >= 0 && blankline < last) {
  604. PicoDrawSync(blankline, 1);
  605. blankline = -1;
  606. }
  607. PicoDrawSync(last, 0);
  608. }
  609. }
  610. PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d)
  611. {
  612. struct PicoVideo *pvid=&Pico.video;
  613. //elprintf(EL_STATUS, "PicoVideoWrite [%06x] %04x [%u] @ %06x",
  614. // a, d, SekCyclesDone(), SekPc);
  615. a &= 0x1c;
  616. switch (a)
  617. {
  618. case 0x00: // Data port 0 or 2
  619. // try avoiding the sync..
  620. if (Pico.m.scanline < (pvid->reg[1]&0x08 ? 240 : 224) && (pvid->reg[1]&0x40) &&
  621. !(!pvid->pending &&
  622. ((pvid->command & 0xc00000f0) == 0x40000010 && PicoMem.vsram[pvid->addr>>1] == (d & 0x7ff)))
  623. )
  624. DrawSync(0); // XXX it's unclear when vscroll data is fetched from vsram?
  625. if (pvid->pending) {
  626. CommandChange(pvid);
  627. pvid->pending=0;
  628. }
  629. if (!(PicoIn.opt&POPT_DIS_VDP_FIFO))
  630. {
  631. VdpFIFO.fifo_data[++VdpFIFO.fifo_dx&3] = d;
  632. SekCyclesBurnRun(PicoVideoFIFOWrite(1, pvid->type == 1, 0, PVS_CPUWR));
  633. elprintf(EL_ASVDP, "VDP data write: [%04x] %04x [%u] {%i} @ %06x",
  634. Pico.video.addr, d, SekCyclesDone(), Pico.video.type, SekPc);
  635. }
  636. VideoWrite(d);
  637. // start DMA fill on write. NB VSRAM and CRAM fills use wrong FIFO data.
  638. if (pvid->status & PVS_DMAFILL)
  639. DmaFill(VdpFIFO.fifo_data[(VdpFIFO.fifo_dx + !!(pvid->type&~0x81))&3]);
  640. break;
  641. case 0x04: // Control (command) port 4 or 6
  642. if (pvid->status & SR_DMA)
  643. SekCyclesBurnRun(PicoVideoFIFORead()); // kludge, flush out running DMA
  644. if (pvid->pending)
  645. {
  646. // Low word of command:
  647. if (!(pvid->reg[1]&0x10))
  648. d = (d&~0x80)|(pvid->command&0x80);
  649. pvid->command &= 0xffff0000;
  650. pvid->command |= d;
  651. pvid->pending = 0;
  652. CommandChange(pvid);
  653. // Check for dma:
  654. if (d & 0x80) {
  655. DrawSync(SekCyclesDone() - Pico.t.m68c_line_start <= 488-390);
  656. CommandDma();
  657. }
  658. }
  659. else
  660. {
  661. if ((d&0xc000)==0x8000)
  662. {
  663. // Register write:
  664. int num=(d>>8)&0x1f;
  665. int dold=pvid->reg[num];
  666. pvid->type=0; // register writes clear command (else no Sega logo in Golden Axe II)
  667. if (num > 0x0a && !(pvid->reg[1]&4)) {
  668. elprintf(EL_ANOMALY, "%02x written to reg %02x in SMS mode @ %06x", d, num, SekPc);
  669. return;
  670. }
  671. if (num == 0 && !(pvid->reg[0]&2) && (d&2))
  672. pvid->hv_latch = PicoVideoRead(0x08);
  673. if (num == 1 && ((pvid->reg[1]^d)&0x40)) {
  674. PicoVideoFIFOMode(d & 0x40, pvid->reg[12]&1);
  675. // handle line blanking before line rendering
  676. if (SekCyclesDone() - Pico.t.m68c_line_start <= 488-390)
  677. blankline = d&0x40 ? -1 : Pico.m.scanline;
  678. }
  679. if (num == 12 && ((pvid->reg[12]^d)&0x01))
  680. PicoVideoFIFOMode(pvid->reg[1]&0x40, d & 1);
  681. DrawSync(SekCyclesDone() - Pico.t.m68c_line_start <= 488-390);
  682. pvid->reg[num]=(unsigned char)d;
  683. switch (num)
  684. {
  685. case 0x00:
  686. elprintf(EL_INTSW, "hint_onoff: %i->%i [%u] pend=%i @ %06x", (dold&0x10)>>4,
  687. (d&0x10)>>4, SekCyclesDone(), (pvid->pending_ints&0x10)>>4, SekPc);
  688. goto update_irq;
  689. case 0x01:
  690. elprintf(EL_INTSW, "vint_onoff: %i->%i [%u] pend=%i @ %06x", (dold&0x20)>>5,
  691. (d&0x20)>>5, SekCyclesDone(), (pvid->pending_ints&0x20)>>5, SekPc);
  692. if (!(pvid->status & PVS_VB2))
  693. pvid->status &= ~SR_VB;
  694. pvid->status |= ((d >> 3) ^ SR_VB) & SR_VB; // forced blanking
  695. goto update_irq;
  696. case 0x05:
  697. case 0x06:
  698. if (d^dold) Pico.est.rendstatus |= PDRAW_SPRITES_MOVED;
  699. break;
  700. case 0x0c:
  701. // renderers should update their palettes if sh/hi mode is changed
  702. if ((d^dold)&8) Pico.m.dirtyPal = 1;
  703. break;
  704. default:
  705. return;
  706. }
  707. SATaddr = ((pvid->reg[5]&0x7f) << 9) | ((pvid->reg[6]&0x20) << 11);
  708. SATmask = ~0x1ff;
  709. if (Pico.video.reg[12]&1)
  710. SATaddr &= ~0x200, SATmask &= ~0x200; // H40, zero lowest SAT bit
  711. //elprintf(EL_STATUS, "spritep moved to %04x", SATaddr);
  712. return;
  713. update_irq:
  714. #ifndef EMU_CORE_DEBUG
  715. // update IRQ level
  716. if (!SekShouldInterrupt()) // hack
  717. {
  718. int lines, pints, irq = 0;
  719. lines = (pvid->reg[1] & 0x20) | (pvid->reg[0] & 0x10);
  720. pints = pvid->pending_ints & lines;
  721. if (pints & 0x20) irq = 6;
  722. else if (pints & 0x10) irq = 4;
  723. SekInterrupt(irq); // update line
  724. // this is broken because cost of current insn isn't known here
  725. if (irq) SekEndRun(21); // make it delayed
  726. }
  727. #endif
  728. }
  729. else
  730. {
  731. // High word of command:
  732. pvid->command&=0x0000ffff;
  733. pvid->command|=d<<16;
  734. pvid->pending=1;
  735. }
  736. }
  737. break;
  738. // case 0x08: // 08 0a - HV counter - lock up
  739. // case 0x0c: // 0c 0e - HV counter - lock up
  740. // case 0x10: // 10 12 - PSG - handled by caller
  741. // case 0x14: // 14 16 - PSG - handled by caller
  742. // case 0x18: // 18 1a - no effect?
  743. case 0x1c: // 1c 1e - debug
  744. pvid->debug = d;
  745. pvid->debug_p = 0;
  746. if (d & (1 << 6)) {
  747. pvid->debug_p |= PVD_KILL_A | PVD_KILL_B;
  748. pvid->debug_p |= PVD_KILL_S_LO | PVD_KILL_S_HI;
  749. }
  750. switch ((d >> 7) & 3) {
  751. case 1:
  752. pvid->debug_p &= ~(PVD_KILL_S_LO | PVD_KILL_S_HI);
  753. pvid->debug_p |= PVD_FORCE_S;
  754. break;
  755. case 2:
  756. pvid->debug_p &= ~PVD_KILL_A;
  757. pvid->debug_p |= PVD_FORCE_A;
  758. break;
  759. case 3:
  760. pvid->debug_p &= ~PVD_KILL_B;
  761. pvid->debug_p |= PVD_FORCE_B;
  762. break;
  763. }
  764. break;
  765. }
  766. }
  767. static u32 VideoSr(const struct PicoVideo *pv)
  768. {
  769. unsigned int c, d = pv->status;
  770. unsigned int hp = pv->reg[12]&1 ? 15*488/210+1 : 15*488/171+1; // HBLANK start
  771. unsigned int hl = pv->reg[12]&1 ? 37*488/210+1 : 28*488/171+1; // HBLANK len
  772. c = SekCyclesDone() - Pico.t.m68c_line_start;
  773. if (c - hp < hl)
  774. d |= SR_HB;
  775. PicoVideoFIFOSync(c);
  776. if (VdpFIFO.fifo_total >= 4)
  777. d |= SR_FULL;
  778. else if (!VdpFIFO.fifo_total)
  779. d |= SR_EMPT;
  780. return d;
  781. }
  782. PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a)
  783. {
  784. a &= 0x1c;
  785. if (a == 0x04) // control port
  786. {
  787. struct PicoVideo *pv = &Pico.video;
  788. unsigned int d = VideoSr(pv);
  789. if (pv->pending) {
  790. CommandChange(pv);
  791. pv->pending = 0;
  792. }
  793. elprintf(EL_SR, "SR read: %04x [%u] @ %06x", d, SekCyclesDone(), SekPc);
  794. return d;
  795. }
  796. // H-counter info (based on Generator):
  797. // frame:
  798. // | <- hblank? -> |
  799. // start <416> hint <36> hdisplay <38> end // CPU cycles
  800. // |---------...---------|------------|-------------|
  801. // 0 B6 E4 FF // 40 cells
  802. // 0 93 E8 FF // 32 cells
  803. // Gens (?) v-render
  804. // start <hblank=84> hint hdisplay <404> |
  805. // |---------------------|--------------------------|
  806. // E4 (hc[0x43]==0) 07 B1 // 40
  807. // E8 (hc[0x45]==0) 05 91 // 32
  808. // check: Sonic 3D Blast bonus, Cannon Fodder, Chase HQ II, 3 Ninjas kick back, Road Rash 3, Skitchin', Wheel of Fortune
  809. if ((a&0x1c)==0x08)
  810. {
  811. unsigned int d;
  812. d = (SekCyclesDone() - Pico.t.m68c_line_start) & 0x1ff; // FIXME
  813. if (Pico.video.reg[0]&2)
  814. d = Pico.video.hv_latch;
  815. else if (Pico.video.reg[12]&1)
  816. d = hcounts_40[d/2] | (Pico.video.v_counter << 8);
  817. else d = hcounts_32[d/2] | (Pico.video.v_counter << 8);
  818. elprintf(EL_HVCNT, "hv: %02x %02x [%u] @ %06x", d, Pico.video.v_counter, SekCyclesDone(), SekPc);
  819. return d;
  820. }
  821. if (a==0x00) // data port
  822. {
  823. return VideoRead();
  824. }
  825. return 0;
  826. }
  827. unsigned char PicoVideoRead8DataH(void)
  828. {
  829. return VideoRead() >> 8;
  830. }
  831. unsigned char PicoVideoRead8DataL(void)
  832. {
  833. return VideoRead();
  834. }
  835. unsigned char PicoVideoRead8CtlH(void)
  836. {
  837. struct PicoVideo *pv = &Pico.video;
  838. u8 d = VideoSr(pv) >> 8;
  839. if (pv->pending) {
  840. CommandChange(pv);
  841. pv->pending = 0;
  842. }
  843. elprintf(EL_SR, "SR read (h): %02x @ %06x", d, SekPc);
  844. return d;
  845. }
  846. unsigned char PicoVideoRead8CtlL(void)
  847. {
  848. struct PicoVideo *pv = &Pico.video;
  849. u8 d = VideoSr(pv);
  850. if (pv->pending) {
  851. CommandChange(pv);
  852. pv->pending = 0;
  853. }
  854. elprintf(EL_SR, "SR read (l): %02x @ %06x", d, SekPc);
  855. return d;
  856. }
  857. unsigned char PicoVideoRead8HV_H(void)
  858. {
  859. elprintf(EL_HVCNT, "vcounter: %02x [%u] @ %06x", Pico.video.v_counter, SekCyclesDone(), SekPc);
  860. return Pico.video.v_counter;
  861. }
  862. // FIXME: broken
  863. unsigned char PicoVideoRead8HV_L(void)
  864. {
  865. u32 d = (SekCyclesDone() - Pico.t.m68c_line_start) & 0x1ff; // FIXME
  866. if (Pico.video.reg[0]&2)
  867. d = Pico.video.hv_latch;
  868. else if (Pico.video.reg[12]&1)
  869. d = hcounts_40[d/2];
  870. else d = hcounts_32[d/2];
  871. elprintf(EL_HVCNT, "hcounter: %02x [%u] @ %06x", d, SekCyclesDone(), SekPc);
  872. return d;
  873. }
  874. void PicoVideoCacheSAT(void)
  875. {
  876. struct PicoVideo *pv = &Pico.video;
  877. int l;
  878. SATaddr = ((pv->reg[5]&0x7f) << 9) | ((pv->reg[6]&0x20) << 11);
  879. SATmask = ~0x1ff;
  880. if (pv->reg[12]&1)
  881. SATaddr &= ~0x200, SATmask &= ~0x200; // H40, zero lowest SAT bit
  882. // rebuild SAT cache XXX wrong since cache and memory can differ
  883. for (l = 0; l < 80; l++) {
  884. ((u16 *)VdpSATCache)[l*2 ] = PicoMem.vram[(SATaddr>>1) + l*4 ];
  885. ((u16 *)VdpSATCache)[l*2 + 1] = PicoMem.vram[(SATaddr>>1) + l*4 + 1];
  886. }
  887. Pico.est.rendstatus |= PDRAW_SPRITES_MOVED;
  888. }
  889. void PicoVideoSave(void)
  890. {
  891. struct VdpFIFO *vf = &VdpFIFO;
  892. struct PicoVideo *pv = &Pico.video;
  893. int l, x;
  894. // account for all outstanding xfers XXX kludge, entry attr's not saved
  895. for (l = vf->fifo_ql, x = vf->fifo_qx + l-1; l > 1; l--, x--)
  896. pv->fifo_cnt += (vf->fifo_queue[x&7] >> 3) << (vf->fifo_queue[x&7] & FQ_BYTE);
  897. }
  898. void PicoVideoLoad(void)
  899. {
  900. struct VdpFIFO *vf = &VdpFIFO;
  901. struct PicoVideo *pv = &Pico.video;
  902. // convert former dma_xfers (why was this in PicoMisc anyway?)
  903. if (Pico.m.dma_xfers) {
  904. pv->status = SR_DMA|PVS_FIFORUN;
  905. pv->fifo_cnt = Pico.m.dma_xfers * (pv->type == 1 ? 2 : 1);
  906. vf->fifo_total = Pico.m.dma_xfers;
  907. Pico.m.dma_xfers = 0;
  908. }
  909. PicoVideoCacheSAT();
  910. }
  911. // vim:shiftwidth=2:ts=2:expandtab