ym2612.c 62 KB

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  1. /*
  2. ** This is a bunch of remains of original fm.c from MAME project. All stuff
  3. ** unrelated to ym2612 was removed, multiple chip support was removed,
  4. ** some parts of code were slightly rewritten and tied to the emulator.
  5. **
  6. ** SSG-EG was also removed, because it's rarely used, Sega2.doc even does not
  7. ** document it ("proprietary") and tells to write 0 to SSG-EG control register.
  8. **
  9. ** updated with fixes from mame 0.216 (file version 1.5.1) (kub)
  10. ** SSG-EG readded from GenPlus (kub)
  11. ** linear sample interpolation for chip to output rate adaption (kub)
  12. */
  13. /*
  14. **
  15. ** File: fm.c -- software implementation of Yamaha FM sound generator
  16. **
  17. ** Copyright (C) 2001, 2002, 2003 Jarek Burczynski (bujar at mame dot net)
  18. ** Copyright (C) 1998 Tatsuyuki Satoh , MultiArcadeMachineEmulator development
  19. **
  20. ** Version 1.4 (final beta)
  21. **
  22. */
  23. /*
  24. ** History:
  25. **
  26. ** 03-08-2003 Jarek Burczynski:
  27. ** - fixed YM2608 initial values (after the reset)
  28. ** - fixed flag and irqmask handling (YM2608)
  29. ** - fixed BUFRDY flag handling (YM2608)
  30. **
  31. ** 14-06-2003 Jarek Burczynski:
  32. ** - implemented all of the YM2608 status register flags
  33. ** - implemented support for external memory read/write via YM2608
  34. ** - implemented support for deltat memory limit register in YM2608 emulation
  35. **
  36. ** 22-05-2003 Jarek Burczynski:
  37. ** - fixed LFO PM calculations (copy&paste bugfix)
  38. **
  39. ** 08-05-2003 Jarek Burczynski:
  40. ** - fixed SSG support
  41. **
  42. ** 22-04-2003 Jarek Burczynski:
  43. ** - implemented 100% correct LFO generator (verified on real YM2610 and YM2608)
  44. **
  45. ** 15-04-2003 Jarek Burczynski:
  46. ** - added support for YM2608's register 0x110 - status mask
  47. **
  48. ** 01-12-2002 Jarek Burczynski:
  49. ** - fixed register addressing in YM2608, YM2610, YM2610B chips. (verified on real YM2608)
  50. ** The addressing patch used for early Neo-Geo games can be removed now.
  51. **
  52. ** 26-11-2002 Jarek Burczynski, Nicola Salmoria:
  53. ** - recreated YM2608 ADPCM ROM using data from real YM2608's output which leads to:
  54. ** - added emulation of YM2608 drums.
  55. ** - output of YM2608 is two times lower now - same as YM2610 (verified on real YM2608)
  56. **
  57. ** 16-08-2002 Jarek Burczynski:
  58. ** - binary exact Envelope Generator (verified on real YM2203);
  59. ** identical to YM2151
  60. ** - corrected 'off by one' error in feedback calculations (when feedback is off)
  61. ** - corrected connection (algorithm) calculation (verified on real YM2203 and YM2610)
  62. **
  63. ** 18-12-2001 Jarek Burczynski:
  64. ** - added SSG-EG support (verified on real YM2203)
  65. **
  66. ** 12-08-2001 Jarek Burczynski:
  67. ** - corrected ym_sin_tab and ym_tl_tab data (verified on real chip)
  68. ** - corrected feedback calculations (verified on real chip)
  69. ** - corrected phase generator calculations (verified on real chip)
  70. ** - corrected envelope generator calculations (verified on real chip)
  71. ** - corrected FM volume level (YM2610 and YM2610B).
  72. ** - changed YMxxxUpdateOne() functions (YM2203, YM2608, YM2610, YM2610B, YM2612) :
  73. ** this was needed to calculate YM2610 FM channels output correctly.
  74. ** (Each FM channel is calculated as in other chips, but the output of the channel
  75. ** gets shifted right by one *before* sending to accumulator. That was impossible to do
  76. ** with previous implementation).
  77. **
  78. ** 23-07-2001 Jarek Burczynski, Nicola Salmoria:
  79. ** - corrected YM2610 ADPCM type A algorithm and tables (verified on real chip)
  80. **
  81. ** 11-06-2001 Jarek Burczynski:
  82. ** - corrected end of sample bug in ADPCMA_calc_cha().
  83. ** Real YM2610 checks for equality between current and end addresses (only 20 LSB bits).
  84. **
  85. ** 08-12-98 hiro-shi:
  86. ** rename ADPCMA -> ADPCMB, ADPCMB -> ADPCMA
  87. ** move ROM limit check.(CALC_CH? -> 2610Write1/2)
  88. ** test program (ADPCMB_TEST)
  89. ** move ADPCM A/B end check.
  90. ** ADPCMB repeat flag(no check)
  91. ** change ADPCM volume rate (8->16) (32->48).
  92. **
  93. ** 09-12-98 hiro-shi:
  94. ** change ADPCM volume. (8->16, 48->64)
  95. ** replace ym2610 ch0/3 (YM-2610B)
  96. ** change ADPCM_SHIFT (10->8) missing bank change 0x4000-0xffff.
  97. ** add ADPCM_SHIFT_MASK
  98. ** change ADPCMA_DECODE_MIN/MAX.
  99. */
  100. /************************************************************************/
  101. /* comment of hiro-shi(Hiromitsu Shioya) */
  102. /* YM2610(B) = OPN-B */
  103. /* YM2610 : PSG:3ch FM:4ch ADPCM(18.5KHz):6ch DeltaT ADPCM:1ch */
  104. /* YM2610B : PSG:3ch FM:6ch ADPCM(18.5KHz):6ch DeltaT ADPCM:1ch */
  105. /************************************************************************/
  106. //#include <stdio.h>
  107. #include <string.h>
  108. #include <math.h>
  109. #include "ym2612.h"
  110. #ifndef EXTERNAL_YM2612
  111. #include <stdlib.h>
  112. // let it be 1 global to simplify things
  113. YM2612 ym2612;
  114. #else
  115. extern YM2612 *ym2612_940;
  116. #define ym2612 (*ym2612_940)
  117. #endif
  118. void memset32(void *dest, int c, int count);
  119. #ifndef __GNUC__
  120. #pragma warning (disable:4100) // unreferenced formal parameter
  121. #pragma warning (disable:4244)
  122. #pragma warning (disable:4245) // signed/unsigned in conversion
  123. #pragma warning (disable:4710)
  124. #pragma warning (disable:4018) // signed/unsigned
  125. #endif
  126. #ifndef INLINE
  127. #define INLINE static __inline
  128. #endif
  129. #ifndef M_PI
  130. #define M_PI 3.14159265358979323846
  131. #endif
  132. /* globals */
  133. #define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
  134. #define EG_SH 16 /* 16.16 fixed point (envelope generator timing) */
  135. #define LFO_SH 24 /* 8.24 fixed point (LFO calculations) */
  136. #define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
  137. #define ENV_BITS 10
  138. #define ENV_LEN (1<<ENV_BITS)
  139. #define ENV_STEP (128.0/ENV_LEN)
  140. #define MAX_ATT_INDEX (ENV_LEN-1) /* 1023 */
  141. #define MIN_ATT_INDEX (0) /* 0 */
  142. #define EG_ATT 4
  143. #define EG_DEC 3
  144. #define EG_SUS 2
  145. #define EG_REL 1
  146. #define EG_OFF 0
  147. #define SIN_BITS 10
  148. #define SIN_LEN (1<<SIN_BITS)
  149. #define SIN_MASK (SIN_LEN-1)
  150. #define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
  151. #define EG_TIMER_OVERFLOW (3*(1<<EG_SH)) /* envelope generator timer overflows every 3 samples (on real chip) */
  152. /* TL_TAB_LEN is calculated as:
  153. * 13 - sinus amplitude bits (Y axis)
  154. * 2 - sinus sign bit (Y axis)
  155. * TL_RES_LEN - sinus resolution (X axis)
  156. */
  157. //#define TL_TAB_LEN (13*2*TL_RES_LEN)
  158. #define TL_TAB_LEN (13*TL_RES_LEN*256/8) // 106496*2
  159. UINT16 ym_tl_tab[TL_TAB_LEN];
  160. /* ~3K wasted but oh well */
  161. UINT16 ym_tl_tab2[13*TL_RES_LEN];
  162. #define ENV_QUIET (2*13*TL_RES_LEN/8)
  163. /* sin waveform table in 'decibel' scale (use only period/4 values) */
  164. static UINT16 ym_sin_tab[256];
  165. /* sustain level table (3dB per step) */
  166. /* bit0, bit1, bit2, bit3, bit4, bit5, bit6 */
  167. /* 1, 2, 4, 8, 16, 32, 64 (value)*/
  168. /* 0.75, 1.5, 3, 6, 12, 24, 48 (dB)*/
  169. /* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
  170. #define SC(db) (UINT32) ( db * (4.0/ENV_STEP) )
  171. static const UINT32 sl_table[16]={
  172. SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
  173. SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
  174. };
  175. #undef SC
  176. #if 0
  177. #define RATE_STEPS (8)
  178. static const UINT8 eg_inc[19*RATE_STEPS]={
  179. /*cycle:0 1 2 3 4 5 6 7*/
  180. /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..11 0 (increment by 0 or 1) */
  181. /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..11 1 */
  182. /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..11 2 */
  183. /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..11 3 */
  184. /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 12 0 (increment by 1) */
  185. /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 12 1 */
  186. /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 12 2 */
  187. /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 12 3 */
  188. /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 13 0 (increment by 2) */
  189. /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 13 1 */
  190. /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 13 2 */
  191. /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 13 3 */
  192. /*12 */ 4,4, 4,4, 4,4, 4,4, /* rate 14 0 (increment by 4) */
  193. /*13 */ 4,4, 4,8, 4,4, 4,8, /* rate 14 1 */
  194. /*14 */ 4,8, 4,8, 4,8, 4,8, /* rate 14 2 */
  195. /*15 */ 4,8, 8,8, 4,8, 8,8, /* rate 14 3 */
  196. /*16 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 0, 15 1, 15 2, 15 3 (increment by 8) */
  197. /*17 */ 16,16,16,16,16,16,16,16, /* rates 15 2, 15 3 for attack */
  198. /*18 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
  199. };
  200. #endif
  201. #define PACK(a0,a1,a2,a3,a4,a5,a6,a7) ((a7<<21)|(a6<<18)|(a5<<15)|(a4<<12)|(a3<<9)|(a2<<6)|(a1<<3)|(a0<<0))
  202. static const UINT32 eg_inc_pack[19] =
  203. {
  204. /* 0 */ PACK(0,1,0,1,0,1,0,1), /* rates 00..11 0 (increment by 0 or 1) */
  205. /* 1 */ PACK(0,1,0,1,1,1,0,1), /* rates 00..11 1 */
  206. /* 2 */ PACK(0,1,1,1,0,1,1,1), /* rates 00..11 2 */
  207. /* 3 */ PACK(0,1,1,1,1,1,1,1), /* rates 00..11 3 */
  208. /* 4 */ PACK(1,1,1,1,1,1,1,1), /* rate 12 0 (increment by 1) */
  209. /* 5 */ PACK(1,1,1,2,1,1,1,2), /* rate 12 1 */
  210. /* 6 */ PACK(1,2,1,2,1,2,1,2), /* rate 12 2 */
  211. /* 7 */ PACK(1,2,2,2,1,2,2,2), /* rate 12 3 */
  212. /* 8 */ PACK(2,2,2,2,2,2,2,2), /* rate 13 0 (increment by 2) */
  213. /* 9 */ PACK(2,2,2,3,2,2,2,3), /* rate 13 1 */
  214. /*10 */ PACK(2,3,2,3,2,3,2,3), /* rate 13 2 */
  215. /*11 */ PACK(2,3,3,3,2,3,3,3), /* rate 13 3 */
  216. /*12 */ PACK(3,3,3,3,3,3,3,3), /* rate 14 0 (increment by 4) */
  217. /*13 */ PACK(3,3,3,4,3,3,3,4), /* rate 14 1 */
  218. /*14 */ PACK(3,4,3,4,3,4,3,4), /* rate 14 2 */
  219. /*15 */ PACK(3,4,4,4,3,4,4,4), /* rate 14 3 */
  220. /*16 */ PACK(4,4,4,4,4,4,4,4), /* rates 15 0, 15 1, 15 2, 15 3 (increment by 8) */
  221. /*17 */ PACK(5,5,5,5,5,5,5,5), /* rates 15 2, 15 3 for attack */
  222. /*18 */ PACK(0,0,0,0,0,0,0,0), /* infinity rates for attack and decay(s) */
  223. };
  224. //#define O(a) (a*RATE_STEPS)
  225. #define O(a) a
  226. /*note that there is no O(17) in this table - it's directly in the code */
  227. static const UINT8 eg_rate_select[32+64+32]={ /* Envelope Generator rates (32 + 64 rates + 32 RKS) */
  228. /* 32 infinite time rates */
  229. O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
  230. O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
  231. O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
  232. O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
  233. /* rates 00-11 */
  234. O(18),O(18),O( 2),O( 3),
  235. O( 0),O( 1),O( 2),O( 3),
  236. O( 0),O( 1),O( 2),O( 3),
  237. O( 0),O( 1),O( 2),O( 3),
  238. O( 0),O( 1),O( 2),O( 3),
  239. O( 0),O( 1),O( 2),O( 3),
  240. O( 0),O( 1),O( 2),O( 3),
  241. O( 0),O( 1),O( 2),O( 3),
  242. O( 0),O( 1),O( 2),O( 3),
  243. O( 0),O( 1),O( 2),O( 3),
  244. O( 0),O( 1),O( 2),O( 3),
  245. O( 0),O( 1),O( 2),O( 3),
  246. /* rate 12 */
  247. O( 4),O( 5),O( 6),O( 7),
  248. /* rate 13 */
  249. O( 8),O( 9),O(10),O(11),
  250. /* rate 14 */
  251. O(12),O(13),O(14),O(15),
  252. /* rate 15 */
  253. O(16),O(16),O(16),O(16),
  254. /* 32 dummy rates (same as 15 3) */
  255. O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
  256. O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
  257. O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
  258. O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16)
  259. };
  260. #undef O
  261. /*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15*/
  262. /*shift 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0 */
  263. /*mask 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0, 0 */
  264. #define O(a) (a*1)
  265. static const UINT8 eg_rate_shift[32+64+32]={ /* Envelope Generator counter shifts (32 + 64 rates + 32 RKS) */
  266. /* 32 infinite time rates */
  267. O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
  268. O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
  269. O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
  270. O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
  271. /* rates 00-11 */
  272. O(11),O(11),O(11),O(11),
  273. O(10),O(10),O(10),O(10),
  274. O( 9),O( 9),O( 9),O( 9),
  275. O( 8),O( 8),O( 8),O( 8),
  276. O( 7),O( 7),O( 7),O( 7),
  277. O( 6),O( 6),O( 6),O( 6),
  278. O( 5),O( 5),O( 5),O( 5),
  279. O( 4),O( 4),O( 4),O( 4),
  280. O( 3),O( 3),O( 3),O( 3),
  281. O( 2),O( 2),O( 2),O( 2),
  282. O( 1),O( 1),O( 1),O( 1),
  283. O( 0),O( 0),O( 0),O( 0),
  284. /* rate 12 */
  285. O( 0),O( 0),O( 0),O( 0),
  286. /* rate 13 */
  287. O( 0),O( 0),O( 0),O( 0),
  288. /* rate 14 */
  289. O( 0),O( 0),O( 0),O( 0),
  290. /* rate 15 */
  291. O( 0),O( 0),O( 0),O( 0),
  292. /* 32 dummy rates (same as 15 3) */
  293. O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
  294. O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
  295. O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
  296. O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0)
  297. };
  298. #undef O
  299. static const UINT8 dt_tab[4 * 32]={
  300. /* this is YM2151 and YM2612 phase increment data (in 10.10 fixed point format)*/
  301. /* FD=0 */
  302. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  303. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  304. /* FD=1 */
  305. 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
  306. 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 8, 8, 8,
  307. /* FD=2 */
  308. 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5,
  309. 5, 6, 6, 7, 8, 8, 9,10,11,12,13,14,16,16,16,16,
  310. /* FD=3 */
  311. 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7,
  312. 8 ,8, 9,10,11,12,13,14,16,17,19,20,22,22,22,22
  313. };
  314. /* OPN key frequency number -> key code follow table */
  315. /* fnum higher 4bit -> keycode lower 2bit */
  316. static const UINT8 opn_fktable[16] = {0,0,0,0,0,0,0,1,2,3,3,3,3,3,3,3};
  317. /* 8 LFO speed parameters */
  318. /* each value represents number of samples that one LFO level will last for */
  319. static const UINT32 lfo_samples_per_step[8] = {108, 77, 71, 67, 62, 44, 8, 5};
  320. /*There are 4 different LFO AM depths available, they are:
  321. 0 dB, 1.4 dB, 5.9 dB, 11.8 dB
  322. Here is how it is generated (in EG steps):
  323. 11.8 dB = 0, 2, 4, 6, 8, 10,12,14,16...126,126,124,122,120,118,....4,2,0
  324. 5.9 dB = 0, 1, 2, 3, 4, 5, 6, 7, 8....63, 63, 62, 61, 60, 59,.....2,1,0
  325. 1.4 dB = 0, 0, 0, 0, 1, 1, 1, 1, 2,...15, 15, 15, 15, 14, 14,.....0,0,0
  326. (1.4 dB is loosing precision as you can see)
  327. It's implemented as generator from 0..126 with step 2 then a shift
  328. right N times, where N is:
  329. 8 for 0 dB
  330. 3 for 1.4 dB
  331. 1 for 5.9 dB
  332. 0 for 11.8 dB
  333. */
  334. static const UINT8 lfo_ams_depth_shift[4] = {8, 3, 1, 0};
  335. /*There are 8 different LFO PM depths available, they are:
  336. 0, 3.4, 6.7, 10, 14, 20, 40, 80 (cents)
  337. Modulation level at each depth depends on F-NUMBER bits: 4,5,6,7,8,9,10
  338. (bits 8,9,10 = FNUM MSB from OCT/FNUM register)
  339. Here we store only first quarter (positive one) of full waveform.
  340. Full table (lfo_pm_table) containing all 128 waveforms is build
  341. at run (init) time.
  342. One value in table below represents 4 (four) basic LFO steps
  343. (1 PM step = 4 AM steps).
  344. For example:
  345. at LFO SPEED=0 (which is 108 samples per basic LFO step)
  346. one value from "lfo_pm_output" table lasts for 432 consecutive
  347. samples (4*108=432) and one full LFO waveform cycle lasts for 13824
  348. samples (32*432=13824; 32 because we store only a quarter of whole
  349. waveform in the table below)
  350. */
  351. static const UINT8 lfo_pm_output[7*8][8]={ /* 7 bits meaningful (of F-NUMBER), 8 LFO output levels per one depth (out of 32), 8 LFO depths */
  352. /* FNUM BIT 4: 000 0001xxxx */
  353. /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
  354. /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
  355. /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 0, 0},
  356. /* DEPTH 3 */ {0, 0, 0, 0, 0, 0, 0, 0},
  357. /* DEPTH 4 */ {0, 0, 0, 0, 0, 0, 0, 0},
  358. /* DEPTH 5 */ {0, 0, 0, 0, 0, 0, 0, 0},
  359. /* DEPTH 6 */ {0, 0, 0, 0, 0, 0, 0, 0},
  360. /* DEPTH 7 */ {0, 0, 0, 0, 1, 1, 1, 1},
  361. /* FNUM BIT 5: 000 0010xxxx */
  362. /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
  363. /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
  364. /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 0, 0},
  365. /* DEPTH 3 */ {0, 0, 0, 0, 0, 0, 0, 0},
  366. /* DEPTH 4 */ {0, 0, 0, 0, 0, 0, 0, 0},
  367. /* DEPTH 5 */ {0, 0, 0, 0, 0, 0, 0, 0},
  368. /* DEPTH 6 */ {0, 0, 0, 0, 1, 1, 1, 1},
  369. /* DEPTH 7 */ {0, 0, 1, 1, 2, 2, 2, 3},
  370. /* FNUM BIT 6: 000 0100xxxx */
  371. /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
  372. /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
  373. /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 0, 0},
  374. /* DEPTH 3 */ {0, 0, 0, 0, 0, 0, 0, 0},
  375. /* DEPTH 4 */ {0, 0, 0, 0, 0, 0, 0, 1},
  376. /* DEPTH 5 */ {0, 0, 0, 0, 1, 1, 1, 1},
  377. /* DEPTH 6 */ {0, 0, 1, 1, 2, 2, 2, 3},
  378. /* DEPTH 7 */ {0, 0, 2, 3, 4, 4, 5, 6},
  379. /* FNUM BIT 7: 000 1000xxxx */
  380. /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
  381. /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
  382. /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 1, 1},
  383. /* DEPTH 3 */ {0, 0, 0, 0, 1, 1, 1, 1},
  384. /* DEPTH 4 */ {0, 0, 0, 1, 1, 1, 1, 2},
  385. /* DEPTH 5 */ {0, 0, 1, 1, 2, 2, 2, 3},
  386. /* DEPTH 6 */ {0, 0, 2, 3, 4, 4, 5, 6},
  387. /* DEPTH 7 */ {0, 0, 4, 6, 8, 8, 0xa, 0xc},
  388. /* FNUM BIT 8: 001 0000xxxx */
  389. /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
  390. /* DEPTH 1 */ {0, 0, 0, 0, 1, 1, 1, 1},
  391. /* DEPTH 2 */ {0, 0, 0, 1, 1, 1, 2, 2},
  392. /* DEPTH 3 */ {0, 0, 1, 1, 2, 2, 3, 3},
  393. /* DEPTH 4 */ {0, 0, 1, 2, 2, 2, 3, 4},
  394. /* DEPTH 5 */ {0, 0, 2, 3, 4, 4, 5, 6},
  395. /* DEPTH 6 */ {0, 0, 4, 6, 8, 8, 0xa, 0xc},
  396. /* DEPTH 7 */ {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
  397. /* FNUM BIT 9: 010 0000xxxx */
  398. /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
  399. /* DEPTH 1 */ {0, 0, 0, 0, 2, 2, 2, 2},
  400. /* DEPTH 2 */ {0, 0, 0, 2, 2, 2, 4, 4},
  401. /* DEPTH 3 */ {0, 0, 2, 2, 4, 4, 6, 6},
  402. /* DEPTH 4 */ {0, 0, 2, 4, 4, 4, 6, 8},
  403. /* DEPTH 5 */ {0, 0, 4, 6, 8, 8, 0xa, 0xc},
  404. /* DEPTH 6 */ {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
  405. /* DEPTH 7 */ {0, 0,0x10,0x18,0x20,0x20,0x28,0x30},
  406. /* FNUM BIT10: 100 0000xxxx */
  407. /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
  408. /* DEPTH 1 */ {0, 0, 0, 0, 4, 4, 4, 4},
  409. /* DEPTH 2 */ {0, 0, 0, 4, 4, 4, 8, 8},
  410. /* DEPTH 3 */ {0, 0, 4, 4, 8, 8, 0xc, 0xc},
  411. /* DEPTH 4 */ {0, 0, 4, 8, 8, 8, 0xc,0x10},
  412. /* DEPTH 5 */ {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
  413. /* DEPTH 6 */ {0, 0,0x10,0x18,0x20,0x20,0x28,0x30},
  414. /* DEPTH 7 */ {0, 0,0x20,0x30,0x40,0x40,0x50,0x60},
  415. };
  416. /* all 128 LFO PM waveforms */
  417. static INT32 lfo_pm_table[128*8*32]; /* 128 combinations of 7 bits meaningful (of F-NUMBER), 8 LFO depths, 32 LFO output levels per one depth */
  418. /* there are 2048 FNUMs that can be generated using FNUM/BLK registers
  419. but LFO works with one more bit of a precision so we really need 4096 elements */
  420. static UINT32 fn_table[4096]; /* fnumber->increment counter */
  421. static int g_lfo_ampm;
  422. /* register number to channel number , slot offset */
  423. #define OPN_CHAN(N) (N&3)
  424. #define OPN_SLOT(N) ((N>>2)&3)
  425. /* slot number */
  426. #define SLOT1 0
  427. #define SLOT2 2
  428. #define SLOT3 1
  429. #define SLOT4 3
  430. /* OPN Mode Register Write */
  431. INLINE void set_timers( int v )
  432. {
  433. /* b7 = CSM MODE */
  434. /* b6 = 3 slot mode */
  435. /* b5 = reset b */
  436. /* b4 = reset a */
  437. /* b3 = timer enable b */
  438. /* b2 = timer enable a */
  439. /* b1 = load b */
  440. /* b0 = load a */
  441. ym2612.OPN.ST.mode = v;
  442. /* reset Timer b flag */
  443. if( v & 0x20 )
  444. ym2612.OPN.ST.status &= ~2;
  445. /* reset Timer a flag */
  446. if( v & 0x10 )
  447. ym2612.OPN.ST.status &= ~1;
  448. }
  449. INLINE void recalc_volout(FM_SLOT *SLOT)
  450. {
  451. INT16 vol_out = SLOT->volume;
  452. if ((SLOT->ssg&0x0c) == 0x0c)
  453. vol_out = (0x200 - SLOT->volume) & MAX_ATT_INDEX;
  454. SLOT->vol_out = vol_out + SLOT->tl;
  455. }
  456. INLINE void FM_KEYON(int c , int s )
  457. {
  458. FM_SLOT *SLOT = &ym2612.CH[c].SLOT[s];
  459. if( !SLOT->key )
  460. {
  461. SLOT->key = 1;
  462. SLOT->phase = 0; /* restart Phase Generator */
  463. SLOT->ssg ^= SLOT->ssgn;
  464. SLOT->ssgn = 0;
  465. SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
  466. if (SLOT->ar_ksr < 32+62) {
  467. if (SLOT->volume > MIN_ATT_INDEX) SLOT->state = EG_ATT;
  468. } else {
  469. SLOT->volume = MIN_ATT_INDEX;
  470. }
  471. // recalc_volout(SLOT);
  472. ym2612.slot_mask |= (1<<s) << (c*4);
  473. }
  474. }
  475. INLINE void FM_KEYOFF(int c , int s )
  476. {
  477. FM_SLOT *SLOT = &ym2612.CH[c].SLOT[s];
  478. if( SLOT->key )
  479. {
  480. SLOT->key = 0;
  481. if (SLOT->state>EG_REL) {
  482. SLOT->state = EG_REL;/* phase -> Release */
  483. if (SLOT->ssg&0x08) {
  484. if (SLOT->ssg&0x04)
  485. SLOT->volume = (0x200 - SLOT->volume);
  486. if (SLOT->volume >= 0x200) {
  487. SLOT->volume = MAX_ATT_INDEX;
  488. SLOT->state = EG_OFF;
  489. }
  490. }
  491. }
  492. SLOT->vol_out = SLOT->volume + SLOT->tl;
  493. }
  494. }
  495. /* set detune & multiple */
  496. INLINE void set_det_mul(FM_CH *CH, FM_SLOT *SLOT, int v)
  497. {
  498. SLOT->mul = (v&0x0f)? (v&0x0f)*2 : 1;
  499. SLOT->DT = ym2612.OPN.ST.dt_tab[(v>>4)&7];
  500. CH->SLOT[SLOT1].Incr=-1;
  501. }
  502. /* set total level */
  503. INLINE void set_tl(FM_SLOT *SLOT, int v)
  504. {
  505. SLOT->tl = (v&0x7f)<<(ENV_BITS-7); /* 7bit TL */
  506. // if (SLOT->state > EG_REL)
  507. // recalc_volout(SLOT);
  508. }
  509. /* set attack rate & key scale */
  510. INLINE void set_ar_ksr(FM_CH *CH, FM_SLOT *SLOT, int v)
  511. {
  512. UINT8 old_KSR = SLOT->KSR;
  513. int eg_sh_ar, eg_sel_ar;
  514. SLOT->ar = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
  515. SLOT->ar_ksr = SLOT->ar + SLOT->ksr;
  516. SLOT->KSR = 3-(v>>6);
  517. if (SLOT->KSR != old_KSR)
  518. {
  519. CH->SLOT[SLOT1].Incr=-1;
  520. }
  521. /* refresh Attack rate */
  522. if ((SLOT->ar_ksr) < 32+62)
  523. {
  524. eg_sh_ar = eg_rate_shift [SLOT->ar_ksr];
  525. eg_sel_ar = eg_rate_select[SLOT->ar_ksr];
  526. }
  527. else
  528. {
  529. eg_sh_ar = 0;
  530. eg_sel_ar = 18;
  531. }
  532. SLOT->eg_pack_ar = eg_inc_pack[eg_sel_ar] | (eg_sh_ar<<24);
  533. }
  534. /* set decay rate */
  535. INLINE void set_dr(FM_SLOT *SLOT, int v)
  536. {
  537. int eg_sh_d1r, eg_sel_d1r;
  538. SLOT->d1r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
  539. eg_sh_d1r = eg_rate_shift [SLOT->d1r + SLOT->ksr];
  540. eg_sel_d1r= eg_rate_select[SLOT->d1r + SLOT->ksr];
  541. SLOT->eg_pack_d1r = eg_inc_pack[eg_sel_d1r] | (eg_sh_d1r<<24);
  542. }
  543. /* set sustain rate */
  544. INLINE void set_sr(FM_SLOT *SLOT, int v)
  545. {
  546. int eg_sh_d2r, eg_sel_d2r;
  547. SLOT->d2r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
  548. eg_sh_d2r = eg_rate_shift [SLOT->d2r + SLOT->ksr];
  549. eg_sel_d2r= eg_rate_select[SLOT->d2r + SLOT->ksr];
  550. SLOT->eg_pack_d2r = eg_inc_pack[eg_sel_d2r] | (eg_sh_d2r<<24);
  551. }
  552. /* set release rate */
  553. INLINE void set_sl_rr(FM_SLOT *SLOT, int v)
  554. {
  555. int eg_sh_rr, eg_sel_rr;
  556. SLOT->sl = sl_table[ v>>4 ];
  557. if (SLOT->state == EG_DEC && (SLOT->volume >= (INT32)(SLOT->sl)))
  558. SLOT->state = EG_SUS;
  559. SLOT->rr = 34 + ((v&0x0f)<<2);
  560. eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr];
  561. eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr];
  562. SLOT->eg_pack_rr = eg_inc_pack[eg_sel_rr] | (eg_sh_rr<<24);
  563. }
  564. INLINE signed int op_calc(UINT32 phase, unsigned int env, signed int pm)
  565. {
  566. int ret, sin = (phase>>16) + (pm>>1);
  567. int neg = sin & 0x200;
  568. if (sin & 0x100) sin ^= 0xff;
  569. sin&=0xff;
  570. env&=~1;
  571. // this was already checked
  572. // if (env >= ENV_QUIET) // 384
  573. // return 0;
  574. ret = ym_tl_tab[sin | (env<<7)];
  575. return neg ? -ret : ret;
  576. }
  577. INLINE signed int op_calc1(UINT32 phase, unsigned int env, signed int pm)
  578. {
  579. int ret, sin = (phase+pm)>>16;
  580. int neg = sin & 0x200;
  581. if (sin & 0x100) sin ^= 0xff;
  582. sin&=0xff;
  583. env&=~1;
  584. // if (env >= ENV_QUIET) // 384
  585. // return 0;
  586. ret = ym_tl_tab[sin | (env<<7)];
  587. return neg ? -ret : ret;
  588. }
  589. #if !defined(_ASM_YM2612_C) || defined(EXTERNAL_YM2612)
  590. /* advance LFO to next sample */
  591. INLINE int advance_lfo(int lfo_ampm, UINT32 lfo_cnt_old, UINT32 lfo_cnt)
  592. {
  593. UINT8 pos;
  594. UINT8 prev_pos;
  595. prev_pos = (lfo_cnt_old >> LFO_SH) & 127;
  596. pos = (lfo_cnt >> LFO_SH) & 127;
  597. /* update AM when LFO output changes */
  598. if (prev_pos != pos)
  599. {
  600. lfo_ampm &= 0xff;
  601. /* triangle (inverted) */
  602. /* AM: 0 to 126 step +2, 126 to 0 step -2 */
  603. if (pos<64)
  604. lfo_ampm |= ((pos^63) * 2) << 8; /* 0 - 126 */
  605. else
  606. lfo_ampm |= ((pos&63) * 2) << 8;
  607. }
  608. else
  609. {
  610. return lfo_ampm;
  611. }
  612. /* PM works with 4 times slower clock */
  613. prev_pos >>= 2;
  614. pos >>= 2;
  615. /* update PM when LFO output changes */
  616. if (prev_pos != pos)
  617. {
  618. lfo_ampm &= ~0xff;
  619. lfo_ampm |= pos; /* 0 - 32 */
  620. }
  621. return lfo_ampm;
  622. }
  623. INLINE void update_eg_phase(FM_SLOT *SLOT, UINT32 eg_cnt, UINT32 ssg_en)
  624. {
  625. INT32 volume = SLOT->volume;
  626. UINT32 pack = SLOT->eg_pack[SLOT->state - 1];
  627. UINT32 shift = pack >> 24;
  628. INT32 eg_inc_val;
  629. if (eg_cnt & ((1 << shift) - 1))
  630. return;
  631. eg_inc_val = pack >> ((eg_cnt >> shift) & 7) * 3;
  632. eg_inc_val = (1 << (eg_inc_val & 7)) >> 1;
  633. if ((SLOT->ssg&0x08) && ssg_en) {
  634. switch (SLOT->state)
  635. {
  636. case EG_ATT: /* attack phase */
  637. volume += ( ~volume * eg_inc_val ) >> 4;
  638. if ( volume <= MIN_ATT_INDEX )
  639. {
  640. volume = MIN_ATT_INDEX;
  641. SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS: EG_DEC;
  642. }
  643. break;
  644. case EG_DEC: /* decay phase */
  645. if (volume < 0x200)
  646. volume += 4*eg_inc_val;
  647. if ( volume >= (INT32) SLOT->sl )
  648. SLOT->state = EG_SUS;
  649. break;
  650. case EG_SUS: /* sustain phase */
  651. if (volume < 0x200)
  652. volume += 4*eg_inc_val;
  653. break;
  654. case EG_REL: /* release phase */
  655. if (volume < 0x200)
  656. volume += 4*eg_inc_val;
  657. if ( volume >= 0x200 )
  658. {
  659. volume = MAX_ATT_INDEX;
  660. SLOT->state = EG_OFF;
  661. }
  662. break;
  663. }
  664. SLOT->vol_out = volume + SLOT->tl;
  665. if ((SLOT->ssg&0x04) && (SLOT->state > EG_REL))
  666. SLOT->vol_out = ((0x200 - volume) & MAX_ATT_INDEX) + SLOT->tl;
  667. } else {
  668. switch (SLOT->state)
  669. {
  670. case EG_ATT: /* attack phase */
  671. volume += ( ~volume * eg_inc_val ) >> 4;
  672. if ( volume <= MIN_ATT_INDEX )
  673. {
  674. volume = MIN_ATT_INDEX;
  675. SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS: EG_DEC;
  676. }
  677. break;
  678. case EG_DEC: /* decay phase */
  679. volume += eg_inc_val;
  680. if ( volume >= (INT32) SLOT->sl )
  681. SLOT->state = EG_SUS;
  682. break;
  683. case EG_SUS: /* sustain phase */
  684. volume += eg_inc_val;
  685. if ( volume >= MAX_ATT_INDEX )
  686. {
  687. volume = MAX_ATT_INDEX;
  688. /* do not change SLOT->state (verified on real chip) */
  689. }
  690. break;
  691. case EG_REL: /* release phase */
  692. volume += eg_inc_val;
  693. if ( volume >= MAX_ATT_INDEX )
  694. {
  695. volume = MAX_ATT_INDEX;
  696. SLOT->state = EG_OFF;
  697. }
  698. break;
  699. }
  700. SLOT->vol_out = volume + SLOT->tl;
  701. }
  702. SLOT->volume = volume;
  703. }
  704. INLINE UINT32 update_ssg_eg_phase(FM_SLOT *SLOT, UINT32 phase)
  705. {
  706. if (SLOT->ssg&0x01) {
  707. if (SLOT->ssg&0x02) {
  708. SLOT->ssg ^= SLOT->ssgn ^ 4;
  709. SLOT->ssgn = 4;
  710. }
  711. if (SLOT->state != EG_ATT && !(SLOT->ssg&0x04))
  712. SLOT->volume = MAX_ATT_INDEX;
  713. } else {
  714. if (SLOT->ssg&0x02) {
  715. SLOT->ssg ^= 4;
  716. SLOT->ssgn ^= 4;
  717. } else
  718. phase = 0;
  719. if (SLOT->state != EG_ATT) {
  720. SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
  721. if (SLOT->ar_ksr < 32+62) {
  722. if (SLOT->volume > MIN_ATT_INDEX) SLOT->state = EG_ATT;
  723. } else {
  724. SLOT->volume = MIN_ATT_INDEX;
  725. }
  726. }
  727. }
  728. // recalc_volout(SLOT);
  729. return phase;
  730. }
  731. #endif
  732. typedef struct
  733. {
  734. UINT16 vol_out1; /* 00: current output from EG circuit (without AM from LFO) */
  735. UINT16 vol_out2;
  736. UINT16 vol_out3;
  737. UINT16 vol_out4;
  738. UINT32 pad[2];
  739. UINT32 phase1; /* 10 */
  740. UINT32 phase2;
  741. UINT32 phase3;
  742. UINT32 phase4;
  743. UINT32 incr1; /* 20: phase step */
  744. UINT32 incr2;
  745. UINT32 incr3;
  746. UINT32 incr4;
  747. UINT32 lfo_cnt; /* 30 */
  748. UINT32 lfo_inc;
  749. INT32 mem; /* one sample delay memory */
  750. UINT32 eg_cnt; /* envelope generator counter */
  751. FM_CH *CH; /* 40: envelope generator counter */
  752. UINT32 eg_timer;
  753. UINT32 eg_timer_add;
  754. UINT32 pack; // 4c: stereo, lastchan, disabled, lfo_enabled | pan_r, pan_l, ams[2] | AMmasks[4] | FB[4] | lfo_ampm[16]
  755. UINT32 algo; /* 50: algo[3], was_update */
  756. INT32 op1_out;
  757. #ifdef _MIPS_ARCH_ALLEGREX
  758. UINT32 pad1[3+8];
  759. #endif
  760. } chan_rend_context;
  761. #if !defined(_ASM_YM2612_C) || defined(EXTERNAL_YM2612)
  762. static void chan_render_loop(chan_rend_context *ct, int *buffer, int length)
  763. {
  764. int scounter; /* sample counter */
  765. /* sample generating loop */
  766. for (scounter = 0; scounter < length; scounter++)
  767. {
  768. int smp = 0; /* produced sample */
  769. unsigned int eg_out, eg_out2, eg_out4;
  770. FM_SLOT *SLOT;
  771. UINT32 cnt = ct->eg_timer_add+(ct->eg_timer & ((1<<EG_SH)-1));
  772. if (ct->pack & 2) while (cnt >= 1<<EG_SH) {
  773. cnt -= 1<<EG_SH;
  774. SLOT = &ct->CH->SLOT[SLOT1];
  775. if ((SLOT->ssg&0x08) && SLOT->state > EG_REL && SLOT->volume >= 0x200)
  776. ct->phase1 = update_ssg_eg_phase(SLOT, ct->phase1);
  777. SLOT = &ct->CH->SLOT[SLOT2];
  778. if ((SLOT->ssg&0x08) && SLOT->state > EG_REL && SLOT->volume >= 0x200)
  779. ct->phase2 = update_ssg_eg_phase(SLOT, ct->phase2);
  780. SLOT = &ct->CH->SLOT[SLOT3];
  781. if ((SLOT->ssg&0x08) && SLOT->state > EG_REL && SLOT->volume >= 0x200)
  782. ct->phase3 = update_ssg_eg_phase(SLOT, ct->phase3);
  783. SLOT = &ct->CH->SLOT[SLOT4];
  784. if ((SLOT->ssg&0x08) && SLOT->state > EG_REL && SLOT->volume >= 0x200)
  785. ct->phase4 = update_ssg_eg_phase(SLOT, ct->phase4);
  786. }
  787. if (ct->pack & 8) { /* LFO enabled ? (test Earthworm Jim in between demo 1 and 2) */
  788. ct->pack = (ct->pack&0xffff) | (advance_lfo(ct->pack >> 16, ct->lfo_cnt, ct->lfo_cnt + ct->lfo_inc) << 16);
  789. ct->lfo_cnt += ct->lfo_inc;
  790. }
  791. ct->eg_timer += ct->eg_timer_add;
  792. if (ct->eg_timer < EG_TIMER_OVERFLOW) {
  793. SLOT = &ct->CH->SLOT[SLOT1];
  794. SLOT->vol_ipol = SLOT->vol_out;
  795. if (SLOT->state > EG_REL) recalc_volout(SLOT);
  796. SLOT = &ct->CH->SLOT[SLOT2];
  797. SLOT->vol_ipol = SLOT->vol_out;
  798. if (SLOT->state > EG_REL) recalc_volout(SLOT);
  799. SLOT = &ct->CH->SLOT[SLOT3];
  800. SLOT->vol_ipol = SLOT->vol_out;
  801. if (SLOT->state > EG_REL) recalc_volout(SLOT);
  802. SLOT = &ct->CH->SLOT[SLOT4];
  803. SLOT->vol_ipol = SLOT->vol_out;
  804. if (SLOT->state > EG_REL) recalc_volout(SLOT);
  805. }
  806. else while (ct->eg_timer >= EG_TIMER_OVERFLOW)
  807. {
  808. ct->eg_timer -= EG_TIMER_OVERFLOW;
  809. ct->eg_cnt++;
  810. if (ct->eg_cnt >= 4096) ct->eg_cnt = 1;
  811. SLOT = &ct->CH->SLOT[SLOT1];
  812. SLOT->vol_ipol = SLOT->vol_out;
  813. if (SLOT->state != EG_OFF) update_eg_phase(SLOT, ct->eg_cnt, ct->pack & 2);
  814. SLOT = &ct->CH->SLOT[SLOT2];
  815. SLOT->vol_ipol = SLOT->vol_out;
  816. if (SLOT->state != EG_OFF) update_eg_phase(SLOT, ct->eg_cnt, ct->pack & 2);
  817. SLOT = &ct->CH->SLOT[SLOT3];
  818. SLOT->vol_ipol = SLOT->vol_out;
  819. if (SLOT->state != EG_OFF) update_eg_phase(SLOT, ct->eg_cnt, ct->pack & 2);
  820. SLOT = &ct->CH->SLOT[SLOT4];
  821. SLOT->vol_ipol = SLOT->vol_out;
  822. if (SLOT->state != EG_OFF) update_eg_phase(SLOT, ct->eg_cnt, ct->pack & 2);
  823. }
  824. #if 0
  825. UINT32 ifrac0 = ct->eg_timer / (EG_TIMER_OVERFLOW>>EG_SH);
  826. UINT32 ifrac1 = (1<<EG_SH) - ifrac0;
  827. SLOT = &ct->CH->SLOT[SLOT1];
  828. ct->vol_out1 = (SLOT->vol_ipol*ifrac1 + SLOT->vol_out*ifrac0) >> EG_SH;
  829. SLOT = &ct->CH->SLOT[SLOT2];
  830. ct->vol_out2 = (SLOT->vol_ipol*ifrac1 + SLOT->vol_out*ifrac0) >> EG_SH;
  831. SLOT = &ct->CH->SLOT[SLOT3];
  832. ct->vol_out3 = (SLOT->vol_ipol*ifrac1 + SLOT->vol_out*ifrac0) >> EG_SH;
  833. SLOT = &ct->CH->SLOT[SLOT4];
  834. ct->vol_out4 = (SLOT->vol_ipol*ifrac1 + SLOT->vol_out*ifrac0) >> EG_SH;
  835. #elif 1
  836. switch (ct->eg_timer >> EG_SH)
  837. {
  838. case 0:
  839. ct->vol_out1 = ct->CH->SLOT[SLOT1].vol_ipol;
  840. ct->vol_out2 = ct->CH->SLOT[SLOT2].vol_ipol;
  841. ct->vol_out3 = ct->CH->SLOT[SLOT3].vol_ipol;
  842. ct->vol_out4 = ct->CH->SLOT[SLOT4].vol_ipol;
  843. break;
  844. case (EG_TIMER_OVERFLOW>>EG_SH)-1:
  845. ct->vol_out1 = ct->CH->SLOT[SLOT1].vol_out;
  846. ct->vol_out2 = ct->CH->SLOT[SLOT2].vol_out;
  847. ct->vol_out3 = ct->CH->SLOT[SLOT3].vol_out;
  848. ct->vol_out4 = ct->CH->SLOT[SLOT4].vol_out;
  849. break;
  850. default:
  851. ct->vol_out1 = (ct->CH->SLOT[SLOT1].vol_ipol +
  852. ct->CH->SLOT[SLOT1].vol_out) >> 1;
  853. ct->vol_out2 = (ct->CH->SLOT[SLOT2].vol_ipol +
  854. ct->CH->SLOT[SLOT2].vol_out) >> 1;
  855. ct->vol_out3 = (ct->CH->SLOT[SLOT3].vol_ipol +
  856. ct->CH->SLOT[SLOT3].vol_out) >> 1;
  857. ct->vol_out4 = (ct->CH->SLOT[SLOT4].vol_ipol +
  858. ct->CH->SLOT[SLOT4].vol_out) >> 1;
  859. break;
  860. }
  861. #elif 0
  862. if (ct->eg_timer >> (EG_SH-1) < EG_TIMER_OVERFLOW >> EG_SH) {
  863. ct->vol_out1 = ct->CH->SLOT[SLOT1].vol_ipol;
  864. ct->vol_out2 = ct->CH->SLOT[SLOT2].vol_ipol;
  865. ct->vol_out3 = ct->CH->SLOT[SLOT3].vol_ipol;
  866. ct->vol_out4 = ct->CH->SLOT[SLOT4].vol_ipol;
  867. } else {
  868. ct->vol_out1 = ct->CH->SLOT[SLOT1].vol_out;
  869. ct->vol_out2 = ct->CH->SLOT[SLOT2].vol_out;
  870. ct->vol_out3 = ct->CH->SLOT[SLOT3].vol_out;
  871. ct->vol_out4 = ct->CH->SLOT[SLOT4].vol_out;
  872. }
  873. #else
  874. ct->vol_out1 = ct->CH->SLOT[SLOT1].vol_out;
  875. ct->vol_out2 = ct->CH->SLOT[SLOT2].vol_out;
  876. ct->vol_out3 = ct->CH->SLOT[SLOT3].vol_out;
  877. ct->vol_out4 = ct->CH->SLOT[SLOT4].vol_out;
  878. #endif
  879. if (ct->pack & 4) continue; /* output disabled */
  880. /* calculate channel sample */
  881. eg_out = ct->vol_out1;
  882. if ( (ct->pack & 8) && (ct->pack&(1<<(SLOT1+8))) ) eg_out += ct->pack >> (((ct->pack&0xc0)>>6)+24);
  883. if( eg_out < ENV_QUIET ) /* SLOT 1 */
  884. {
  885. int out = 0;
  886. if (ct->pack&0xf000) out = ((ct->op1_out>>16) + ((ct->op1_out<<16)>>16)) << ((ct->pack&0xf000)>>12); /* op1_out0 + op1_out1 */
  887. ct->op1_out <<= 16;
  888. ct->op1_out |= (unsigned short)op_calc1(ct->phase1, eg_out, out);
  889. } else {
  890. ct->op1_out <<= 16; /* op1_out0 = op1_out1; op1_out1 = 0; */
  891. }
  892. eg_out = ct->vol_out3; // volume_calc(&CH->SLOT[SLOT3]);
  893. eg_out2 = ct->vol_out2; // volume_calc(&CH->SLOT[SLOT2]);
  894. eg_out4 = ct->vol_out4; // volume_calc(&CH->SLOT[SLOT4]);
  895. if (ct->pack & 8) {
  896. unsigned int add = ct->pack >> (((ct->pack&0xc0)>>6)+24);
  897. if (ct->pack & (1<<(SLOT3+8))) eg_out += add;
  898. if (ct->pack & (1<<(SLOT2+8))) eg_out2 += add;
  899. if (ct->pack & (1<<(SLOT4+8))) eg_out4 += add;
  900. }
  901. switch( ct->algo&0x7 )
  902. {
  903. case 0:
  904. {
  905. /* M1---C1---MEM---M2---C2---OUT */
  906. int m2,c1,c2=0; /* Phase Modulation input for operators 2,3,4 */
  907. m2 = ct->mem;
  908. c1 = ct->op1_out>>16;
  909. if( eg_out < ENV_QUIET ) { /* SLOT 3 */
  910. c2 = op_calc(ct->phase3, eg_out, m2);
  911. }
  912. if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
  913. ct->mem = op_calc(ct->phase2, eg_out2, c1);
  914. }
  915. else ct->mem = 0;
  916. if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
  917. smp = op_calc(ct->phase4, eg_out4, c2);
  918. }
  919. break;
  920. }
  921. case 1:
  922. {
  923. /* M1------+-MEM---M2---C2---OUT */
  924. /* C1-+ */
  925. int m2,c2=0;
  926. m2 = ct->mem;
  927. ct->mem = ct->op1_out>>16;
  928. if( eg_out < ENV_QUIET ) { /* SLOT 3 */
  929. c2 = op_calc(ct->phase3, eg_out, m2);
  930. }
  931. if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
  932. ct->mem+= op_calc(ct->phase2, eg_out2, 0);
  933. }
  934. if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
  935. smp = op_calc(ct->phase4, eg_out4, c2);
  936. }
  937. break;
  938. }
  939. case 2:
  940. {
  941. /* M1-----------------+-C2---OUT */
  942. /* C1---MEM---M2-+ */
  943. int m2,c2;
  944. m2 = ct->mem;
  945. c2 = ct->op1_out>>16;
  946. if( eg_out < ENV_QUIET ) { /* SLOT 3 */
  947. c2 += op_calc(ct->phase3, eg_out, m2);
  948. }
  949. if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
  950. ct->mem = op_calc(ct->phase2, eg_out2, 0);
  951. }
  952. else ct->mem = 0;
  953. if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
  954. smp = op_calc(ct->phase4, eg_out4, c2);
  955. }
  956. break;
  957. }
  958. case 3:
  959. {
  960. /* M1---C1---MEM------+-C2---OUT */
  961. /* M2-+ */
  962. int c1,c2;
  963. c2 = ct->mem;
  964. c1 = ct->op1_out>>16;
  965. if( eg_out < ENV_QUIET ) { /* SLOT 3 */
  966. c2 += op_calc(ct->phase3, eg_out, 0);
  967. }
  968. if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
  969. ct->mem = op_calc(ct->phase2, eg_out2, c1);
  970. }
  971. else ct->mem = 0;
  972. if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
  973. smp = op_calc(ct->phase4, eg_out4, c2);
  974. }
  975. break;
  976. }
  977. case 4:
  978. {
  979. /* M1---C1-+-OUT */
  980. /* M2---C2-+ */
  981. /* MEM: not used */
  982. int c1,c2=0;
  983. c1 = ct->op1_out>>16;
  984. if( eg_out < ENV_QUIET ) { /* SLOT 3 */
  985. c2 = op_calc(ct->phase3, eg_out, 0);
  986. }
  987. if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
  988. smp = op_calc(ct->phase2, eg_out2, c1);
  989. }
  990. if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
  991. smp+= op_calc(ct->phase4, eg_out4, c2);
  992. }
  993. break;
  994. }
  995. case 5:
  996. {
  997. /* +----C1----+ */
  998. /* M1-+-MEM---M2-+-OUT */
  999. /* +----C2----+ */
  1000. int m2,c1,c2;
  1001. m2 = ct->mem;
  1002. ct->mem = c1 = c2 = ct->op1_out>>16;
  1003. if( eg_out < ENV_QUIET ) { /* SLOT 3 */
  1004. smp = op_calc(ct->phase3, eg_out, m2);
  1005. }
  1006. if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
  1007. smp+= op_calc(ct->phase2, eg_out2, c1);
  1008. }
  1009. if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
  1010. smp+= op_calc(ct->phase4, eg_out4, c2);
  1011. }
  1012. break;
  1013. }
  1014. case 6:
  1015. {
  1016. /* M1---C1-+ */
  1017. /* M2-+-OUT */
  1018. /* C2-+ */
  1019. /* MEM: not used */
  1020. int c1;
  1021. c1 = ct->op1_out>>16;
  1022. if( eg_out < ENV_QUIET ) { /* SLOT 3 */
  1023. smp = op_calc(ct->phase3, eg_out, 0);
  1024. }
  1025. if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
  1026. smp+= op_calc(ct->phase2, eg_out2, c1);
  1027. }
  1028. if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
  1029. smp+= op_calc(ct->phase4, eg_out4, 0);
  1030. }
  1031. break;
  1032. }
  1033. case 7:
  1034. {
  1035. /* M1-+ */
  1036. /* C1-+-OUT */
  1037. /* M2-+ */
  1038. /* C2-+ */
  1039. /* MEM: not used*/
  1040. smp = ct->op1_out>>16;
  1041. if( eg_out < ENV_QUIET ) { /* SLOT 3 */
  1042. smp += op_calc(ct->phase3, eg_out, 0);
  1043. }
  1044. if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
  1045. smp += op_calc(ct->phase2, eg_out2, 0);
  1046. }
  1047. if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
  1048. smp += op_calc(ct->phase4, eg_out4, 0);
  1049. }
  1050. break;
  1051. }
  1052. }
  1053. /* done calculating channel sample */
  1054. /* mix sample to output buffer */
  1055. if (smp) {
  1056. if (ct->pack & 1) { /* stereo */
  1057. if (ct->pack & 0x20) /* L */ /* TODO: check correctness */
  1058. buffer[scounter*2] += smp;
  1059. if (ct->pack & 0x10) /* R */
  1060. buffer[scounter*2+1] += smp;
  1061. } else {
  1062. buffer[scounter] += smp;
  1063. }
  1064. ct->algo |= 8;
  1065. }
  1066. /* update phase counters AFTER output calculations */
  1067. ct->phase1 += ct->incr1;
  1068. ct->phase2 += ct->incr2;
  1069. ct->phase3 += ct->incr3;
  1070. ct->phase4 += ct->incr4;
  1071. }
  1072. }
  1073. #else
  1074. void chan_render_loop(chan_rend_context *ct, int *buffer, unsigned short length);
  1075. #endif
  1076. static chan_rend_context crct;
  1077. static void chan_render_prep(void)
  1078. {
  1079. crct.eg_timer_add = ym2612.OPN.eg_timer_add;
  1080. crct.lfo_inc = ym2612.OPN.lfo_inc;
  1081. }
  1082. static void chan_render_finish(void)
  1083. {
  1084. ym2612.OPN.eg_cnt = crct.eg_cnt;
  1085. ym2612.OPN.eg_timer = crct.eg_timer;
  1086. g_lfo_ampm = crct.pack >> 16; // need_save
  1087. ym2612.OPN.lfo_cnt = crct.lfo_cnt;
  1088. }
  1089. static UINT32 update_lfo_phase(FM_SLOT *SLOT, UINT32 block_fnum)
  1090. {
  1091. UINT32 fnum_lfo;
  1092. INT32 lfo_fn_table_index_offset;
  1093. UINT8 blk;
  1094. UINT32 fn;
  1095. int fc,fdt;
  1096. fnum_lfo = ((block_fnum & 0x7f0) >> 4) * 32 * 8;
  1097. lfo_fn_table_index_offset = lfo_pm_table[ fnum_lfo + crct.CH->pms + ((crct.pack>>16)&0xff) ];
  1098. if (lfo_fn_table_index_offset) /* LFO phase modulation active */
  1099. {
  1100. block_fnum = block_fnum*2 + lfo_fn_table_index_offset;
  1101. blk = (block_fnum&0x7000) >> 12;
  1102. fn = block_fnum & 0xfff;
  1103. /* phase increment counter */
  1104. fc = (fn_table[fn]>>(7-blk));
  1105. fdt = fc + SLOT->DT[crct.CH->kcode];
  1106. if (fdt < 0) fdt += fn_table[0x7ff*2] >> 2;
  1107. return (fdt * SLOT->mul) >> 1;
  1108. } else
  1109. return SLOT->Incr;
  1110. }
  1111. static int chan_render(int *buffer, int length, int c, UINT32 flags) // flags: stereo, ?, disabled, ?, pan_r, pan_l
  1112. {
  1113. crct.CH = &ym2612.CH[c];
  1114. crct.mem = crct.CH->mem_value; /* one sample delay memory */
  1115. crct.lfo_cnt = ym2612.OPN.lfo_cnt;
  1116. flags &= 0x37;
  1117. if (crct.lfo_inc) {
  1118. flags |= 8;
  1119. flags |= g_lfo_ampm << 16;
  1120. flags |= crct.CH->AMmasks << 8;
  1121. if (crct.CH->ams == 8) // no ams
  1122. flags &= ~0xf00;
  1123. else flags |= (crct.CH->ams&3)<<6;
  1124. }
  1125. flags |= (crct.CH->FB&0xf)<<12; /* feedback shift */
  1126. crct.pack = flags;
  1127. crct.eg_cnt = ym2612.OPN.eg_cnt; /* envelope generator counter */
  1128. crct.eg_timer = ym2612.OPN.eg_timer;
  1129. /* precalculate phase modulation incr */
  1130. crct.phase1 = crct.CH->SLOT[SLOT1].phase;
  1131. crct.phase2 = crct.CH->SLOT[SLOT2].phase;
  1132. crct.phase3 = crct.CH->SLOT[SLOT3].phase;
  1133. crct.phase4 = crct.CH->SLOT[SLOT4].phase;
  1134. crct.op1_out = crct.CH->op1_out;
  1135. crct.algo = crct.CH->ALGO & 7;
  1136. if(crct.CH->pms && (ym2612.OPN.ST.mode & 0xC0) && c == 2) {
  1137. /* 3 slot mode */
  1138. crct.incr1 = update_lfo_phase(&crct.CH->SLOT[SLOT1], ym2612.OPN.SL3.block_fnum[1]);
  1139. crct.incr2 = update_lfo_phase(&crct.CH->SLOT[SLOT2], ym2612.OPN.SL3.block_fnum[2]);
  1140. crct.incr3 = update_lfo_phase(&crct.CH->SLOT[SLOT3], ym2612.OPN.SL3.block_fnum[0]);
  1141. crct.incr4 = update_lfo_phase(&crct.CH->SLOT[SLOT4], crct.CH->block_fnum);
  1142. }
  1143. else if(crct.CH->pms)
  1144. {
  1145. crct.incr1 = update_lfo_phase(&crct.CH->SLOT[SLOT1], crct.CH->block_fnum);
  1146. crct.incr2 = update_lfo_phase(&crct.CH->SLOT[SLOT2], crct.CH->block_fnum);
  1147. crct.incr3 = update_lfo_phase(&crct.CH->SLOT[SLOT3], crct.CH->block_fnum);
  1148. crct.incr4 = update_lfo_phase(&crct.CH->SLOT[SLOT4], crct.CH->block_fnum);
  1149. }
  1150. else /* no LFO phase modulation */
  1151. {
  1152. crct.incr1 = crct.CH->SLOT[SLOT1].Incr;
  1153. crct.incr2 = crct.CH->SLOT[SLOT2].Incr;
  1154. crct.incr3 = crct.CH->SLOT[SLOT3].Incr;
  1155. crct.incr4 = crct.CH->SLOT[SLOT4].Incr;
  1156. }
  1157. chan_render_loop(&crct, buffer, length);
  1158. crct.CH->op1_out = crct.op1_out;
  1159. crct.CH->mem_value = crct.mem;
  1160. if (crct.CH->SLOT[SLOT1].state | crct.CH->SLOT[SLOT2].state | crct.CH->SLOT[SLOT3].state | crct.CH->SLOT[SLOT4].state)
  1161. {
  1162. crct.CH->SLOT[SLOT1].phase = crct.phase1;
  1163. crct.CH->SLOT[SLOT2].phase = crct.phase2;
  1164. crct.CH->SLOT[SLOT3].phase = crct.phase3;
  1165. crct.CH->SLOT[SLOT4].phase = crct.phase4;
  1166. }
  1167. else
  1168. ym2612.slot_mask &= ~(0xf << (c*4));
  1169. return (crct.algo & 8) >> 3; // had output
  1170. }
  1171. /* update phase increment and envelope generator */
  1172. INLINE void refresh_fc_eg_slot(FM_SLOT *SLOT, int fc, int kc)
  1173. {
  1174. int ksr, fdt;
  1175. /* (frequency) phase increment counter */
  1176. fdt = fc+SLOT->DT[kc];
  1177. /* detect overflow */
  1178. // if (fdt < 0) fdt += fn_table[0x7ff*2] >> (7-blk-1);
  1179. if (fdt < 0) fdt += fn_table[0x7ff*2] >> 2;
  1180. SLOT->Incr = fdt*SLOT->mul >> 1;
  1181. ksr = kc >> SLOT->KSR;
  1182. if( SLOT->ksr != ksr )
  1183. {
  1184. int eg_sh, eg_sel;
  1185. SLOT->ksr = ksr;
  1186. SLOT->ar_ksr = SLOT->ar + ksr;
  1187. /* calculate envelope generator rates */
  1188. if ((SLOT->ar_ksr) < 32+62)
  1189. {
  1190. eg_sh = eg_rate_shift [SLOT->ar_ksr];
  1191. eg_sel = eg_rate_select[SLOT->ar_ksr];
  1192. }
  1193. else
  1194. {
  1195. eg_sh = 0;
  1196. eg_sel = 18;
  1197. }
  1198. SLOT->eg_pack_ar = eg_inc_pack[eg_sel] | (eg_sh<<24);
  1199. eg_sh = eg_rate_shift [SLOT->d1r + ksr];
  1200. eg_sel = eg_rate_select[SLOT->d1r + ksr];
  1201. SLOT->eg_pack_d1r = eg_inc_pack[eg_sel] | (eg_sh<<24);
  1202. eg_sh = eg_rate_shift [SLOT->d2r + ksr];
  1203. eg_sel = eg_rate_select[SLOT->d2r + ksr];
  1204. SLOT->eg_pack_d2r = eg_inc_pack[eg_sel] | (eg_sh<<24);
  1205. eg_sh = eg_rate_shift [SLOT->rr + ksr];
  1206. eg_sel = eg_rate_select[SLOT->rr + ksr];
  1207. SLOT->eg_pack_rr = eg_inc_pack[eg_sel] | (eg_sh<<24);
  1208. }
  1209. }
  1210. /* update phase increment counters */
  1211. INLINE void refresh_fc_eg_chan(FM_CH *CH)
  1212. {
  1213. if( CH->SLOT[SLOT1].Incr==-1){
  1214. int fc = CH->fc;
  1215. int kc = CH->kcode;
  1216. refresh_fc_eg_slot(&CH->SLOT[SLOT1] , fc , kc );
  1217. refresh_fc_eg_slot(&CH->SLOT[SLOT2] , fc , kc );
  1218. refresh_fc_eg_slot(&CH->SLOT[SLOT3] , fc , kc );
  1219. refresh_fc_eg_slot(&CH->SLOT[SLOT4] , fc , kc );
  1220. }
  1221. }
  1222. INLINE void refresh_fc_eg_chan_sl3(void)
  1223. {
  1224. if( ym2612.CH[2].SLOT[SLOT1].Incr==-1)
  1225. {
  1226. refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT1], ym2612.OPN.SL3.fc[1], ym2612.OPN.SL3.kcode[1] );
  1227. refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT2], ym2612.OPN.SL3.fc[2], ym2612.OPN.SL3.kcode[2] );
  1228. refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT3], ym2612.OPN.SL3.fc[0], ym2612.OPN.SL3.kcode[0] );
  1229. refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT4], ym2612.CH[2].fc , ym2612.CH[2].kcode );
  1230. }
  1231. }
  1232. /* initialize time tables */
  1233. static void init_timetables(const UINT8 *dttable)
  1234. {
  1235. int i,d;
  1236. double rate;
  1237. /* DeTune table */
  1238. for (d = 0;d <= 3;d++){
  1239. for (i = 0;i <= 31;i++){
  1240. rate = ((double)dttable[d*32 + i]) * ym2612.OPN.ST.freqbase * (1<<(FREQ_SH-10));
  1241. ym2612.OPN.ST.dt_tab[d][i] = (INT32) rate;
  1242. ym2612.OPN.ST.dt_tab[d+4][i] = -ym2612.OPN.ST.dt_tab[d][i];
  1243. }
  1244. }
  1245. }
  1246. static void reset_channels(FM_CH *CH)
  1247. {
  1248. int c,s;
  1249. ym2612.OPN.ST.mode = 0; /* normal mode */
  1250. ym2612.OPN.ST.TA = 0;
  1251. ym2612.OPN.ST.TAC = 0;
  1252. ym2612.OPN.ST.TB = 0;
  1253. ym2612.OPN.ST.TBC = 0;
  1254. for( c = 0 ; c < 6 ; c++ )
  1255. {
  1256. CH[c].fc = 0;
  1257. for(s = 0 ; s < 4 ; s++ )
  1258. {
  1259. CH[c].SLOT[s].Incr = -1;
  1260. CH[c].SLOT[s].key = 0;
  1261. CH[c].SLOT[s].phase = 0;
  1262. CH[c].SLOT[s].ssg = CH[c].SLOT[s].ssgn = 0;
  1263. CH[c].SLOT[s].state= EG_OFF;
  1264. CH[c].SLOT[s].volume = MAX_ATT_INDEX;
  1265. CH[c].SLOT[s].vol_out = MAX_ATT_INDEX;
  1266. }
  1267. CH[c].mem_value = CH[c].op1_out = 0;
  1268. }
  1269. ym2612.slot_mask = 0;
  1270. ym2612.ssg_mask = 0;
  1271. }
  1272. /* initialize generic tables */
  1273. static void init_tables(void)
  1274. {
  1275. signed int i,x,y,p;
  1276. signed int n;
  1277. double o,m;
  1278. for (i=0; i < 256; i++)
  1279. {
  1280. /* non-standard sinus */
  1281. m = sin( ((i*2)+1) * M_PI / SIN_LEN ); /* checked against the real chip */
  1282. /* we never reach zero here due to ((i*2)+1) */
  1283. if (m>0.0)
  1284. o = 8*log(1.0/m)/log(2); /* convert to 'decibels' */
  1285. else
  1286. o = 8*log(-1.0/m)/log(2); /* convert to 'decibels' */
  1287. o = o / (ENV_STEP/4);
  1288. n = (int)(2.0*o);
  1289. if (n&1) /* round to nearest */
  1290. n = (n>>1)+1;
  1291. else
  1292. n = n>>1;
  1293. ym_sin_tab[ i ] = n;
  1294. //dprintf("FM.C: sin [%4i]= %4i", i, ym_sin_tab[i]);
  1295. }
  1296. //dprintf("FM.C: ENV_QUIET= %08x", ENV_QUIET );
  1297. for (x=0; x < TL_RES_LEN; x++)
  1298. {
  1299. m = (1<<16) / pow(2, (x+1) * (ENV_STEP/4.0) / 8.0);
  1300. m = floor(m);
  1301. /* we never reach (1<<16) here due to the (x+1) */
  1302. /* result fits within 16 bits at maximum */
  1303. n = (int)m; /* 16 bits here */
  1304. n >>= 4; /* 12 bits here */
  1305. if (n&1) /* round to nearest */
  1306. n = (n>>1)+1;
  1307. else
  1308. n = n>>1;
  1309. /* 11 bits here (rounded) */
  1310. n <<= 2; /* 13 bits here (as in real chip) */
  1311. ym_tl_tab2[ x ] = n;
  1312. for (i=1; i < 13; i++)
  1313. {
  1314. ym_tl_tab2[ x + i*TL_RES_LEN ] = n >> i;
  1315. }
  1316. }
  1317. for (x=0; x < 256; x++)
  1318. {
  1319. int sin = ym_sin_tab[ x ];
  1320. for (y=0; y < 2*13*TL_RES_LEN/8; y+=2)
  1321. {
  1322. p = (y<<2) + sin;
  1323. if (p >= 13*TL_RES_LEN)
  1324. ym_tl_tab[(y<<7) | x] = 0;
  1325. else ym_tl_tab[(y<<7) | x] = ym_tl_tab2[p];
  1326. }
  1327. }
  1328. /* build LFO PM modulation table */
  1329. for(i = 0; i < 8; i++) /* 8 PM depths */
  1330. {
  1331. UINT8 fnum;
  1332. for (fnum=0; fnum<128; fnum++) /* 7 bits meaningful of F-NUMBER */
  1333. {
  1334. UINT8 value;
  1335. UINT8 step;
  1336. UINT32 offset_depth = i;
  1337. UINT32 offset_fnum_bit;
  1338. UINT32 bit_tmp;
  1339. for (step=0; step<8; step++)
  1340. {
  1341. value = 0;
  1342. for (bit_tmp=0; bit_tmp<7; bit_tmp++) /* 7 bits */
  1343. {
  1344. if (fnum & (1<<bit_tmp)) /* only if bit "bit_tmp" is set */
  1345. {
  1346. offset_fnum_bit = bit_tmp * 8;
  1347. value += lfo_pm_output[offset_fnum_bit + offset_depth][step];
  1348. }
  1349. }
  1350. lfo_pm_table[(fnum*32*8) + (i*32) + step + 0] = value;
  1351. lfo_pm_table[(fnum*32*8) + (i*32) +(step^7)+ 8] = value;
  1352. lfo_pm_table[(fnum*32*8) + (i*32) + step +16] = -value;
  1353. lfo_pm_table[(fnum*32*8) + (i*32) +(step^7)+24] = -value;
  1354. }
  1355. }
  1356. }
  1357. }
  1358. /* CSM Key Controll */
  1359. #if 0
  1360. INLINE void CSMKeyControll(FM_CH *CH)
  1361. {
  1362. /* this is wrong, atm */
  1363. /* all key on */
  1364. FM_KEYON(CH,SLOT1);
  1365. FM_KEYON(CH,SLOT2);
  1366. FM_KEYON(CH,SLOT3);
  1367. FM_KEYON(CH,SLOT4);
  1368. }
  1369. #endif
  1370. /* prescaler set (and make time tables) */
  1371. static void OPNSetPres(int pres)
  1372. {
  1373. int i;
  1374. /* frequency base */
  1375. ym2612.OPN.ST.freqbase = (ym2612.OPN.ST.rate) ? ((double)ym2612.OPN.ST.clock / ym2612.OPN.ST.rate) / pres : 0;
  1376. ym2612.OPN.eg_timer_add = (1<<EG_SH) * ym2612.OPN.ST.freqbase;
  1377. /* make time tables */
  1378. init_timetables( dt_tab );
  1379. /* there are 2048 FNUMs that can be generated using FNUM/BLK registers
  1380. but LFO works with one more bit of a precision so we really need 4096 elements */
  1381. /* calculate fnumber -> increment counter table */
  1382. for(i = 0; i < 4096; i++)
  1383. {
  1384. /* freq table for octave 7 */
  1385. /* OPN phase increment counter = 20bit */
  1386. fn_table[i] = (UINT32)( (double)i * 32 * ym2612.OPN.ST.freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
  1387. }
  1388. /* LFO freq. table */
  1389. for(i = 0; i < 8; i++)
  1390. {
  1391. /* Amplitude modulation: 64 output levels (triangle waveform); 1 level lasts for one of "lfo_samples_per_step" samples */
  1392. /* Phase modulation: one entry from lfo_pm_output lasts for one of 4 * "lfo_samples_per_step" samples */
  1393. ym2612.OPN.lfo_freq[i] = (1.0 / lfo_samples_per_step[i]) * (1<<LFO_SH) * ym2612.OPN.ST.freqbase;
  1394. }
  1395. }
  1396. /* write a OPN register (0x30-0xff) */
  1397. static int OPNWriteReg(int r, int v)
  1398. {
  1399. int ret = 1;
  1400. FM_CH *CH;
  1401. FM_SLOT *SLOT;
  1402. UINT8 c = OPN_CHAN(r);
  1403. if (c == 3) return 0; /* 0xX3,0xX7,0xXB,0xXF */
  1404. if (r >= 0x100) c+=3;
  1405. CH = &ym2612.CH[c];
  1406. SLOT = &(CH->SLOT[OPN_SLOT(r)]);
  1407. switch( r & 0xf0 ) {
  1408. case 0x30: /* DET , MUL */
  1409. set_det_mul(CH,SLOT,v);
  1410. break;
  1411. case 0x40: /* TL */
  1412. set_tl(SLOT,v);
  1413. break;
  1414. case 0x50: /* KS, AR */
  1415. set_ar_ksr(CH,SLOT,v);
  1416. break;
  1417. case 0x60: /* bit7 = AM ENABLE, DR | depends on ksr */
  1418. set_dr(SLOT,v);
  1419. if(v&0x80) CH->AMmasks |= 1<<OPN_SLOT(r);
  1420. else CH->AMmasks &= ~(1<<OPN_SLOT(r));
  1421. break;
  1422. case 0x70: /* SR | depends on ksr */
  1423. set_sr(SLOT,v);
  1424. break;
  1425. case 0x80: /* SL, RR | depends on ksr */
  1426. set_sl_rr(SLOT,v);
  1427. break;
  1428. case 0x90: /* SSG-EG */
  1429. SLOT->ssg = v&0x0f;
  1430. SLOT->ssg ^= SLOT->ssgn;
  1431. if (v&0x08) ym2612.ssg_mask |= 1<<(OPN_SLOT(r) + c*4);
  1432. else ym2612.ssg_mask &= ~(1<<(OPN_SLOT(r) + c*4));
  1433. // if (SLOT->state > EG_REL)
  1434. // recalc_volout(SLOT);
  1435. break;
  1436. case 0xa0:
  1437. switch( OPN_SLOT(r) ){
  1438. case 0: /* 0xa0-0xa2 : FNUM1 | depends on fn_h (below) */
  1439. {
  1440. UINT32 fn = (((UINT32)( (CH->fn_h)&7))<<8) + v;
  1441. UINT8 blk = CH->fn_h>>3;
  1442. /* keyscale code */
  1443. CH->kcode = (blk<<2) | opn_fktable[fn >> 7];
  1444. /* phase increment counter */
  1445. CH->fc = fn_table[fn*2]>>(7-blk);
  1446. /* store fnum in clear form for LFO PM calculations */
  1447. CH->block_fnum = (blk<<11) | fn;
  1448. CH->SLOT[SLOT1].Incr=-1;
  1449. }
  1450. break;
  1451. case 1: /* 0xa4-0xa6 : FNUM2,BLK */
  1452. CH->fn_h = v&0x3f;
  1453. ret = 0;
  1454. break;
  1455. case 2: /* 0xa8-0xaa : 3CH FNUM1 */
  1456. if(r < 0x100)
  1457. {
  1458. UINT32 fn = (((UINT32)(ym2612.OPN.SL3.fn_h&7))<<8) + v;
  1459. UINT8 blk = ym2612.OPN.SL3.fn_h>>3;
  1460. /* keyscale code */
  1461. ym2612.OPN.SL3.kcode[c]= (blk<<2) | opn_fktable[fn >> 7];
  1462. /* phase increment counter */
  1463. ym2612.OPN.SL3.fc[c] = fn_table[fn*2]>>(7-blk);
  1464. ym2612.OPN.SL3.block_fnum[c] = (blk<<11) | fn;
  1465. ym2612.CH[2].SLOT[SLOT1].Incr=-1;
  1466. }
  1467. break;
  1468. case 3: /* 0xac-0xae : 3CH FNUM2,BLK */
  1469. if(r < 0x100)
  1470. ym2612.OPN.SL3.fn_h = v&0x3f;
  1471. ret = 0;
  1472. break;
  1473. default:
  1474. ret = 0;
  1475. break;
  1476. }
  1477. break;
  1478. case 0xb0:
  1479. switch( OPN_SLOT(r) ){
  1480. case 0: /* 0xb0-0xb2 : FB,ALGO */
  1481. {
  1482. int feedback = (v>>3)&7;
  1483. CH->ALGO = v&7;
  1484. CH->FB = feedback ? feedback+6 : 0;
  1485. }
  1486. break;
  1487. case 1: /* 0xb4-0xb6 : L , R , AMS , PMS (YM2612/YM2610B/YM2610/YM2608) */
  1488. {
  1489. int panshift = c<<1;
  1490. /* b0-2 PMS */
  1491. CH->pms = (v & 7) * 32; /* CH->pms = PM depth * 32 (index in lfo_pm_table) */
  1492. /* b4-5 AMS */
  1493. CH->ams = lfo_ams_depth_shift[(v>>4) & 3];
  1494. /* PAN : b7 = L, b6 = R */
  1495. ym2612.OPN.pan &= ~(3<<panshift);
  1496. ym2612.OPN.pan |= ((v & 0xc0) >> 6) << panshift; // ..LRLR
  1497. }
  1498. break;
  1499. default:
  1500. ret = 0;
  1501. break;
  1502. }
  1503. break;
  1504. default:
  1505. ret = 0;
  1506. break;
  1507. }
  1508. return ret;
  1509. }
  1510. /*******************************************************************************/
  1511. /* YM2612 local section */
  1512. /*******************************************************************************/
  1513. /* Generate samples for YM2612 */
  1514. int YM2612UpdateOne_(int *buffer, int length, int stereo, int is_buf_empty)
  1515. {
  1516. int pan;
  1517. int active_chs = 0;
  1518. int flags = stereo ? 1:0;
  1519. // if !is_buf_empty, it means it has valid samples to mix with, else it may contain trash
  1520. if (is_buf_empty) memset32(buffer, 0, length<<stereo);
  1521. /*
  1522. {
  1523. int c, s;
  1524. ppp();
  1525. for (c = 0; c < 6; c++) {
  1526. int slr = 0, slm;
  1527. printf("%i: ", c);
  1528. for (s = 0; s < 4; s++) {
  1529. if (ym2612.CH[c].SLOT[s].state != EG_OFF) slr = 1;
  1530. printf(" %i", ym2612.CH[c].SLOT[s].state != EG_OFF);
  1531. }
  1532. slm = (ym2612.slot_mask&(0xf<<(c*4))) ? 1 : 0;
  1533. printf(" | %i", slm);
  1534. printf(" | %i\n", ym2612.CH[c].SLOT[SLOT1].Incr==-1);
  1535. if (slr != slm) exit(1);
  1536. }
  1537. }
  1538. */
  1539. /* refresh PG and EG */
  1540. refresh_fc_eg_chan( &ym2612.CH[0] );
  1541. refresh_fc_eg_chan( &ym2612.CH[1] );
  1542. if( (ym2612.OPN.ST.mode & 0xc0) )
  1543. /* 3SLOT MODE */
  1544. refresh_fc_eg_chan_sl3();
  1545. else
  1546. refresh_fc_eg_chan( &ym2612.CH[2] );
  1547. refresh_fc_eg_chan( &ym2612.CH[3] );
  1548. refresh_fc_eg_chan( &ym2612.CH[4] );
  1549. refresh_fc_eg_chan( &ym2612.CH[5] );
  1550. pan = ym2612.OPN.pan;
  1551. /* mix to 32bit dest */
  1552. // flags: stereo, ssg_enabled, disabled, _, pan_r, pan_l
  1553. chan_render_prep();
  1554. #define BIT_IF(v,b,c) { v &= ~(1<<(b)); if (c) v |= 1<<(b); }
  1555. BIT_IF(flags, 1, (ym2612.ssg_mask & 0x00000f) && (ym2612.OPN.ST.flags & 1));
  1556. if (ym2612.slot_mask & 0x00000f) active_chs |= chan_render(buffer, length, 0, flags|((pan&0x003)<<4)) << 0;
  1557. BIT_IF(flags, 1, (ym2612.ssg_mask & 0x0000f0) && (ym2612.OPN.ST.flags & 1));
  1558. if (ym2612.slot_mask & 0x0000f0) active_chs |= chan_render(buffer, length, 1, flags|((pan&0x00c)<<2)) << 1;
  1559. BIT_IF(flags, 1, (ym2612.ssg_mask & 0x000f00) && (ym2612.OPN.ST.flags & 1));
  1560. if (ym2612.slot_mask & 0x000f00) active_chs |= chan_render(buffer, length, 2, flags|((pan&0x030) )) << 2;
  1561. BIT_IF(flags, 1, (ym2612.ssg_mask & 0x00f000) && (ym2612.OPN.ST.flags & 1));
  1562. if (ym2612.slot_mask & 0x00f000) active_chs |= chan_render(buffer, length, 3, flags|((pan&0x0c0)>>2)) << 3;
  1563. BIT_IF(flags, 1, (ym2612.ssg_mask & 0x0f0000) && (ym2612.OPN.ST.flags & 1));
  1564. if (ym2612.slot_mask & 0x0f0000) active_chs |= chan_render(buffer, length, 4, flags|((pan&0x300)>>4)) << 4;
  1565. BIT_IF(flags, 1, (ym2612.ssg_mask & 0xf00000) && (ym2612.OPN.ST.flags & 1));
  1566. if (ym2612.slot_mask & 0xf00000) active_chs |= chan_render(buffer, length, 5, flags|((pan&0xc00)>>6)|(!!ym2612.dacen<<2)) << 5;
  1567. #undef BIT_IF
  1568. chan_render_finish();
  1569. return active_chs; // 1 if buffer updated
  1570. }
  1571. /* initialize YM2612 emulator */
  1572. void YM2612Init_(int clock, int rate, int ssg)
  1573. {
  1574. memset(&ym2612, 0, sizeof(ym2612));
  1575. init_tables();
  1576. ym2612.OPN.ST.clock = clock;
  1577. ym2612.OPN.ST.rate = rate;
  1578. ym2612.OPN.ST.flags = (ssg ? 1:0);
  1579. OPNSetPres( 6*24 );
  1580. /* Extend handler */
  1581. YM2612ResetChip_();
  1582. }
  1583. /* reset */
  1584. void YM2612ResetChip_(void)
  1585. {
  1586. int i;
  1587. memset(ym2612.REGS, 0, sizeof(ym2612.REGS));
  1588. set_timers( 0x30 ); /* mode 0 , timer reset */
  1589. ym2612.REGS[0x27] = 0x30;
  1590. ym2612.OPN.eg_timer = 0;
  1591. ym2612.OPN.eg_cnt = 0;
  1592. ym2612.OPN.lfo_inc = 0;
  1593. ym2612.OPN.lfo_cnt = 0;
  1594. g_lfo_ampm = 126 << 8;
  1595. ym2612.OPN.ST.status = 0;
  1596. reset_channels( &ym2612.CH[0] );
  1597. for(i = 0xb6 ; i >= 0xb4 ; i-- )
  1598. {
  1599. OPNWriteReg(i ,0xc0);
  1600. OPNWriteReg(i|0x100,0xc0);
  1601. ym2612.REGS[i ] = 0xc0;
  1602. ym2612.REGS[i|0x100] = 0xc0;
  1603. }
  1604. for(i = 0xb2 ; i >= 0x30 ; i-- )
  1605. {
  1606. OPNWriteReg(i ,0);
  1607. OPNWriteReg(i|0x100,0);
  1608. }
  1609. for(i = 0x26 ; i >= 0x20 ; i-- ) OPNWriteReg(i,0);
  1610. /* DAC mode clear */
  1611. ym2612.dacen = 0;
  1612. ym2612.dacout = 0;
  1613. ym2612.addr_A1 = 0;
  1614. }
  1615. /* YM2612 write */
  1616. /* a = address */
  1617. /* v = value */
  1618. /* returns 1 if sample affecting state changed */
  1619. int YM2612Write_(unsigned int a, unsigned int v)
  1620. {
  1621. int addr, ret=1;
  1622. v &= 0xff; /* adjust to 8 bit bus */
  1623. switch( a & 3 ){
  1624. case 0: /* address port 0 */
  1625. case 2: /* address port 1 */
  1626. ym2612.OPN.ST.address = v;
  1627. ym2612.addr_A1 = (a & 2) >> 1;
  1628. ret = 0;
  1629. break;
  1630. case 1:
  1631. case 3: /* data port */
  1632. addr = ym2612.OPN.ST.address | ((int)ym2612.addr_A1 << 8);
  1633. switch( addr & 0x1f0 )
  1634. {
  1635. case 0x20: /* 0x20-0x2f Mode */
  1636. switch( addr )
  1637. {
  1638. case 0x22: /* LFO FREQ (YM2608/YM2610/YM2610B/YM2612) */
  1639. if (v&0x08) /* LFO enabled ? */
  1640. {
  1641. ym2612.OPN.lfo_inc = ym2612.OPN.lfo_freq[v&7];
  1642. }
  1643. else
  1644. {
  1645. ym2612.OPN.lfo_inc = 0;
  1646. ym2612.OPN.lfo_cnt = 0;
  1647. g_lfo_ampm = 126 << 8;
  1648. }
  1649. break;
  1650. #if 0 // handled elsewhere
  1651. case 0x24: { // timer A High 8
  1652. int TAnew = (ym2612.OPN.ST.TA & 0x03)|(((int)v)<<2);
  1653. if(ym2612.OPN.ST.TA != TAnew) {
  1654. // we should reset ticker only if new value is written. Outrun requires this.
  1655. ym2612.OPN.ST.TA = TAnew;
  1656. ym2612.OPN.ST.TAC = (1024-TAnew)*18;
  1657. ym2612.OPN.ST.TAT = 0;
  1658. }
  1659. }
  1660. ret=0;
  1661. break;
  1662. case 0x25: { // timer A Low 2
  1663. int TAnew = (ym2612.OPN.ST.TA & 0x3fc)|(v&3);
  1664. if(ym2612.OPN.ST.TA != TAnew) {
  1665. ym2612.OPN.ST.TA = TAnew;
  1666. ym2612.OPN.ST.TAC = (1024-TAnew)*18;
  1667. ym2612.OPN.ST.TAT = 0;
  1668. }
  1669. }
  1670. ret=0;
  1671. break;
  1672. case 0x26: // timer B
  1673. if(ym2612.OPN.ST.TB != v) {
  1674. ym2612.OPN.ST.TB = v;
  1675. ym2612.OPN.ST.TBC = (256-v)<<4;
  1676. ym2612.OPN.ST.TBC *= 18;
  1677. ym2612.OPN.ST.TBT = 0;
  1678. }
  1679. ret=0;
  1680. break;
  1681. #endif
  1682. case 0x27: /* mode, timer control */
  1683. set_timers( v );
  1684. ret=0;
  1685. break;
  1686. case 0x28: /* key on / off */
  1687. {
  1688. UINT8 c;
  1689. c = v & 0x03;
  1690. if( c == 3 ) { ret=0; break; }
  1691. if( v&0x04 ) c+=3;
  1692. if(v&0x10) FM_KEYON(c,SLOT1); else FM_KEYOFF(c,SLOT1);
  1693. if(v&0x20) FM_KEYON(c,SLOT2); else FM_KEYOFF(c,SLOT2);
  1694. if(v&0x40) FM_KEYON(c,SLOT3); else FM_KEYOFF(c,SLOT3);
  1695. if(v&0x80) FM_KEYON(c,SLOT4); else FM_KEYOFF(c,SLOT4);
  1696. break;
  1697. }
  1698. case 0x2a: /* DAC data (YM2612) */
  1699. ym2612.dacout = ((int)v - 0x80) << 6; /* level unknown (notaz: 8 seems to be too much) */
  1700. ret=0;
  1701. break;
  1702. case 0x2b: /* DAC Sel (YM2612) */
  1703. /* b7 = dac enable */
  1704. ym2612.dacen = v & 0x80;
  1705. ret=0;
  1706. break;
  1707. default:
  1708. break;
  1709. }
  1710. break;
  1711. default: /* 0x30-0xff OPN section */
  1712. /* write register */
  1713. ret = OPNWriteReg(addr,v);
  1714. }
  1715. break;
  1716. }
  1717. return ret;
  1718. }
  1719. #if 0
  1720. UINT8 YM2612Read_(void)
  1721. {
  1722. return ym2612.OPN.ST.status;
  1723. }
  1724. int YM2612PicoTick_(int n)
  1725. {
  1726. int ret = 0;
  1727. // timer A
  1728. if(ym2612.OPN.ST.mode & 0x01 && (ym2612.OPN.ST.TAT+=64*n) >= ym2612.OPN.ST.TAC) {
  1729. ym2612.OPN.ST.TAT -= ym2612.OPN.ST.TAC;
  1730. if(ym2612.OPN.ST.mode & 0x04) ym2612.OPN.ST.status |= 1;
  1731. // CSM mode total level latch and auto key on
  1732. if(ym2612.OPN.ST.mode & 0x80) {
  1733. CSMKeyControll( &(ym2612.CH[2]) ); // Vectorman2, etc.
  1734. ret = 1;
  1735. }
  1736. }
  1737. // timer B
  1738. if(ym2612.OPN.ST.mode & 0x02 && (ym2612.OPN.ST.TBT+=64*n) >= ym2612.OPN.ST.TBC) {
  1739. ym2612.OPN.ST.TBT -= ym2612.OPN.ST.TBC;
  1740. if(ym2612.OPN.ST.mode & 0x08) ym2612.OPN.ST.status |= 2;
  1741. }
  1742. return ret;
  1743. }
  1744. #endif
  1745. void YM2612PicoStateLoad_(void)
  1746. {
  1747. reset_channels( &ym2612.CH[0] );
  1748. ym2612.slot_mask = 0xffffff;
  1749. }
  1750. /* rather stupid design because I wanted to fit in unused register "space" */
  1751. typedef struct
  1752. {
  1753. UINT32 state_phase;
  1754. INT16 volume;
  1755. } ym_save_addon_slot;
  1756. typedef struct
  1757. {
  1758. UINT32 magic;
  1759. UINT8 address;
  1760. UINT8 status;
  1761. UINT8 addr_A1;
  1762. UINT8 unused;
  1763. int TAT;
  1764. int TBT;
  1765. UINT32 eg_cnt; // 10
  1766. UINT32 eg_timer;
  1767. UINT32 lfo_cnt;
  1768. UINT16 lfo_ampm;
  1769. UINT16 unused2;
  1770. UINT32 keyon_field; // 20
  1771. UINT32 kcode_fc_sl3_3;
  1772. UINT32 reserved[2];
  1773. } ym_save_addon;
  1774. typedef struct
  1775. {
  1776. UINT16 block_fnum[6];
  1777. UINT16 block_fnum_sl3[3];
  1778. UINT16 reserved[7];
  1779. } ym_save_addon2;
  1780. void YM2612PicoStateSave2(int tat, int tbt)
  1781. {
  1782. ym_save_addon_slot ss;
  1783. ym_save_addon2 sa2;
  1784. ym_save_addon sa;
  1785. unsigned char *ptr;
  1786. int c, s;
  1787. memset(&sa, 0, sizeof(sa));
  1788. memset(&sa2, 0, sizeof(sa2));
  1789. // chans 1,2,3
  1790. ptr = &ym2612.REGS[0x0b8];
  1791. for (c = 0; c < 3; c++)
  1792. {
  1793. for (s = 0; s < 4; s++) {
  1794. ss.state_phase = (ym2612.CH[c].SLOT[s].state << 29) | (ym2612.CH[c].SLOT[s].phase >> 3);
  1795. ss.volume = ym2612.CH[c].SLOT[s].volume;
  1796. if (ym2612.CH[c].SLOT[s].key)
  1797. sa.keyon_field |= 1 << (c*4 + s);
  1798. memcpy(ptr, &ss, 6);
  1799. ptr += 6;
  1800. }
  1801. sa2.block_fnum[c] = ym2612.CH[c].block_fnum;
  1802. }
  1803. // chans 4,5,6
  1804. ptr = &ym2612.REGS[0x1b8];
  1805. for (; c < 6; c++)
  1806. {
  1807. for (s = 0; s < 4; s++) {
  1808. ss.state_phase = (ym2612.CH[c].SLOT[s].state << 29) | (ym2612.CH[c].SLOT[s].phase >> 3);
  1809. ss.volume = ym2612.CH[c].SLOT[s].volume;
  1810. if (ym2612.CH[c].SLOT[s].key)
  1811. sa.keyon_field |= 1 << (c*4 + s);
  1812. memcpy(ptr, &ss, 6);
  1813. ptr += 6;
  1814. }
  1815. sa2.block_fnum[c] = ym2612.CH[c].block_fnum;
  1816. }
  1817. for (c = 0; c < 3; c++)
  1818. {
  1819. sa2.block_fnum_sl3[c] = ym2612.OPN.SL3.block_fnum[c];
  1820. }
  1821. memcpy(&ym2612.REGS[0], &sa2, sizeof(sa2)); // 0x20 max
  1822. // other things
  1823. ptr = &ym2612.REGS[0x100];
  1824. sa.magic = 0x41534d59; // 'YMSA'
  1825. sa.address = ym2612.OPN.ST.address;
  1826. sa.status = ym2612.OPN.ST.status;
  1827. sa.addr_A1 = ym2612.addr_A1;
  1828. sa.TAT = tat;
  1829. sa.TBT = tbt;
  1830. sa.eg_cnt = ym2612.OPN.eg_cnt;
  1831. sa.eg_timer = ym2612.OPN.eg_timer;
  1832. sa.lfo_cnt = ym2612.OPN.lfo_cnt;
  1833. sa.lfo_ampm = g_lfo_ampm;
  1834. memcpy(ptr, &sa, sizeof(sa)); // 0x30 max
  1835. }
  1836. int YM2612PicoStateLoad2(int *tat, int *tbt)
  1837. {
  1838. ym_save_addon_slot ss;
  1839. ym_save_addon2 sa2;
  1840. ym_save_addon sa;
  1841. unsigned char *ptr;
  1842. UINT32 fn;
  1843. UINT8 blk;
  1844. int c, s;
  1845. ptr = &ym2612.REGS[0x100];
  1846. memcpy(&sa, ptr, sizeof(sa)); // 0x30 max
  1847. if (sa.magic != 0x41534d59) return -1;
  1848. ptr = &ym2612.REGS[0];
  1849. memcpy(&sa2, ptr, sizeof(sa2));
  1850. ym2612.OPN.ST.address = sa.address;
  1851. ym2612.OPN.ST.status = sa.status;
  1852. ym2612.addr_A1 = sa.addr_A1;
  1853. ym2612.OPN.eg_cnt = sa.eg_cnt;
  1854. ym2612.OPN.eg_timer = sa.eg_timer;
  1855. ym2612.OPN.lfo_cnt = sa.lfo_cnt;
  1856. g_lfo_ampm = sa.lfo_ampm;
  1857. if (tat != NULL) *tat = sa.TAT;
  1858. if (tbt != NULL) *tbt = sa.TBT;
  1859. // chans 1,2,3
  1860. ptr = &ym2612.REGS[0x0b8];
  1861. for (c = 0; c < 3; c++)
  1862. {
  1863. for (s = 0; s < 4; s++) {
  1864. memcpy(&ss, ptr, 6);
  1865. ym2612.CH[c].SLOT[s].state = ss.state_phase >> 29;
  1866. ym2612.CH[c].SLOT[s].phase = ss.state_phase << 3;
  1867. ym2612.CH[c].SLOT[s].volume = ss.volume;
  1868. ym2612.CH[c].SLOT[s].key = (sa.keyon_field & (1 << (c*4 + s))) ? 1 : 0;
  1869. ym2612.CH[c].SLOT[s].ksr = (UINT8)-1;
  1870. ptr += 6;
  1871. }
  1872. ym2612.CH[c].SLOT[SLOT1].Incr=-1;
  1873. ym2612.CH[c].block_fnum = sa2.block_fnum[c];
  1874. fn = ym2612.CH[c].block_fnum & 0x7ff;
  1875. blk = ym2612.CH[c].block_fnum >> 11;
  1876. ym2612.CH[c].kcode= (blk<<2) | opn_fktable[fn >> 7];
  1877. ym2612.CH[c].fc = fn_table[fn*2]>>(7-blk);
  1878. }
  1879. // chans 4,5,6
  1880. ptr = &ym2612.REGS[0x1b8];
  1881. for (; c < 6; c++)
  1882. {
  1883. for (s = 0; s < 4; s++) {
  1884. memcpy(&ss, ptr, 6);
  1885. ym2612.CH[c].SLOT[s].state = ss.state_phase >> 29;
  1886. ym2612.CH[c].SLOT[s].phase = ss.state_phase << 3;
  1887. ym2612.CH[c].SLOT[s].volume = ss.volume;
  1888. ym2612.CH[c].SLOT[s].key = (sa.keyon_field & (1 << (c*4 + s))) ? 1 : 0;
  1889. ym2612.CH[c].SLOT[s].ksr = (UINT8)-1;
  1890. ptr += 6;
  1891. }
  1892. ym2612.CH[c].SLOT[SLOT1].Incr=-1;
  1893. ym2612.CH[c].block_fnum = sa2.block_fnum[c];
  1894. fn = ym2612.CH[c].block_fnum & 0x7ff;
  1895. blk = ym2612.CH[c].block_fnum >> 11;
  1896. ym2612.CH[c].kcode= (blk<<2) | opn_fktable[fn >> 7];
  1897. ym2612.CH[c].fc = fn_table[fn*2]>>(7-blk);
  1898. }
  1899. for (c = 0; c < 3; c++)
  1900. {
  1901. ym2612.OPN.SL3.block_fnum[c] = sa2.block_fnum_sl3[c];
  1902. fn = ym2612.OPN.SL3.block_fnum[c] & 0x7ff;
  1903. blk = ym2612.OPN.SL3.block_fnum[c] >> 11;
  1904. ym2612.OPN.SL3.kcode[c]= (blk<<2) | opn_fktable[fn >> 7];
  1905. ym2612.OPN.SL3.fc[c] = fn_table[fn*2]>>(7-blk);
  1906. }
  1907. return 0;
  1908. }
  1909. void *YM2612GetRegs(void)
  1910. {
  1911. return ym2612.REGS;
  1912. }