memory.c 37 KB

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  1. /*
  2. * memory handling
  3. * (c) Copyright Dave, 2004
  4. * (C) notaz, 2006-2010
  5. *
  6. * This work is licensed under the terms of MAME license.
  7. * See COPYING file in the top-level directory.
  8. */
  9. #include "pico_int.h"
  10. #include "memory.h"
  11. #include "sound/ym2612.h"
  12. #include "sound/sn76496.h"
  13. extern unsigned int lastSSRamWrite; // used by serial eeprom code
  14. uptr m68k_read8_map [0x1000000 >> M68K_MEM_SHIFT];
  15. uptr m68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];
  16. uptr m68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];
  17. uptr m68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];
  18. static void xmap_set(uptr *map, int shift, int start_addr, int end_addr,
  19. const void *func_or_mh, int is_func)
  20. {
  21. #ifdef __clang__
  22. // workaround bug (segfault) in
  23. // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)
  24. volatile
  25. #endif
  26. uptr addr = (uptr)func_or_mh;
  27. int mask = (1 << shift) - 1;
  28. int i;
  29. if ((start_addr & mask) != 0 || (end_addr & mask) != mask) {
  30. elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: tried to map bad range: %06x-%06x",
  31. start_addr, end_addr);
  32. return;
  33. }
  34. if (addr & 1) {
  35. elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: ptr is not aligned: %08lx", addr);
  36. return;
  37. }
  38. if (!is_func)
  39. addr -= start_addr;
  40. for (i = start_addr >> shift; i <= end_addr >> shift; i++) {
  41. map[i] = addr >> 1;
  42. if (is_func)
  43. map[i] |= MAP_FLAG;
  44. }
  45. }
  46. void z80_map_set(uptr *map, int start_addr, int end_addr,
  47. const void *func_or_mh, int is_func)
  48. {
  49. xmap_set(map, Z80_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);
  50. }
  51. void cpu68k_map_set(uptr *map, int start_addr, int end_addr,
  52. const void *func_or_mh, int is_func)
  53. {
  54. xmap_set(map, M68K_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);
  55. #ifdef EMU_F68K
  56. // setup FAME fetchmap
  57. if (!is_func)
  58. {
  59. int shiftout = 24 - FAMEC_FETCHBITS;
  60. int i = start_addr >> shiftout;
  61. uptr base = (uptr)func_or_mh - (i << shiftout);
  62. for (; i <= (end_addr >> shiftout); i++)
  63. PicoCpuFM68k.Fetch[i] = base;
  64. }
  65. #endif
  66. }
  67. // more specialized/optimized function (does same as above)
  68. void cpu68k_map_all_ram(int start_addr, int end_addr, void *ptr, int is_sub)
  69. {
  70. uptr *r8map, *r16map, *w8map, *w16map;
  71. uptr addr = (uptr)ptr;
  72. int shift = M68K_MEM_SHIFT;
  73. int i;
  74. if (!is_sub) {
  75. r8map = m68k_read8_map;
  76. r16map = m68k_read16_map;
  77. w8map = m68k_write8_map;
  78. w16map = m68k_write16_map;
  79. } else {
  80. r8map = s68k_read8_map;
  81. r16map = s68k_read16_map;
  82. w8map = s68k_write8_map;
  83. w16map = s68k_write16_map;
  84. }
  85. addr -= start_addr;
  86. addr >>= 1;
  87. for (i = start_addr >> shift; i <= end_addr >> shift; i++)
  88. r8map[i] = r16map[i] = w8map[i] = w16map[i] = addr;
  89. #ifdef EMU_F68K
  90. // setup FAME fetchmap
  91. {
  92. M68K_CONTEXT *ctx = is_sub ? &PicoCpuFS68k : &PicoCpuFM68k;
  93. int shiftout = 24 - FAMEC_FETCHBITS;
  94. i = start_addr >> shiftout;
  95. addr = (uptr)ptr - (i << shiftout);
  96. for (; i <= (end_addr >> shiftout); i++)
  97. ctx->Fetch[i] = addr;
  98. }
  99. #endif
  100. }
  101. static u32 m68k_unmapped_read8(u32 a)
  102. {
  103. elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
  104. return 0; // assume pulldown, as if MegaCD2 was attached
  105. }
  106. static u32 m68k_unmapped_read16(u32 a)
  107. {
  108. elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
  109. return 0;
  110. }
  111. static void m68k_unmapped_write8(u32 a, u32 d)
  112. {
  113. elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  114. }
  115. static void m68k_unmapped_write16(u32 a, u32 d)
  116. {
  117. elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  118. }
  119. void m68k_map_unmap(int start_addr, int end_addr)
  120. {
  121. #ifdef __clang__
  122. // workaround bug (segfault) in
  123. // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)
  124. volatile
  125. #endif
  126. uptr addr;
  127. int shift = M68K_MEM_SHIFT;
  128. int i;
  129. addr = (uptr)m68k_unmapped_read8;
  130. for (i = start_addr >> shift; i <= end_addr >> shift; i++)
  131. m68k_read8_map[i] = (addr >> 1) | MAP_FLAG;
  132. addr = (uptr)m68k_unmapped_read16;
  133. for (i = start_addr >> shift; i <= end_addr >> shift; i++)
  134. m68k_read16_map[i] = (addr >> 1) | MAP_FLAG;
  135. addr = (uptr)m68k_unmapped_write8;
  136. for (i = start_addr >> shift; i <= end_addr >> shift; i++)
  137. m68k_write8_map[i] = (addr >> 1) | MAP_FLAG;
  138. addr = (uptr)m68k_unmapped_write16;
  139. for (i = start_addr >> shift; i <= end_addr >> shift; i++)
  140. m68k_write16_map[i] = (addr >> 1) | MAP_FLAG;
  141. }
  142. #ifndef _ASM_MEMORY_C
  143. MAKE_68K_READ8(m68k_read8, m68k_read8_map)
  144. MAKE_68K_READ16(m68k_read16, m68k_read16_map)
  145. MAKE_68K_READ32(m68k_read32, m68k_read16_map)
  146. MAKE_68K_WRITE8(m68k_write8, m68k_write8_map)
  147. MAKE_68K_WRITE16(m68k_write16, m68k_write16_map)
  148. MAKE_68K_WRITE32(m68k_write32, m68k_write16_map)
  149. #endif
  150. // -----------------------------------------------------------------
  151. static u32 ym2612_read_local_68k(void);
  152. static int ym2612_write_local(u32 a, u32 d, int is_from_z80);
  153. static void z80_mem_setup(void);
  154. #ifdef _ASM_MEMORY_C
  155. u32 PicoRead8_sram(u32 a);
  156. u32 PicoRead16_sram(u32 a);
  157. #endif
  158. #ifdef EMU_CORE_DEBUG
  159. u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};
  160. int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0;
  161. extern unsigned int ppop;
  162. #endif
  163. #ifdef IO_STATS
  164. void log_io(unsigned int addr, int bits, int rw);
  165. #elif defined(_MSC_VER)
  166. #define log_io
  167. #else
  168. #define log_io(...)
  169. #endif
  170. #if defined(EMU_C68K)
  171. void cyclone_crashed(u32 pc, struct Cyclone *context)
  172. {
  173. elprintf(EL_STATUS|EL_ANOMALY, "%c68k crash detected @ %06x",
  174. context == &PicoCpuCM68k ? 'm' : 's', pc);
  175. context->membase = (u32)Pico.rom;
  176. context->pc = (u32)Pico.rom + Pico.romsize;
  177. }
  178. #endif
  179. // -----------------------------------------------------------------
  180. // memmap helpers
  181. static u32 read_pad_3btn(int i, u32 out_bits)
  182. {
  183. u32 pad = ~PicoIn.padInt[i]; // Get inverse of pad MXYZ SACB RLDU
  184. u32 value;
  185. if (out_bits & 0x40) // TH
  186. value = pad & 0x3f; // ?1CB RLDU
  187. else
  188. value = ((pad & 0xc0) >> 2) | (pad & 3); // ?0SA 00DU
  189. value |= out_bits & 0x40;
  190. return value;
  191. }
  192. static u32 read_pad_6btn(int i, u32 out_bits)
  193. {
  194. u32 pad = ~PicoIn.padInt[i]; // Get inverse of pad MXYZ SACB RLDU
  195. int phase = Pico.m.padTHPhase[i];
  196. u32 value;
  197. if (phase == 2 && !(out_bits & 0x40)) {
  198. value = (pad & 0xc0) >> 2; // ?0SA 0000
  199. goto out;
  200. }
  201. else if(phase == 3) {
  202. if (out_bits & 0x40)
  203. return (pad & 0x30) | ((pad >> 8) & 0xf); // ?1CB MXYZ
  204. else
  205. return ((pad & 0xc0) >> 2) | 0x0f; // ?0SA 1111
  206. goto out;
  207. }
  208. if (out_bits & 0x40) // TH
  209. value = pad & 0x3f; // ?1CB RLDU
  210. else
  211. value = ((pad & 0xc0) >> 2) | (pad & 3); // ?0SA 00DU
  212. out:
  213. value |= out_bits & 0x40;
  214. return value;
  215. }
  216. static u32 read_nothing(int i, u32 out_bits)
  217. {
  218. return 0xff;
  219. }
  220. typedef u32 (port_read_func)(int index, u32 out_bits);
  221. static port_read_func *port_readers[3] = {
  222. read_pad_3btn,
  223. read_pad_3btn,
  224. read_nothing
  225. };
  226. static NOINLINE u32 port_read(int i)
  227. {
  228. u32 data_reg = PicoMem.ioports[i + 1];
  229. u32 ctrl_reg = PicoMem.ioports[i + 4] | 0x80;
  230. u32 in, out;
  231. out = data_reg & ctrl_reg;
  232. // pull-ups: should be 0x7f, but Decap Attack has a bug where it temp.
  233. // disables output before doing TH-low read, so don't emulate it for TH.
  234. // Decap Attack reportedly doesn't work on Nomad but works on must
  235. // other MD revisions (different pull-up strength?).
  236. out |= 0x3f & ~ctrl_reg;
  237. in = port_readers[i](i, out);
  238. return (in & ~ctrl_reg) | (data_reg & ctrl_reg);
  239. }
  240. void PicoSetInputDevice(int port, enum input_device device)
  241. {
  242. port_read_func *func;
  243. if (port < 0 || port > 2)
  244. return;
  245. switch (device) {
  246. case PICO_INPUT_PAD_3BTN:
  247. func = read_pad_3btn;
  248. break;
  249. case PICO_INPUT_PAD_6BTN:
  250. func = read_pad_6btn;
  251. break;
  252. default:
  253. func = read_nothing;
  254. break;
  255. }
  256. port_readers[port] = func;
  257. }
  258. NOINLINE u32 io_ports_read(u32 a)
  259. {
  260. u32 d;
  261. a = (a>>1) & 0xf;
  262. switch (a) {
  263. case 0: d = Pico.m.hardware; break; // Hardware value (Version register)
  264. case 1: d = port_read(0); break;
  265. case 2: d = port_read(1); break;
  266. case 3: d = port_read(2); break;
  267. default: d = PicoMem.ioports[a]; break; // IO ports can be used as RAM
  268. }
  269. return d;
  270. }
  271. NOINLINE void io_ports_write(u32 a, u32 d)
  272. {
  273. a = (a>>1) & 0xf;
  274. // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
  275. if (1 <= a && a <= 2)
  276. {
  277. Pico.m.padDelay[a - 1] = 0;
  278. if (!(PicoMem.ioports[a] & 0x40) && (d & 0x40))
  279. Pico.m.padTHPhase[a - 1]++;
  280. }
  281. // certain IO ports can be used as RAM
  282. PicoMem.ioports[a] = d;
  283. }
  284. static int z80_cycles_from_68k(void)
  285. {
  286. int m68k_cnt = SekCyclesDone() - Pico.t.m68c_frame_start;
  287. return cycles_68k_to_z80(m68k_cnt);
  288. }
  289. void NOINLINE ctl_write_z80busreq(u32 d)
  290. {
  291. d&=1; d^=1;
  292. elprintf(EL_BUSREQ, "set_zrun: %i->%i [%u] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);
  293. if (d ^ Pico.m.z80Run)
  294. {
  295. if (d)
  296. {
  297. Pico.t.z80c_cnt = z80_cycles_from_68k() + 2;
  298. }
  299. else
  300. {
  301. if ((PicoIn.opt & POPT_EN_Z80) && !Pico.m.z80_reset) {
  302. pprof_start(m68k);
  303. PicoSyncZ80(SekCyclesDone());
  304. pprof_end_sub(m68k);
  305. }
  306. }
  307. Pico.m.z80Run = d;
  308. }
  309. }
  310. void NOINLINE ctl_write_z80reset(u32 d)
  311. {
  312. d&=1; d^=1;
  313. elprintf(EL_BUSREQ, "set_zreset: %i->%i [%u] @%06x", Pico.m.z80_reset, d, SekCyclesDone(), SekPc);
  314. if (d ^ Pico.m.z80_reset)
  315. {
  316. if (d)
  317. {
  318. if ((PicoIn.opt & POPT_EN_Z80) && Pico.m.z80Run) {
  319. pprof_start(m68k);
  320. PicoSyncZ80(SekCyclesDone());
  321. pprof_end_sub(m68k);
  322. }
  323. YM2612ResetChip();
  324. timers_reset();
  325. }
  326. else
  327. {
  328. Pico.t.z80c_cnt = z80_cycles_from_68k() + 2;
  329. z80_reset();
  330. }
  331. Pico.m.z80_reset = d;
  332. }
  333. }
  334. static int get_scanline(int is_from_z80);
  335. static void psg_write_68k(u32 d)
  336. {
  337. // look for volume write and update if needed
  338. if ((d & 0x90) == 0x90)
  339. PsndDoPSG(Pico.m.scanline);
  340. SN76496Write(d);
  341. }
  342. static void psg_write_z80(u32 d)
  343. {
  344. if ((d & 0x90) == 0x90) {
  345. int scanline = get_scanline(1);
  346. PsndDoPSG(scanline);
  347. }
  348. SN76496Write(d);
  349. }
  350. // -----------------------------------------------------------------
  351. #ifndef _ASM_MEMORY_C
  352. // cart (save) RAM area (usually 0x200000 - ...)
  353. static u32 PicoRead8_sram(u32 a)
  354. {
  355. u32 d;
  356. if (Pico.sv.start <= a && a <= Pico.sv.end && (Pico.m.sram_reg & SRR_MAPPED))
  357. {
  358. if (Pico.sv.flags & SRF_EEPROM) {
  359. d = EEPROM_read();
  360. if (!(a & 1))
  361. d >>= 8;
  362. d &= 0xff;
  363. } else
  364. d = *(u8 *)(Pico.sv.data - Pico.sv.start + a);
  365. elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);
  366. return d;
  367. }
  368. // XXX: this is banking unfriendly
  369. if (a < Pico.romsize)
  370. return Pico.rom[a ^ 1];
  371. return m68k_unmapped_read8(a);
  372. }
  373. static u32 PicoRead16_sram(u32 a)
  374. {
  375. u32 d;
  376. if (Pico.sv.start <= a && a <= Pico.sv.end && (Pico.m.sram_reg & SRR_MAPPED))
  377. {
  378. if (Pico.sv.flags & SRF_EEPROM)
  379. d = EEPROM_read();
  380. else {
  381. u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);
  382. d = pm[0] << 8;
  383. d |= pm[1];
  384. }
  385. elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);
  386. return d;
  387. }
  388. if (a < Pico.romsize)
  389. return *(u16 *)(Pico.rom + a);
  390. return m68k_unmapped_read16(a);
  391. }
  392. #endif // _ASM_MEMORY_C
  393. static void PicoWrite8_sram(u32 a, u32 d)
  394. {
  395. if (a > Pico.sv.end || a < Pico.sv.start || !(Pico.m.sram_reg & SRR_MAPPED)) {
  396. m68k_unmapped_write8(a, d);
  397. return;
  398. }
  399. elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d & 0xff, SekPc);
  400. if (Pico.sv.flags & SRF_EEPROM)
  401. {
  402. EEPROM_write8(a, d);
  403. }
  404. else {
  405. u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);
  406. if (*pm != (u8)d) {
  407. Pico.sv.changed = 1;
  408. *pm = (u8)d;
  409. }
  410. }
  411. }
  412. static void PicoWrite16_sram(u32 a, u32 d)
  413. {
  414. if (a > Pico.sv.end || a < Pico.sv.start || !(Pico.m.sram_reg & SRR_MAPPED)) {
  415. m68k_unmapped_write16(a, d);
  416. return;
  417. }
  418. elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d & 0xffff, SekPc);
  419. if (Pico.sv.flags & SRF_EEPROM)
  420. {
  421. EEPROM_write16(d);
  422. }
  423. else {
  424. u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);
  425. if (pm[0] != (u8)(d >> 8)) {
  426. Pico.sv.changed = 1;
  427. pm[0] = (u8)(d >> 8);
  428. }
  429. if (pm[1] != (u8)d) {
  430. Pico.sv.changed = 1;
  431. pm[1] = (u8)d;
  432. }
  433. }
  434. }
  435. // z80 area (0xa00000 - 0xa0ffff)
  436. // TODO: verify mirrors VDP and bank reg (bank area mirroring verified)
  437. static u32 PicoRead8_z80(u32 a)
  438. {
  439. u32 d = 0xff;
  440. if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {
  441. elprintf(EL_ANOMALY, "68k z80 read with no bus! [%06x] @ %06x", a, SekPc);
  442. // open bus. Pulled down if MegaCD2 is attached.
  443. return 0;
  444. }
  445. if ((a & 0x4000) == 0x0000)
  446. d = PicoMem.zram[a & 0x1fff];
  447. else if ((a & 0x6000) == 0x4000) // 0x4000-0x5fff
  448. d = ym2612_read_local_68k();
  449. else
  450. elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
  451. return d;
  452. }
  453. static u32 PicoRead16_z80(u32 a)
  454. {
  455. u32 d = PicoRead8_z80(a);
  456. return d | (d << 8);
  457. }
  458. static void PicoWrite8_z80(u32 a, u32 d)
  459. {
  460. if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {
  461. // verified on real hw
  462. elprintf(EL_ANOMALY, "68k z80 write with no bus or reset! [%06x] %02x @ %06x", a, d&0xff, SekPc);
  463. return;
  464. }
  465. if ((a & 0x4000) == 0x0000) { // z80 RAM
  466. PicoMem.zram[a & 0x1fff] = (u8)d;
  467. return;
  468. }
  469. if ((a & 0x6000) == 0x4000) { // FM Sound
  470. if (PicoIn.opt & POPT_EN_FM)
  471. ym2612_write_local(a & 3, d & 0xff, 0);
  472. return;
  473. }
  474. // TODO: probably other VDP access too? Maybe more mirrors?
  475. if ((a & 0x7ff9) == 0x7f11) { // PSG Sound
  476. psg_write_68k(d);
  477. return;
  478. }
  479. if ((a & 0x7f00) == 0x6000) // Z80 BANK register
  480. {
  481. Pico.m.z80_bank68k >>= 1;
  482. Pico.m.z80_bank68k |= d << 8;
  483. Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one
  484. elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k << 15);
  485. return;
  486. }
  487. elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @ %06x", a, d&0xff, SekPc);
  488. }
  489. static void PicoWrite16_z80(u32 a, u32 d)
  490. {
  491. // for RAM, only most significant byte is sent
  492. // TODO: verify remaining accesses
  493. PicoWrite8_z80(a, d >> 8);
  494. }
  495. #ifndef _ASM_MEMORY_C
  496. // IO/control area (0xa10000 - 0xa1ffff)
  497. u32 PicoRead8_io(u32 a)
  498. {
  499. u32 d;
  500. if ((a & 0xffe0) == 0x0000) { // I/O ports
  501. d = io_ports_read(a);
  502. goto end;
  503. }
  504. // faking open bus (MegaCD pulldowns don't work here curiously)
  505. d = Pico.m.rotate++;
  506. d ^= d << 6;
  507. if ((a & 0xfc00) == 0x1000) {
  508. // bit8 seems to be readable in this range
  509. if (!(a & 1))
  510. d &= ~0x01;
  511. if ((a & 0xff01) == 0x1100) { // z80 busreq (verified)
  512. d |= (Pico.m.z80Run | Pico.m.z80_reset) & 1;
  513. elprintf(EL_BUSREQ, "get_zrun: %02x [%u] @%06x", d, SekCyclesDone(), SekPc);
  514. }
  515. goto end;
  516. }
  517. d = PicoRead8_32x(a);
  518. end:
  519. return d;
  520. }
  521. u32 PicoRead16_io(u32 a)
  522. {
  523. u32 d;
  524. if ((a & 0xffe0) == 0x0000) { // I/O ports
  525. d = io_ports_read(a);
  526. d |= d << 8;
  527. goto end;
  528. }
  529. // faking open bus
  530. d = (Pico.m.rotate += 0x41);
  531. d ^= (d << 5) ^ (d << 8);
  532. // bit8 seems to be readable in this range
  533. if ((a & 0xfc00) == 0x1000) {
  534. d &= ~0x0100;
  535. if ((a & 0xff00) == 0x1100) { // z80 busreq
  536. d |= ((Pico.m.z80Run | Pico.m.z80_reset) & 1) << 8;
  537. elprintf(EL_BUSREQ, "get_zrun: %04x [%u] @%06x", d, SekCyclesDone(), SekPc);
  538. }
  539. goto end;
  540. }
  541. d = PicoRead16_32x(a);
  542. end:
  543. return d;
  544. }
  545. void PicoWrite8_io(u32 a, u32 d)
  546. {
  547. if ((a & 0xffe1) == 0x0001) { // I/O ports (verified: only LSB!)
  548. io_ports_write(a, d);
  549. return;
  550. }
  551. if ((a & 0xff01) == 0x1100) { // z80 busreq
  552. ctl_write_z80busreq(d);
  553. return;
  554. }
  555. if ((a & 0xff01) == 0x1200) { // z80 reset
  556. ctl_write_z80reset(d);
  557. return;
  558. }
  559. if (a == 0xa130f1) { // sram access register
  560. elprintf(EL_SRAMIO, "sram reg=%02x", d);
  561. Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);
  562. Pico.m.sram_reg |= (u8)(d & 3);
  563. return;
  564. }
  565. PicoWrite8_32x(a, d);
  566. }
  567. void PicoWrite16_io(u32 a, u32 d)
  568. {
  569. if ((a & 0xffe0) == 0x0000) { // I/O ports (verified: only LSB!)
  570. io_ports_write(a, d);
  571. return;
  572. }
  573. if ((a & 0xff00) == 0x1100) { // z80 busreq
  574. ctl_write_z80busreq(d >> 8);
  575. return;
  576. }
  577. if ((a & 0xff00) == 0x1200) { // z80 reset
  578. ctl_write_z80reset(d >> 8);
  579. return;
  580. }
  581. if (a == 0xa130f0) { // sram access register
  582. elprintf(EL_SRAMIO, "sram reg=%02x", d);
  583. Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);
  584. Pico.m.sram_reg |= (u8)(d & 3);
  585. return;
  586. }
  587. PicoWrite16_32x(a, d);
  588. }
  589. #endif // _ASM_MEMORY_C
  590. // VDP area (0xc00000 - 0xdfffff)
  591. // TODO: verify if lower byte goes to PSG on word writes
  592. u32 PicoRead8_vdp(u32 a)
  593. {
  594. if ((a & 0x00f0) == 0x0000) {
  595. switch (a & 0x0d)
  596. {
  597. case 0x00: return PicoVideoRead8DataH();
  598. case 0x01: return PicoVideoRead8DataL();
  599. case 0x04: return PicoVideoRead8CtlH();
  600. case 0x05: return PicoVideoRead8CtlL();
  601. case 0x08:
  602. case 0x0c: return PicoVideoRead8HV_H();
  603. case 0x09:
  604. case 0x0d: return PicoVideoRead8HV_L();
  605. }
  606. }
  607. elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
  608. return 0;
  609. }
  610. static u32 PicoRead16_vdp(u32 a)
  611. {
  612. if ((a & 0x00e0) == 0x0000)
  613. return PicoVideoRead(a);
  614. elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
  615. return 0;
  616. }
  617. static void PicoWrite8_vdp(u32 a, u32 d)
  618. {
  619. if ((a & 0x00f9) == 0x0011) { // PSG Sound
  620. psg_write_68k(d);
  621. return;
  622. }
  623. if ((a & 0x00e0) == 0x0000) {
  624. d &= 0xff;
  625. PicoVideoWrite(a, d | (d << 8));
  626. return;
  627. }
  628. elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @%06x", a, d & 0xff, SekPc);
  629. }
  630. static void PicoWrite16_vdp(u32 a, u32 d)
  631. {
  632. if ((a & 0x00f9) == 0x0010) { // PSG Sound
  633. psg_write_68k(d);
  634. return;
  635. }
  636. if ((a & 0x00e0) == 0x0000) {
  637. PicoVideoWrite(a, d);
  638. return;
  639. }
  640. elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  641. }
  642. // -----------------------------------------------------------------
  643. #ifdef EMU_M68K
  644. static void m68k_mem_setup(void);
  645. #endif
  646. PICO_INTERNAL void PicoMemSetup(void)
  647. {
  648. int mask, rs, sstart, a;
  649. // setup the memory map
  650. cpu68k_map_set(m68k_read8_map, 0x000000, 0xffffff, m68k_unmapped_read8, 1);
  651. cpu68k_map_set(m68k_read16_map, 0x000000, 0xffffff, m68k_unmapped_read16, 1);
  652. cpu68k_map_set(m68k_write8_map, 0x000000, 0xffffff, m68k_unmapped_write8, 1);
  653. cpu68k_map_set(m68k_write16_map, 0x000000, 0xffffff, m68k_unmapped_write16, 1);
  654. // ROM
  655. // align to bank size. We know ROM loader allocated enough for this
  656. mask = (1 << M68K_MEM_SHIFT) - 1;
  657. rs = (Pico.romsize + mask) & ~mask;
  658. cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico.rom, 0);
  659. cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico.rom, 0);
  660. // Common case of on-cart (save) RAM, usually at 0x200000-...
  661. if ((Pico.sv.flags & SRF_ENABLED) && Pico.sv.data != NULL) {
  662. sstart = Pico.sv.start;
  663. rs = Pico.sv.end - sstart;
  664. rs = (rs + mask) & ~mask;
  665. if (sstart + rs >= 0x1000000)
  666. rs = 0x1000000 - sstart;
  667. cpu68k_map_set(m68k_read8_map, sstart, sstart + rs - 1, PicoRead8_sram, 1);
  668. cpu68k_map_set(m68k_read16_map, sstart, sstart + rs - 1, PicoRead16_sram, 1);
  669. cpu68k_map_set(m68k_write8_map, sstart, sstart + rs - 1, PicoWrite8_sram, 1);
  670. cpu68k_map_set(m68k_write16_map, sstart, sstart + rs - 1, PicoWrite16_sram, 1);
  671. }
  672. // Z80 region
  673. cpu68k_map_set(m68k_read8_map, 0xa00000, 0xa0ffff, PicoRead8_z80, 1);
  674. cpu68k_map_set(m68k_read16_map, 0xa00000, 0xa0ffff, PicoRead16_z80, 1);
  675. cpu68k_map_set(m68k_write8_map, 0xa00000, 0xa0ffff, PicoWrite8_z80, 1);
  676. cpu68k_map_set(m68k_write16_map, 0xa00000, 0xa0ffff, PicoWrite16_z80, 1);
  677. // IO/control region
  678. cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_io, 1);
  679. cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_io, 1);
  680. cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_io, 1);
  681. cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_io, 1);
  682. // VDP region
  683. for (a = 0xc00000; a < 0xe00000; a += 0x010000) {
  684. if ((a & 0xe700e0) != 0xc00000)
  685. continue;
  686. cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoRead8_vdp, 1);
  687. cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoRead16_vdp, 1);
  688. cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoWrite8_vdp, 1);
  689. cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoWrite16_vdp, 1);
  690. }
  691. // RAM and it's mirrors
  692. for (a = 0xe00000; a < 0x1000000; a += 0x010000) {
  693. cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoMem.ram, 0);
  694. cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoMem.ram, 0);
  695. cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoMem.ram, 0);
  696. cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoMem.ram, 0);
  697. }
  698. // Setup memory callbacks:
  699. #ifdef EMU_C68K
  700. PicoCpuCM68k.read8 = (void *)m68k_read8_map;
  701. PicoCpuCM68k.read16 = (void *)m68k_read16_map;
  702. PicoCpuCM68k.read32 = (void *)m68k_read16_map;
  703. PicoCpuCM68k.write8 = (void *)m68k_write8_map;
  704. PicoCpuCM68k.write16 = (void *)m68k_write16_map;
  705. PicoCpuCM68k.write32 = (void *)m68k_write16_map;
  706. PicoCpuCM68k.checkpc = NULL; /* unused */
  707. PicoCpuCM68k.fetch8 = NULL;
  708. PicoCpuCM68k.fetch16 = NULL;
  709. PicoCpuCM68k.fetch32 = NULL;
  710. #endif
  711. #ifdef EMU_F68K
  712. PicoCpuFM68k.read_byte = m68k_read8;
  713. PicoCpuFM68k.read_word = m68k_read16;
  714. PicoCpuFM68k.read_long = m68k_read32;
  715. PicoCpuFM68k.write_byte = m68k_write8;
  716. PicoCpuFM68k.write_word = m68k_write16;
  717. PicoCpuFM68k.write_long = m68k_write32;
  718. // setup FAME fetchmap
  719. {
  720. int i;
  721. // by default, point everything to first 64k of ROM
  722. for (i = 0; i < M68K_FETCHBANK1 * 0xe0 / 0x100; i++)
  723. PicoCpuFM68k.Fetch[i] = (uptr)Pico.rom - (i<<(24-FAMEC_FETCHBITS));
  724. // now real ROM
  725. for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)
  726. PicoCpuFM68k.Fetch[i] = (uptr)Pico.rom;
  727. // RAM already set
  728. }
  729. #endif
  730. #ifdef EMU_M68K
  731. m68k_mem_setup();
  732. #endif
  733. z80_mem_setup();
  734. }
  735. #ifdef EMU_M68K
  736. unsigned int (*pm68k_read_memory_8) (unsigned int address) = NULL;
  737. unsigned int (*pm68k_read_memory_16)(unsigned int address) = NULL;
  738. unsigned int (*pm68k_read_memory_32)(unsigned int address) = NULL;
  739. void (*pm68k_write_memory_8) (unsigned int address, unsigned char value) = NULL;
  740. void (*pm68k_write_memory_16)(unsigned int address, unsigned short value) = NULL;
  741. void (*pm68k_write_memory_32)(unsigned int address, unsigned int value) = NULL;
  742. /* it appears that Musashi doesn't always mask the unused bits */
  743. unsigned int m68k_read_memory_8 (unsigned int address) { return pm68k_read_memory_8 (address) & 0xff; }
  744. unsigned int m68k_read_memory_16(unsigned int address) { return pm68k_read_memory_16(address) & 0xffff; }
  745. unsigned int m68k_read_memory_32(unsigned int address) { return pm68k_read_memory_32(address); }
  746. void m68k_write_memory_8 (unsigned int address, unsigned int value) { pm68k_write_memory_8 (address, (u8)value); }
  747. void m68k_write_memory_16(unsigned int address, unsigned int value) { pm68k_write_memory_16(address,(u16)value); }
  748. void m68k_write_memory_32(unsigned int address, unsigned int value) { pm68k_write_memory_32(address, value); }
  749. static void m68k_mem_setup(void)
  750. {
  751. pm68k_read_memory_8 = m68k_read8;
  752. pm68k_read_memory_16 = m68k_read16;
  753. pm68k_read_memory_32 = m68k_read32;
  754. pm68k_write_memory_8 = m68k_write8;
  755. pm68k_write_memory_16 = m68k_write16;
  756. pm68k_write_memory_32 = m68k_write32;
  757. }
  758. #endif // EMU_M68K
  759. // -----------------------------------------------------------------
  760. static int get_scanline(int is_from_z80)
  761. {
  762. if (is_from_z80) {
  763. int mclk_z80 = (z80_cyclesLeft<0 ? Pico.t.z80c_aim : z80_cyclesDone()) * 15;
  764. int mclk_line = Pico.t.z80_scanline * 488 * 7;
  765. while (mclk_z80 - mclk_line >= 488 * 7)
  766. Pico.t.z80_scanline++, mclk_line += 488 * 7;
  767. return Pico.t.z80_scanline;
  768. }
  769. return Pico.m.scanline;
  770. }
  771. /* probably should not be in this file, but it's near related code here */
  772. void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new)
  773. {
  774. int xcycles = z80_cycles << 8;
  775. /* check for overflows */
  776. if ((mode_old & 4) && xcycles >= Pico.t.timer_a_next_oflow)
  777. ym2612.OPN.ST.status |= 1;
  778. if ((mode_old & 8) && xcycles >= Pico.t.timer_b_next_oflow)
  779. ym2612.OPN.ST.status |= 2;
  780. /* update timer a */
  781. if (mode_old & 1)
  782. while (xcycles > Pico.t.timer_a_next_oflow)
  783. Pico.t.timer_a_next_oflow += Pico.t.timer_a_step;
  784. if ((mode_old ^ mode_new) & 1) // turning on/off
  785. {
  786. if (mode_old & 1)
  787. Pico.t.timer_a_next_oflow = TIMER_NO_OFLOW;
  788. else
  789. Pico.t.timer_a_next_oflow = xcycles + Pico.t.timer_a_step;
  790. }
  791. if (mode_new & 1)
  792. elprintf(EL_YMTIMER, "timer a upd to %i @ %i", Pico.t.timer_a_next_oflow>>8, z80_cycles);
  793. /* update timer b */
  794. if (mode_old & 2)
  795. while (xcycles > Pico.t.timer_b_next_oflow)
  796. Pico.t.timer_b_next_oflow += Pico.t.timer_b_step;
  797. if ((mode_old ^ mode_new) & 2)
  798. {
  799. if (mode_old & 2)
  800. Pico.t.timer_b_next_oflow = TIMER_NO_OFLOW;
  801. else
  802. Pico.t.timer_b_next_oflow = xcycles + Pico.t.timer_b_step;
  803. }
  804. if (mode_new & 2)
  805. elprintf(EL_YMTIMER, "timer b upd to %i @ %i", Pico.t.timer_b_next_oflow>>8, z80_cycles);
  806. }
  807. // ym2612 DAC and timer I/O handlers for z80
  808. static int ym2612_write_local(u32 a, u32 d, int is_from_z80)
  809. {
  810. int addr;
  811. a &= 3;
  812. if (a == 1 && ym2612.OPN.ST.address == 0x2a) /* DAC data */
  813. {
  814. int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
  815. //elprintf(EL_STATUS, "%03i dac w %08x z80 %i", cycles, d, is_from_z80);
  816. if (ym2612.dacen)
  817. PsndDoDAC(cycles);
  818. ym2612.dacout = ((int)d - 0x80) << 6;
  819. return 0;
  820. }
  821. switch (a)
  822. {
  823. case 0: /* address port 0 */
  824. ym2612.OPN.ST.address = d;
  825. ym2612.addr_A1 = 0;
  826. #ifdef __GP2X__
  827. if (PicoIn.opt & POPT_EXT_FM) YM2612Write_940(a, d, -1);
  828. #endif
  829. return 0;
  830. case 1: /* data port 0 */
  831. if (ym2612.addr_A1 != 0)
  832. return 0;
  833. addr = ym2612.OPN.ST.address;
  834. ym2612.REGS[addr] = d;
  835. switch (addr)
  836. {
  837. case 0x24: // timer A High 8
  838. case 0x25: { // timer A Low 2
  839. int TAnew = (addr == 0x24) ? ((ym2612.OPN.ST.TA & 0x03)|(((int)d)<<2))
  840. : ((ym2612.OPN.ST.TA & 0x3fc)|(d&3));
  841. if (ym2612.OPN.ST.TA != TAnew)
  842. {
  843. //elprintf(EL_STATUS, "timer a set %i", TAnew);
  844. ym2612.OPN.ST.TA = TAnew;
  845. //ym2612.OPN.ST.TAC = (1024-TAnew)*18;
  846. //ym2612.OPN.ST.TAT = 0;
  847. Pico.t.timer_a_step = TIMER_A_TICK_ZCYCLES * (1024 - TAnew);
  848. if (ym2612.OPN.ST.mode & 1) {
  849. // this is not right, should really be done on overflow only
  850. int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
  851. Pico.t.timer_a_next_oflow = (cycles << 8) + Pico.t.timer_a_step;
  852. }
  853. elprintf(EL_YMTIMER, "timer a set to %i, %i", 1024 - TAnew, Pico.t.timer_a_next_oflow>>8);
  854. }
  855. return 0;
  856. }
  857. case 0x26: // timer B
  858. if (ym2612.OPN.ST.TB != d) {
  859. //elprintf(EL_STATUS, "timer b set %i", d);
  860. ym2612.OPN.ST.TB = d;
  861. //ym2612.OPN.ST.TBC = (256-d) * 288;
  862. //ym2612.OPN.ST.TBT = 0;
  863. Pico.t.timer_b_step = TIMER_B_TICK_ZCYCLES * (256 - d); // 262800
  864. if (ym2612.OPN.ST.mode & 2) {
  865. int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
  866. Pico.t.timer_b_next_oflow = (cycles << 8) + Pico.t.timer_b_step;
  867. }
  868. elprintf(EL_YMTIMER, "timer b set to %i, %i", 256 - d, Pico.t.timer_b_next_oflow>>8);
  869. }
  870. return 0;
  871. case 0x27: { /* mode, timer control */
  872. int old_mode = ym2612.OPN.ST.mode;
  873. int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
  874. ym2612.OPN.ST.mode = d;
  875. elprintf(EL_YMTIMER, "st mode %02x", d);
  876. ym2612_sync_timers(cycles, old_mode, d);
  877. /* reset Timer a flag */
  878. if (d & 0x10)
  879. ym2612.OPN.ST.status &= ~1;
  880. /* reset Timer b flag */
  881. if (d & 0x20)
  882. ym2612.OPN.ST.status &= ~2;
  883. if ((d ^ old_mode) & 0xc0) {
  884. #ifdef __GP2X__
  885. if (PicoIn.opt & POPT_EXT_FM) return YM2612Write_940(a, d, get_scanline(is_from_z80));
  886. #endif
  887. PsndDoFM(cycles);
  888. return 1;
  889. }
  890. return 0;
  891. }
  892. case 0x2b: { /* DAC Sel (YM2612) */
  893. ym2612.dacen = d & 0x80;
  894. #ifdef __GP2X__
  895. if (PicoIn.opt & POPT_EXT_FM) YM2612Write_940(a, d, get_scanline(is_from_z80));
  896. #endif
  897. return 0;
  898. }
  899. }
  900. break;
  901. case 2: /* address port 1 */
  902. ym2612.OPN.ST.address = d;
  903. ym2612.addr_A1 = 1;
  904. #ifdef __GP2X__
  905. if (PicoIn.opt & POPT_EXT_FM) YM2612Write_940(a, d, -1);
  906. #endif
  907. return 0;
  908. case 3: /* data port 1 */
  909. if (ym2612.addr_A1 != 1)
  910. return 0;
  911. addr = ym2612.OPN.ST.address | 0x100;
  912. ym2612.REGS[addr] = d;
  913. break;
  914. }
  915. #ifdef __GP2X__
  916. if (PicoIn.opt & POPT_EXT_FM)
  917. return YM2612Write_940(a, d, get_scanline(is_from_z80));
  918. #endif
  919. PsndDoFM(is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k());
  920. return YM2612Write_(a, d);
  921. }
  922. #define ym2612_read_local() \
  923. if (xcycles >= Pico.t.timer_a_next_oflow) \
  924. ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 1; \
  925. if (xcycles >= Pico.t.timer_b_next_oflow) \
  926. ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 2
  927. static u32 ym2612_read_local_z80(void)
  928. {
  929. int xcycles = z80_cyclesDone() << 8;
  930. ym2612_read_local();
  931. elprintf(EL_YMTIMER, "timer z80 read %i, sched %i, %i @ %i|%i",
  932. ym2612.OPN.ST.status, Pico.t.timer_a_next_oflow >> 8,
  933. Pico.t.timer_b_next_oflow >> 8, xcycles >> 8, (xcycles >> 8) / 228);
  934. return ym2612.OPN.ST.status;
  935. }
  936. static u32 ym2612_read_local_68k(void)
  937. {
  938. int xcycles = z80_cycles_from_68k() << 8;
  939. ym2612_read_local();
  940. elprintf(EL_YMTIMER, "timer 68k read %i, sched %i, %i @ %i|%i",
  941. ym2612.OPN.ST.status, Pico.t.timer_a_next_oflow >> 8,
  942. Pico.t.timer_b_next_oflow >> 8, xcycles >> 8, (xcycles >> 8) / 228);
  943. return ym2612.OPN.ST.status;
  944. }
  945. void ym2612_pack_state(void)
  946. {
  947. // timers are saved as tick counts, in 16.16 int format
  948. int tac, tat = 0, tbc, tbt = 0;
  949. tac = 1024 - ym2612.OPN.ST.TA;
  950. tbc = 256 - ym2612.OPN.ST.TB;
  951. if (Pico.t.timer_a_next_oflow != TIMER_NO_OFLOW)
  952. tat = (int)((double)(Pico.t.timer_a_step - Pico.t.timer_a_next_oflow)
  953. / (double)Pico.t.timer_a_step * tac * 65536);
  954. if (Pico.t.timer_b_next_oflow != TIMER_NO_OFLOW)
  955. tbt = (int)((double)(Pico.t.timer_b_step - Pico.t.timer_b_next_oflow)
  956. / (double)Pico.t.timer_b_step * tbc * 65536);
  957. elprintf(EL_YMTIMER, "save: timer a %i/%i", tat >> 16, tac);
  958. elprintf(EL_YMTIMER, "save: timer b %i/%i", tbt >> 16, tbc);
  959. #ifdef __GP2X__
  960. if (PicoIn.opt & POPT_EXT_FM)
  961. YM2612PicoStateSave2_940(tat, tbt);
  962. else
  963. #endif
  964. YM2612PicoStateSave2(tat, tbt);
  965. }
  966. void ym2612_unpack_state(void)
  967. {
  968. int i, ret, tac, tat, tbc, tbt;
  969. YM2612PicoStateLoad();
  970. // feed all the registers and update internal state
  971. for (i = 0x20; i < 0xA0; i++) {
  972. ym2612_write_local(0, i, 0);
  973. ym2612_write_local(1, ym2612.REGS[i], 0);
  974. }
  975. for (i = 0x30; i < 0xA0; i++) {
  976. ym2612_write_local(2, i, 0);
  977. ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
  978. }
  979. for (i = 0xAF; i >= 0xA0; i--) { // must apply backwards
  980. ym2612_write_local(2, i, 0);
  981. ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
  982. ym2612_write_local(0, i, 0);
  983. ym2612_write_local(1, ym2612.REGS[i], 0);
  984. }
  985. for (i = 0xB0; i < 0xB8; i++) {
  986. ym2612_write_local(0, i, 0);
  987. ym2612_write_local(1, ym2612.REGS[i], 0);
  988. ym2612_write_local(2, i, 0);
  989. ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
  990. }
  991. #ifdef __GP2X__
  992. if (PicoIn.opt & POPT_EXT_FM)
  993. ret = YM2612PicoStateLoad2_940(&tat, &tbt);
  994. else
  995. #endif
  996. ret = YM2612PicoStateLoad2(&tat, &tbt);
  997. if (ret != 0) {
  998. elprintf(EL_STATUS, "old ym2612 state");
  999. return; // no saved timers
  1000. }
  1001. tac = (1024 - ym2612.OPN.ST.TA) << 16;
  1002. tbc = (256 - ym2612.OPN.ST.TB) << 16;
  1003. if (ym2612.OPN.ST.mode & 1)
  1004. Pico.t.timer_a_next_oflow = (int)((double)(tac - tat) / (double)tac * Pico.t.timer_a_step);
  1005. else
  1006. Pico.t.timer_a_next_oflow = TIMER_NO_OFLOW;
  1007. if (ym2612.OPN.ST.mode & 2)
  1008. Pico.t.timer_b_next_oflow = (int)((double)(tbc - tbt) / (double)tbc * Pico.t.timer_b_step);
  1009. else
  1010. Pico.t.timer_b_next_oflow = TIMER_NO_OFLOW;
  1011. elprintf(EL_YMTIMER, "load: %i/%i, timer_a_next_oflow %i", tat>>16, tac>>16, Pico.t.timer_a_next_oflow >> 8);
  1012. elprintf(EL_YMTIMER, "load: %i/%i, timer_b_next_oflow %i", tbt>>16, tbc>>16, Pico.t.timer_b_next_oflow >> 8);
  1013. }
  1014. #if defined(NO_32X) && defined(_ASM_MEMORY_C)
  1015. // referenced by asm code
  1016. u32 PicoRead8_32x(u32 a) { return 0; }
  1017. u32 PicoRead16_32x(u32 a) { return 0; }
  1018. void PicoWrite8_32x(u32 a, u32 d) {}
  1019. void PicoWrite16_32x(u32 a, u32 d) {}
  1020. #endif
  1021. // -----------------------------------------------------------------
  1022. // z80 memhandlers
  1023. static unsigned char z80_md_vdp_read(unsigned short a)
  1024. {
  1025. z80_subCLeft(2);
  1026. if ((a & 0x00f0) == 0x0000) {
  1027. switch (a & 0x0d)
  1028. {
  1029. case 0x00: return PicoVideoRead8DataH();
  1030. case 0x01: return PicoVideoRead8DataL();
  1031. case 0x04: return PicoVideoRead8CtlH();
  1032. case 0x05: return PicoVideoRead8CtlL();
  1033. case 0x08:
  1034. case 0x0c: return get_scanline(1); // FIXME: make it proper
  1035. case 0x09:
  1036. case 0x0d: return Pico.m.rotate++;
  1037. }
  1038. }
  1039. elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, 0xff);
  1040. return 0xff;
  1041. }
  1042. static unsigned char z80_md_bank_read(unsigned short a)
  1043. {
  1044. unsigned int addr68k;
  1045. unsigned char ret;
  1046. z80_subCLeft(3);
  1047. addr68k = Pico.m.z80_bank68k << 15;
  1048. addr68k |= a & 0x7fff;
  1049. ret = m68k_read8(addr68k);
  1050. elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);
  1051. return ret;
  1052. }
  1053. static void z80_md_ym2612_write(unsigned int a, unsigned char data)
  1054. {
  1055. if (PicoIn.opt & POPT_EN_FM)
  1056. ym2612_write_local(a, data, 1);
  1057. }
  1058. static void z80_md_vdp_br_write(unsigned int a, unsigned char data)
  1059. {
  1060. if ((a&0xfff9) == 0x7f11) // 7f11 7f13 7f15 7f17
  1061. {
  1062. psg_write_z80(data);
  1063. return;
  1064. }
  1065. // at least VDP data writes hang my machine
  1066. if ((a>>8) == 0x60)
  1067. {
  1068. Pico.m.z80_bank68k >>= 1;
  1069. Pico.m.z80_bank68k |= data << 8;
  1070. Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one
  1071. return;
  1072. }
  1073. elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);
  1074. }
  1075. static void z80_md_bank_write(unsigned int a, unsigned char data)
  1076. {
  1077. unsigned int addr68k;
  1078. addr68k = Pico.m.z80_bank68k << 15;
  1079. addr68k += a & 0x7fff;
  1080. elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);
  1081. m68k_write8(addr68k, data);
  1082. }
  1083. // -----------------------------------------------------------------
  1084. static unsigned char z80_md_in(unsigned short p)
  1085. {
  1086. elprintf(EL_ANOMALY, "Z80 port %04x read", p);
  1087. return 0xff;
  1088. }
  1089. static void z80_md_out(unsigned short p, unsigned char d)
  1090. {
  1091. elprintf(EL_ANOMALY, "Z80 port %04x write %02x", p, d);
  1092. }
  1093. static void z80_mem_setup(void)
  1094. {
  1095. z80_map_set(z80_read_map, 0x0000, 0x1fff, PicoMem.zram, 0);
  1096. z80_map_set(z80_read_map, 0x2000, 0x3fff, PicoMem.zram, 0);
  1097. z80_map_set(z80_read_map, 0x4000, 0x5fff, ym2612_read_local_z80, 1);
  1098. z80_map_set(z80_read_map, 0x6000, 0x7fff, z80_md_vdp_read, 1);
  1099. z80_map_set(z80_read_map, 0x8000, 0xffff, z80_md_bank_read, 1);
  1100. z80_map_set(z80_write_map, 0x0000, 0x1fff, PicoMem.zram, 0);
  1101. z80_map_set(z80_write_map, 0x2000, 0x3fff, PicoMem.zram, 0);
  1102. z80_map_set(z80_write_map, 0x4000, 0x5fff, z80_md_ym2612_write, 1);
  1103. z80_map_set(z80_write_map, 0x6000, 0x7fff, z80_md_vdp_br_write, 1);
  1104. z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write, 1);
  1105. #ifdef _USE_DRZ80
  1106. drZ80.z80_in = z80_md_in;
  1107. drZ80.z80_out = z80_md_out;
  1108. #endif
  1109. #ifdef _USE_CZ80
  1110. Cz80_Set_Fetch(&CZ80, 0x0000, 0x1fff, (FPTR)PicoMem.zram); // main RAM
  1111. Cz80_Set_Fetch(&CZ80, 0x2000, 0x3fff, (FPTR)PicoMem.zram); // mirror
  1112. Cz80_Set_INPort(&CZ80, z80_md_in);
  1113. Cz80_Set_OUTPort(&CZ80, z80_md_out);
  1114. #endif
  1115. }
  1116. // vim:shiftwidth=2:ts=2:expandtab