memory.c 37 KB

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  1. /*
  2. * memory handling
  3. * (c) Copyright Dave, 2004
  4. * (C) notaz, 2006-2010
  5. *
  6. * This work is licensed under the terms of MAME license.
  7. * See COPYING file in the top-level directory.
  8. */
  9. #include "pico_int.h"
  10. #include "memory.h"
  11. #include "sound/ym2612.h"
  12. #include "sound/sn76496.h"
  13. extern unsigned int lastSSRamWrite; // used by serial eeprom code
  14. uptr m68k_read8_map [0x1000000 >> M68K_MEM_SHIFT];
  15. uptr m68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];
  16. uptr m68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];
  17. uptr m68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];
  18. static void xmap_set(uptr *map, int shift, int start_addr, int end_addr,
  19. const void *func_or_mh, int is_func)
  20. {
  21. #ifdef __clang__
  22. // workaround bug (segfault) in
  23. // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)
  24. volatile
  25. #endif
  26. uptr addr = (uptr)func_or_mh;
  27. int mask = (1 << shift) - 1;
  28. int i;
  29. if ((start_addr & mask) != 0 || (end_addr & mask) != mask) {
  30. elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: tried to map bad range: %06x-%06x",
  31. start_addr, end_addr);
  32. return;
  33. }
  34. if (addr & 1) {
  35. elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: ptr is not aligned: %08lx", addr);
  36. return;
  37. }
  38. if (!is_func)
  39. addr -= start_addr;
  40. for (i = start_addr >> shift; i <= end_addr >> shift; i++) {
  41. map[i] = addr >> 1;
  42. if (is_func)
  43. map[i] |= MAP_FLAG;
  44. }
  45. }
  46. void z80_map_set(uptr *map, int start_addr, int end_addr,
  47. const void *func_or_mh, int is_func)
  48. {
  49. xmap_set(map, Z80_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);
  50. }
  51. void cpu68k_map_set(uptr *map, int start_addr, int end_addr,
  52. const void *func_or_mh, int is_func)
  53. {
  54. xmap_set(map, M68K_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);
  55. #ifdef EMU_F68K
  56. // setup FAME fetchmap
  57. if (!is_func)
  58. {
  59. int shiftout = 24 - FAMEC_FETCHBITS;
  60. int i = start_addr >> shiftout;
  61. uptr base = (uptr)func_or_mh - (i << shiftout);
  62. for (; i <= (end_addr >> shiftout); i++)
  63. PicoCpuFM68k.Fetch[i] = base;
  64. }
  65. #endif
  66. }
  67. // more specialized/optimized function (does same as above)
  68. void cpu68k_map_all_ram(int start_addr, int end_addr, void *ptr, int is_sub)
  69. {
  70. uptr *r8map, *r16map, *w8map, *w16map;
  71. uptr addr = (uptr)ptr;
  72. int shift = M68K_MEM_SHIFT;
  73. int i;
  74. if (!is_sub) {
  75. r8map = m68k_read8_map;
  76. r16map = m68k_read16_map;
  77. w8map = m68k_write8_map;
  78. w16map = m68k_write16_map;
  79. } else {
  80. r8map = s68k_read8_map;
  81. r16map = s68k_read16_map;
  82. w8map = s68k_write8_map;
  83. w16map = s68k_write16_map;
  84. }
  85. addr -= start_addr;
  86. addr >>= 1;
  87. for (i = start_addr >> shift; i <= end_addr >> shift; i++)
  88. r8map[i] = r16map[i] = w8map[i] = w16map[i] = addr;
  89. #ifdef EMU_F68K
  90. // setup FAME fetchmap
  91. {
  92. M68K_CONTEXT *ctx = is_sub ? &PicoCpuFS68k : &PicoCpuFM68k;
  93. int shiftout = 24 - FAMEC_FETCHBITS;
  94. i = start_addr >> shiftout;
  95. addr = (uptr)ptr - (i << shiftout);
  96. for (; i <= (end_addr >> shiftout); i++)
  97. ctx->Fetch[i] = addr;
  98. }
  99. #endif
  100. }
  101. static u32 m68k_unmapped_read8(u32 a)
  102. {
  103. elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
  104. return 0; // assume pulldown, as if MegaCD2 was attached
  105. }
  106. static u32 m68k_unmapped_read16(u32 a)
  107. {
  108. elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
  109. return 0;
  110. }
  111. static void m68k_unmapped_write8(u32 a, u32 d)
  112. {
  113. elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  114. }
  115. static void m68k_unmapped_write16(u32 a, u32 d)
  116. {
  117. elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  118. }
  119. void m68k_map_unmap(int start_addr, int end_addr)
  120. {
  121. #ifdef __clang__
  122. // workaround bug (segfault) in
  123. // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)
  124. volatile
  125. #endif
  126. uptr addr;
  127. int shift = M68K_MEM_SHIFT;
  128. int i;
  129. addr = (uptr)m68k_unmapped_read8;
  130. for (i = start_addr >> shift; i <= end_addr >> shift; i++)
  131. m68k_read8_map[i] = (addr >> 1) | MAP_FLAG;
  132. addr = (uptr)m68k_unmapped_read16;
  133. for (i = start_addr >> shift; i <= end_addr >> shift; i++)
  134. m68k_read16_map[i] = (addr >> 1) | MAP_FLAG;
  135. addr = (uptr)m68k_unmapped_write8;
  136. for (i = start_addr >> shift; i <= end_addr >> shift; i++)
  137. m68k_write8_map[i] = (addr >> 1) | MAP_FLAG;
  138. addr = (uptr)m68k_unmapped_write16;
  139. for (i = start_addr >> shift; i <= end_addr >> shift; i++)
  140. m68k_write16_map[i] = (addr >> 1) | MAP_FLAG;
  141. }
  142. #ifndef _ASM_MEMORY_C
  143. MAKE_68K_READ8(m68k_read8, m68k_read8_map)
  144. MAKE_68K_READ16(m68k_read16, m68k_read16_map)
  145. MAKE_68K_READ32(m68k_read32, m68k_read16_map)
  146. MAKE_68K_WRITE8(m68k_write8, m68k_write8_map)
  147. MAKE_68K_WRITE16(m68k_write16, m68k_write16_map)
  148. MAKE_68K_WRITE32(m68k_write32, m68k_write16_map)
  149. #endif
  150. // -----------------------------------------------------------------
  151. static u32 ym2612_read_local_68k(void);
  152. static int ym2612_write_local(u32 a, u32 d, int is_from_z80);
  153. static void z80_mem_setup(void);
  154. #ifdef _ASM_MEMORY_C
  155. u32 PicoRead8_sram(u32 a);
  156. u32 PicoRead16_sram(u32 a);
  157. #endif
  158. #ifdef EMU_CORE_DEBUG
  159. u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};
  160. int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0;
  161. extern unsigned int ppop;
  162. #endif
  163. #ifdef IO_STATS
  164. void log_io(unsigned int addr, int bits, int rw);
  165. #elif defined(_MSC_VER)
  166. #define log_io
  167. #else
  168. #define log_io(...)
  169. #endif
  170. #if defined(EMU_C68K)
  171. void cyclone_crashed(u32 pc, struct Cyclone *context)
  172. {
  173. elprintf(EL_STATUS|EL_ANOMALY, "%c68k crash detected @ %06x",
  174. context == &PicoCpuCM68k ? 'm' : 's', pc);
  175. context->membase = (u32)Pico.rom;
  176. context->pc = (u32)Pico.rom + Pico.romsize;
  177. }
  178. #endif
  179. // -----------------------------------------------------------------
  180. // memmap helpers
  181. static u32 read_pad_3btn(int i, u32 out_bits)
  182. {
  183. u32 pad = ~PicoIn.padInt[i]; // Get inverse of pad MXYZ SACB RLDU
  184. u32 value;
  185. if (out_bits & 0x40) // TH
  186. value = pad & 0x3f; // ?1CB RLDU
  187. else
  188. value = ((pad & 0xc0) >> 2) | (pad & 3); // ?0SA 00DU
  189. value |= out_bits & 0x40;
  190. return value;
  191. }
  192. static u32 read_pad_6btn(int i, u32 out_bits)
  193. {
  194. u32 pad = ~PicoIn.padInt[i]; // Get inverse of pad MXYZ SACB RLDU
  195. int phase = Pico.m.padTHPhase[i];
  196. u32 value;
  197. if (phase == 2 && !(out_bits & 0x40)) {
  198. value = (pad & 0xc0) >> 2; // ?0SA 0000
  199. goto out;
  200. }
  201. else if(phase == 3) {
  202. if (out_bits & 0x40)
  203. return (pad & 0x30) | ((pad >> 8) & 0xf); // ?1CB MXYZ
  204. else
  205. return ((pad & 0xc0) >> 2) | 0x0f; // ?0SA 1111
  206. goto out;
  207. }
  208. if (out_bits & 0x40) // TH
  209. value = pad & 0x3f; // ?1CB RLDU
  210. else
  211. value = ((pad & 0xc0) >> 2) | (pad & 3); // ?0SA 00DU
  212. out:
  213. value |= out_bits & 0x40;
  214. return value;
  215. }
  216. static u32 read_nothing(int i, u32 out_bits)
  217. {
  218. return 0xff;
  219. }
  220. typedef u32 (port_read_func)(int index, u32 out_bits);
  221. static port_read_func *port_readers[3] = {
  222. read_pad_3btn,
  223. read_pad_3btn,
  224. read_nothing
  225. };
  226. static NOINLINE u32 port_read(int i)
  227. {
  228. u32 data_reg = PicoMem.ioports[i + 1];
  229. u32 ctrl_reg = PicoMem.ioports[i + 4] | 0x80;
  230. u32 in, out;
  231. out = data_reg & ctrl_reg;
  232. // pull-ups: should be 0x7f, but Decap Attack has a bug where it temp.
  233. // disables output before doing TH-low read, so don't emulate it for TH.
  234. // Decap Attack reportedly doesn't work on Nomad but works on must
  235. // other MD revisions (different pull-up strength?).
  236. if (PicoIn.AHW & PAHW_32X) // don't do it on 32X, it breaks WWF Raw
  237. out |= 0x7f & ~ctrl_reg;
  238. else
  239. out |= 0x3f & ~ctrl_reg;
  240. in = port_readers[i](i, out);
  241. return (in & ~ctrl_reg) | (data_reg & ctrl_reg);
  242. }
  243. void PicoSetInputDevice(int port, enum input_device device)
  244. {
  245. port_read_func *func;
  246. if (port < 0 || port > 2)
  247. return;
  248. switch (device) {
  249. case PICO_INPUT_PAD_3BTN:
  250. func = read_pad_3btn;
  251. break;
  252. case PICO_INPUT_PAD_6BTN:
  253. func = read_pad_6btn;
  254. break;
  255. default:
  256. func = read_nothing;
  257. break;
  258. }
  259. port_readers[port] = func;
  260. }
  261. NOINLINE u32 io_ports_read(u32 a)
  262. {
  263. u32 d;
  264. a = (a>>1) & 0xf;
  265. switch (a) {
  266. case 0: d = Pico.m.hardware; break; // Hardware value (Version register)
  267. case 1: d = port_read(0); break;
  268. case 2: d = port_read(1); break;
  269. case 3: d = port_read(2); break;
  270. default: d = PicoMem.ioports[a]; break; // IO ports can be used as RAM
  271. }
  272. return d;
  273. }
  274. NOINLINE void io_ports_write(u32 a, u32 d)
  275. {
  276. a = (a>>1) & 0xf;
  277. // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
  278. if (1 <= a && a <= 2)
  279. {
  280. Pico.m.padDelay[a - 1] = 0;
  281. if (!(PicoMem.ioports[a] & 0x40) && (d & 0x40))
  282. Pico.m.padTHPhase[a - 1]++;
  283. }
  284. // certain IO ports can be used as RAM
  285. PicoMem.ioports[a] = d;
  286. }
  287. static int z80_cycles_from_68k(void)
  288. {
  289. int m68k_cnt = SekCyclesDone() - Pico.t.m68c_frame_start;
  290. return cycles_68k_to_z80(m68k_cnt);
  291. }
  292. void NOINLINE ctl_write_z80busreq(u32 d)
  293. {
  294. d&=1; d^=1;
  295. elprintf(EL_BUSREQ, "set_zrun: %i->%i [%u] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);
  296. if (d ^ Pico.m.z80Run)
  297. {
  298. if (d)
  299. {
  300. Pico.t.z80c_cnt = z80_cycles_from_68k() + 2;
  301. }
  302. else
  303. {
  304. if ((PicoIn.opt & POPT_EN_Z80) && !Pico.m.z80_reset) {
  305. pprof_start(m68k);
  306. PicoSyncZ80(SekCyclesDone());
  307. pprof_end_sub(m68k);
  308. }
  309. }
  310. Pico.m.z80Run = d;
  311. }
  312. }
  313. void NOINLINE ctl_write_z80reset(u32 d)
  314. {
  315. d&=1; d^=1;
  316. elprintf(EL_BUSREQ, "set_zreset: %i->%i [%u] @%06x", Pico.m.z80_reset, d, SekCyclesDone(), SekPc);
  317. if (d ^ Pico.m.z80_reset)
  318. {
  319. if (d)
  320. {
  321. if ((PicoIn.opt & POPT_EN_Z80) && Pico.m.z80Run) {
  322. pprof_start(m68k);
  323. PicoSyncZ80(SekCyclesDone());
  324. pprof_end_sub(m68k);
  325. }
  326. YM2612ResetChip();
  327. timers_reset();
  328. }
  329. else
  330. {
  331. Pico.t.z80c_cnt = z80_cycles_from_68k() + 2;
  332. z80_reset();
  333. }
  334. Pico.m.z80_reset = d;
  335. }
  336. }
  337. static int get_scanline(int is_from_z80);
  338. static void psg_write_68k(u32 d)
  339. {
  340. // look for volume write and update if needed
  341. if ((d & 0x90) == 0x90)
  342. PsndDoPSG(Pico.m.scanline);
  343. SN76496Write(d);
  344. }
  345. static void psg_write_z80(u32 d)
  346. {
  347. if ((d & 0x90) == 0x90) {
  348. int scanline = get_scanline(1);
  349. PsndDoPSG(scanline);
  350. }
  351. SN76496Write(d);
  352. }
  353. // -----------------------------------------------------------------
  354. #ifndef _ASM_MEMORY_C
  355. // cart (save) RAM area (usually 0x200000 - ...)
  356. static u32 PicoRead8_sram(u32 a)
  357. {
  358. u32 d;
  359. if (Pico.sv.start <= a && a <= Pico.sv.end && (Pico.m.sram_reg & SRR_MAPPED))
  360. {
  361. if (Pico.sv.flags & SRF_EEPROM) {
  362. d = EEPROM_read();
  363. if (!(a & 1))
  364. d >>= 8;
  365. d &= 0xff;
  366. } else
  367. d = *(u8 *)(Pico.sv.data - Pico.sv.start + a);
  368. elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);
  369. return d;
  370. }
  371. // XXX: this is banking unfriendly
  372. if (a < Pico.romsize)
  373. return Pico.rom[a ^ 1];
  374. return m68k_unmapped_read8(a);
  375. }
  376. static u32 PicoRead16_sram(u32 a)
  377. {
  378. u32 d;
  379. if (Pico.sv.start <= a && a <= Pico.sv.end && (Pico.m.sram_reg & SRR_MAPPED))
  380. {
  381. if (Pico.sv.flags & SRF_EEPROM)
  382. d = EEPROM_read();
  383. else {
  384. u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);
  385. d = pm[0] << 8;
  386. d |= pm[1];
  387. }
  388. elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);
  389. return d;
  390. }
  391. if (a < Pico.romsize)
  392. return *(u16 *)(Pico.rom + a);
  393. return m68k_unmapped_read16(a);
  394. }
  395. #endif // _ASM_MEMORY_C
  396. static void PicoWrite8_sram(u32 a, u32 d)
  397. {
  398. if (a > Pico.sv.end || a < Pico.sv.start || !(Pico.m.sram_reg & SRR_MAPPED)) {
  399. m68k_unmapped_write8(a, d);
  400. return;
  401. }
  402. elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d & 0xff, SekPc);
  403. if (Pico.sv.flags & SRF_EEPROM)
  404. {
  405. EEPROM_write8(a, d);
  406. }
  407. else {
  408. u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);
  409. if (*pm != (u8)d) {
  410. Pico.sv.changed = 1;
  411. *pm = (u8)d;
  412. }
  413. }
  414. }
  415. static void PicoWrite16_sram(u32 a, u32 d)
  416. {
  417. if (a > Pico.sv.end || a < Pico.sv.start || !(Pico.m.sram_reg & SRR_MAPPED)) {
  418. m68k_unmapped_write16(a, d);
  419. return;
  420. }
  421. elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d & 0xffff, SekPc);
  422. if (Pico.sv.flags & SRF_EEPROM)
  423. {
  424. EEPROM_write16(d);
  425. }
  426. else {
  427. u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);
  428. if (pm[0] != (u8)(d >> 8)) {
  429. Pico.sv.changed = 1;
  430. pm[0] = (u8)(d >> 8);
  431. }
  432. if (pm[1] != (u8)d) {
  433. Pico.sv.changed = 1;
  434. pm[1] = (u8)d;
  435. }
  436. }
  437. }
  438. // z80 area (0xa00000 - 0xa0ffff)
  439. // TODO: verify mirrors VDP and bank reg (bank area mirroring verified)
  440. static u32 PicoRead8_z80(u32 a)
  441. {
  442. u32 d = 0xff;
  443. if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {
  444. elprintf(EL_ANOMALY, "68k z80 read with no bus! [%06x] @ %06x", a, SekPc);
  445. // open bus. Pulled down if MegaCD2 is attached.
  446. return 0;
  447. }
  448. if ((a & 0x4000) == 0x0000)
  449. d = PicoMem.zram[a & 0x1fff];
  450. else if ((a & 0x6000) == 0x4000) // 0x4000-0x5fff
  451. d = ym2612_read_local_68k();
  452. else
  453. elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
  454. return d;
  455. }
  456. static u32 PicoRead16_z80(u32 a)
  457. {
  458. u32 d = PicoRead8_z80(a);
  459. return d | (d << 8);
  460. }
  461. static void PicoWrite8_z80(u32 a, u32 d)
  462. {
  463. if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {
  464. // verified on real hw
  465. elprintf(EL_ANOMALY, "68k z80 write with no bus or reset! [%06x] %02x @ %06x", a, d&0xff, SekPc);
  466. return;
  467. }
  468. if ((a & 0x4000) == 0x0000) { // z80 RAM
  469. PicoMem.zram[a & 0x1fff] = (u8)d;
  470. return;
  471. }
  472. if ((a & 0x6000) == 0x4000) { // FM Sound
  473. if (PicoIn.opt & POPT_EN_FM)
  474. ym2612_write_local(a & 3, d & 0xff, 0);
  475. return;
  476. }
  477. // TODO: probably other VDP access too? Maybe more mirrors?
  478. if ((a & 0x7ff9) == 0x7f11) { // PSG Sound
  479. psg_write_68k(d);
  480. return;
  481. }
  482. if ((a & 0x7f00) == 0x6000) // Z80 BANK register
  483. {
  484. Pico.m.z80_bank68k >>= 1;
  485. Pico.m.z80_bank68k |= d << 8;
  486. Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one
  487. elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k << 15);
  488. return;
  489. }
  490. elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @ %06x", a, d&0xff, SekPc);
  491. }
  492. static void PicoWrite16_z80(u32 a, u32 d)
  493. {
  494. // for RAM, only most significant byte is sent
  495. // TODO: verify remaining accesses
  496. PicoWrite8_z80(a, d >> 8);
  497. }
  498. #ifndef _ASM_MEMORY_C
  499. // IO/control area (0xa10000 - 0xa1ffff)
  500. u32 PicoRead8_io(u32 a)
  501. {
  502. u32 d;
  503. if ((a & 0xffe0) == 0x0000) { // I/O ports
  504. d = io_ports_read(a);
  505. goto end;
  506. }
  507. // faking open bus (MegaCD pulldowns don't work here curiously)
  508. d = Pico.m.rotate++;
  509. d ^= d << 6;
  510. if ((a & 0xfc00) == 0x1000) {
  511. // bit8 seems to be readable in this range
  512. if (!(a & 1))
  513. d &= ~0x01;
  514. if ((a & 0xff01) == 0x1100) { // z80 busreq (verified)
  515. d |= (Pico.m.z80Run | Pico.m.z80_reset) & 1;
  516. elprintf(EL_BUSREQ, "get_zrun: %02x [%u] @%06x", d, SekCyclesDone(), SekPc);
  517. }
  518. goto end;
  519. }
  520. d = PicoRead8_32x(a);
  521. end:
  522. return d;
  523. }
  524. u32 PicoRead16_io(u32 a)
  525. {
  526. u32 d;
  527. if ((a & 0xffe0) == 0x0000) { // I/O ports
  528. d = io_ports_read(a);
  529. d |= d << 8;
  530. goto end;
  531. }
  532. // faking open bus
  533. d = (Pico.m.rotate += 0x41);
  534. d ^= (d << 5) ^ (d << 8);
  535. // bit8 seems to be readable in this range
  536. if ((a & 0xfc00) == 0x1000) {
  537. d &= ~0x0100;
  538. if ((a & 0xff00) == 0x1100) { // z80 busreq
  539. d |= ((Pico.m.z80Run | Pico.m.z80_reset) & 1) << 8;
  540. elprintf(EL_BUSREQ, "get_zrun: %04x [%u] @%06x", d, SekCyclesDone(), SekPc);
  541. }
  542. goto end;
  543. }
  544. d = PicoRead16_32x(a);
  545. end:
  546. return d;
  547. }
  548. void PicoWrite8_io(u32 a, u32 d)
  549. {
  550. if ((a & 0xffe1) == 0x0001) { // I/O ports (verified: only LSB!)
  551. io_ports_write(a, d);
  552. return;
  553. }
  554. if ((a & 0xff01) == 0x1100) { // z80 busreq
  555. ctl_write_z80busreq(d);
  556. return;
  557. }
  558. if ((a & 0xff01) == 0x1200) { // z80 reset
  559. ctl_write_z80reset(d);
  560. return;
  561. }
  562. if (a == 0xa130f1) { // sram access register
  563. elprintf(EL_SRAMIO, "sram reg=%02x", d);
  564. Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);
  565. Pico.m.sram_reg |= (u8)(d & 3);
  566. return;
  567. }
  568. PicoWrite8_32x(a, d);
  569. }
  570. void PicoWrite16_io(u32 a, u32 d)
  571. {
  572. if ((a & 0xffe0) == 0x0000) { // I/O ports (verified: only LSB!)
  573. io_ports_write(a, d);
  574. return;
  575. }
  576. if ((a & 0xff00) == 0x1100) { // z80 busreq
  577. ctl_write_z80busreq(d >> 8);
  578. return;
  579. }
  580. if ((a & 0xff00) == 0x1200) { // z80 reset
  581. ctl_write_z80reset(d >> 8);
  582. return;
  583. }
  584. if (a == 0xa130f0) { // sram access register
  585. elprintf(EL_SRAMIO, "sram reg=%02x", d);
  586. Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);
  587. Pico.m.sram_reg |= (u8)(d & 3);
  588. return;
  589. }
  590. PicoWrite16_32x(a, d);
  591. }
  592. #endif // _ASM_MEMORY_C
  593. // VDP area (0xc00000 - 0xdfffff)
  594. // TODO: verify if lower byte goes to PSG on word writes
  595. u32 PicoRead8_vdp(u32 a)
  596. {
  597. if ((a & 0x00f0) == 0x0000) {
  598. switch (a & 0x0d)
  599. {
  600. case 0x00: return PicoVideoRead8DataH(0);
  601. case 0x01: return PicoVideoRead8DataL(0);
  602. case 0x04: return PicoVideoRead8CtlH(0);
  603. case 0x05: return PicoVideoRead8CtlL(0);
  604. case 0x08:
  605. case 0x0c: return PicoVideoRead8HV_H(0);
  606. case 0x09:
  607. case 0x0d: return PicoVideoRead8HV_L(0);
  608. }
  609. }
  610. elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
  611. return 0;
  612. }
  613. static u32 PicoRead16_vdp(u32 a)
  614. {
  615. if ((a & 0x00e0) == 0x0000)
  616. return PicoVideoRead(a);
  617. elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
  618. return 0;
  619. }
  620. static void PicoWrite8_vdp(u32 a, u32 d)
  621. {
  622. if ((a & 0x00f9) == 0x0011) { // PSG Sound
  623. psg_write_68k(d);
  624. return;
  625. }
  626. if ((a & 0x00e0) == 0x0000) {
  627. d &= 0xff;
  628. PicoVideoWrite(a, d | (d << 8));
  629. return;
  630. }
  631. elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @%06x", a, d & 0xff, SekPc);
  632. }
  633. static void PicoWrite16_vdp(u32 a, u32 d)
  634. {
  635. if ((a & 0x00f9) == 0x0010) { // PSG Sound
  636. psg_write_68k(d);
  637. return;
  638. }
  639. if ((a & 0x00e0) == 0x0000) {
  640. PicoVideoWrite(a, d);
  641. return;
  642. }
  643. elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  644. }
  645. // -----------------------------------------------------------------
  646. #ifdef EMU_M68K
  647. static void m68k_mem_setup(void);
  648. #endif
  649. PICO_INTERNAL void PicoMemSetup(void)
  650. {
  651. int mask, rs, sstart, a;
  652. // setup the memory map
  653. cpu68k_map_set(m68k_read8_map, 0x000000, 0xffffff, m68k_unmapped_read8, 1);
  654. cpu68k_map_set(m68k_read16_map, 0x000000, 0xffffff, m68k_unmapped_read16, 1);
  655. cpu68k_map_set(m68k_write8_map, 0x000000, 0xffffff, m68k_unmapped_write8, 1);
  656. cpu68k_map_set(m68k_write16_map, 0x000000, 0xffffff, m68k_unmapped_write16, 1);
  657. // ROM
  658. // align to bank size. We know ROM loader allocated enough for this
  659. mask = (1 << M68K_MEM_SHIFT) - 1;
  660. rs = (Pico.romsize + mask) & ~mask;
  661. cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico.rom, 0);
  662. cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico.rom, 0);
  663. // Common case of on-cart (save) RAM, usually at 0x200000-...
  664. if ((Pico.sv.flags & SRF_ENABLED) && Pico.sv.data != NULL) {
  665. sstart = Pico.sv.start;
  666. rs = Pico.sv.end - sstart;
  667. rs = (rs + mask) & ~mask;
  668. if (sstart + rs >= 0x1000000)
  669. rs = 0x1000000 - sstart;
  670. cpu68k_map_set(m68k_read8_map, sstart, sstart + rs - 1, PicoRead8_sram, 1);
  671. cpu68k_map_set(m68k_read16_map, sstart, sstart + rs - 1, PicoRead16_sram, 1);
  672. cpu68k_map_set(m68k_write8_map, sstart, sstart + rs - 1, PicoWrite8_sram, 1);
  673. cpu68k_map_set(m68k_write16_map, sstart, sstart + rs - 1, PicoWrite16_sram, 1);
  674. }
  675. // Z80 region
  676. cpu68k_map_set(m68k_read8_map, 0xa00000, 0xa0ffff, PicoRead8_z80, 1);
  677. cpu68k_map_set(m68k_read16_map, 0xa00000, 0xa0ffff, PicoRead16_z80, 1);
  678. cpu68k_map_set(m68k_write8_map, 0xa00000, 0xa0ffff, PicoWrite8_z80, 1);
  679. cpu68k_map_set(m68k_write16_map, 0xa00000, 0xa0ffff, PicoWrite16_z80, 1);
  680. // IO/control region
  681. cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_io, 1);
  682. cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_io, 1);
  683. cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_io, 1);
  684. cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_io, 1);
  685. // VDP region
  686. for (a = 0xc00000; a < 0xe00000; a += 0x010000) {
  687. if ((a & 0xe700e0) != 0xc00000)
  688. continue;
  689. cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoRead8_vdp, 1);
  690. cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoRead16_vdp, 1);
  691. cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoWrite8_vdp, 1);
  692. cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoWrite16_vdp, 1);
  693. }
  694. // RAM and it's mirrors
  695. for (a = 0xe00000; a < 0x1000000; a += 0x010000) {
  696. cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoMem.ram, 0);
  697. cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoMem.ram, 0);
  698. cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoMem.ram, 0);
  699. cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoMem.ram, 0);
  700. }
  701. // Setup memory callbacks:
  702. #ifdef EMU_C68K
  703. PicoCpuCM68k.read8 = (void *)m68k_read8_map;
  704. PicoCpuCM68k.read16 = (void *)m68k_read16_map;
  705. PicoCpuCM68k.read32 = (void *)m68k_read16_map;
  706. PicoCpuCM68k.write8 = (void *)m68k_write8_map;
  707. PicoCpuCM68k.write16 = (void *)m68k_write16_map;
  708. PicoCpuCM68k.write32 = (void *)m68k_write16_map;
  709. PicoCpuCM68k.checkpc = NULL; /* unused */
  710. PicoCpuCM68k.fetch8 = NULL;
  711. PicoCpuCM68k.fetch16 = NULL;
  712. PicoCpuCM68k.fetch32 = NULL;
  713. #endif
  714. #ifdef EMU_F68K
  715. PicoCpuFM68k.read_byte = (void *)m68k_read8;
  716. PicoCpuFM68k.read_word = (void *)m68k_read16;
  717. PicoCpuFM68k.read_long = (void *)m68k_read32;
  718. PicoCpuFM68k.write_byte = (void *)m68k_write8;
  719. PicoCpuFM68k.write_word = (void *)m68k_write16;
  720. PicoCpuFM68k.write_long = (void *)m68k_write32;
  721. // setup FAME fetchmap
  722. {
  723. int i;
  724. // by default, point everything to first 64k of ROM
  725. for (i = 0; i < M68K_FETCHBANK1 * 0xe0 / 0x100; i++)
  726. PicoCpuFM68k.Fetch[i] = (uptr)Pico.rom - (i<<(24-FAMEC_FETCHBITS));
  727. // now real ROM
  728. for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)
  729. PicoCpuFM68k.Fetch[i] = (uptr)Pico.rom;
  730. // RAM already set
  731. }
  732. #endif
  733. #ifdef EMU_M68K
  734. m68k_mem_setup();
  735. #endif
  736. z80_mem_setup();
  737. }
  738. #ifdef EMU_M68K
  739. unsigned int (*pm68k_read_memory_8) (unsigned int address) = NULL;
  740. unsigned int (*pm68k_read_memory_16)(unsigned int address) = NULL;
  741. unsigned int (*pm68k_read_memory_32)(unsigned int address) = NULL;
  742. void (*pm68k_write_memory_8) (unsigned int address, unsigned char value) = NULL;
  743. void (*pm68k_write_memory_16)(unsigned int address, unsigned short value) = NULL;
  744. void (*pm68k_write_memory_32)(unsigned int address, unsigned int value) = NULL;
  745. /* it appears that Musashi doesn't always mask the unused bits */
  746. unsigned int m68k_read_memory_8 (unsigned int address) { return pm68k_read_memory_8 (address) & 0xff; }
  747. unsigned int m68k_read_memory_16(unsigned int address) { return pm68k_read_memory_16(address) & 0xffff; }
  748. unsigned int m68k_read_memory_32(unsigned int address) { return pm68k_read_memory_32(address); }
  749. void m68k_write_memory_8 (unsigned int address, unsigned int value) { pm68k_write_memory_8 (address, (u8)value); }
  750. void m68k_write_memory_16(unsigned int address, unsigned int value) { pm68k_write_memory_16(address,(u16)value); }
  751. void m68k_write_memory_32(unsigned int address, unsigned int value) { pm68k_write_memory_32(address, value); }
  752. static void m68k_mem_setup(void)
  753. {
  754. pm68k_read_memory_8 = m68k_read8;
  755. pm68k_read_memory_16 = m68k_read16;
  756. pm68k_read_memory_32 = m68k_read32;
  757. pm68k_write_memory_8 = m68k_write8;
  758. pm68k_write_memory_16 = m68k_write16;
  759. pm68k_write_memory_32 = m68k_write32;
  760. }
  761. #endif // EMU_M68K
  762. // -----------------------------------------------------------------
  763. static int get_scanline(int is_from_z80)
  764. {
  765. if (is_from_z80) {
  766. int mclk_z80 = (z80_cyclesLeft<0 ? Pico.t.z80c_aim : z80_cyclesDone()) * 15;
  767. int mclk_line = Pico.t.z80_scanline * 488 * 7;
  768. while (mclk_z80 - mclk_line >= 488 * 7)
  769. Pico.t.z80_scanline++, mclk_line += 488 * 7;
  770. return Pico.t.z80_scanline;
  771. }
  772. return Pico.m.scanline;
  773. }
  774. /* probably should not be in this file, but it's near related code here */
  775. void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new)
  776. {
  777. int xcycles = z80_cycles << 8;
  778. /* check for overflows */
  779. if ((mode_old & 4) && xcycles >= Pico.t.timer_a_next_oflow)
  780. ym2612.OPN.ST.status |= 1;
  781. if ((mode_old & 8) && xcycles >= Pico.t.timer_b_next_oflow)
  782. ym2612.OPN.ST.status |= 2;
  783. /* update timer a */
  784. if (mode_old & 1)
  785. while (xcycles > Pico.t.timer_a_next_oflow)
  786. Pico.t.timer_a_next_oflow += Pico.t.timer_a_step;
  787. if ((mode_old ^ mode_new) & 1) // turning on/off
  788. {
  789. if (mode_old & 1)
  790. Pico.t.timer_a_next_oflow = TIMER_NO_OFLOW;
  791. else
  792. Pico.t.timer_a_next_oflow = xcycles + Pico.t.timer_a_step;
  793. }
  794. if (mode_new & 1)
  795. elprintf(EL_YMTIMER, "timer a upd to %i @ %i", Pico.t.timer_a_next_oflow>>8, z80_cycles);
  796. /* update timer b */
  797. if (mode_old & 2)
  798. while (xcycles > Pico.t.timer_b_next_oflow)
  799. Pico.t.timer_b_next_oflow += Pico.t.timer_b_step;
  800. if ((mode_old ^ mode_new) & 2)
  801. {
  802. if (mode_old & 2)
  803. Pico.t.timer_b_next_oflow = TIMER_NO_OFLOW;
  804. else
  805. Pico.t.timer_b_next_oflow = xcycles + Pico.t.timer_b_step;
  806. }
  807. if (mode_new & 2)
  808. elprintf(EL_YMTIMER, "timer b upd to %i @ %i", Pico.t.timer_b_next_oflow>>8, z80_cycles);
  809. }
  810. // ym2612 DAC and timer I/O handlers for z80
  811. static int ym2612_write_local(u32 a, u32 d, int is_from_z80)
  812. {
  813. int addr;
  814. a &= 3;
  815. if (a == 1 && ym2612.OPN.ST.address == 0x2a) /* DAC data */
  816. {
  817. int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
  818. //elprintf(EL_STATUS, "%03i dac w %08x z80 %i", cycles, d, is_from_z80);
  819. if (ym2612.dacen)
  820. PsndDoDAC(cycles);
  821. ym2612.dacout = ((int)d - 0x80) << 6;
  822. return 0;
  823. }
  824. switch (a)
  825. {
  826. case 0: /* address port 0 */
  827. ym2612.OPN.ST.address = d;
  828. ym2612.addr_A1 = 0;
  829. #ifdef __GP2X__
  830. if (PicoIn.opt & POPT_EXT_FM) YM2612Write_940(a, d, -1);
  831. #endif
  832. return 0;
  833. case 1: /* data port 0 */
  834. if (ym2612.addr_A1 != 0)
  835. return 0;
  836. addr = ym2612.OPN.ST.address;
  837. ym2612.REGS[addr] = d;
  838. switch (addr)
  839. {
  840. case 0x24: // timer A High 8
  841. case 0x25: { // timer A Low 2
  842. int TAnew = (addr == 0x24) ? ((ym2612.OPN.ST.TA & 0x03)|(((int)d)<<2))
  843. : ((ym2612.OPN.ST.TA & 0x3fc)|(d&3));
  844. if (ym2612.OPN.ST.TA != TAnew)
  845. {
  846. //elprintf(EL_STATUS, "timer a set %i", TAnew);
  847. ym2612.OPN.ST.TA = TAnew;
  848. //ym2612.OPN.ST.TAC = (1024-TAnew)*18;
  849. //ym2612.OPN.ST.TAT = 0;
  850. Pico.t.timer_a_step = TIMER_A_TICK_ZCYCLES * (1024 - TAnew);
  851. if (ym2612.OPN.ST.mode & 1) {
  852. // this is not right, should really be done on overflow only
  853. int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
  854. Pico.t.timer_a_next_oflow = (cycles << 8) + Pico.t.timer_a_step;
  855. }
  856. elprintf(EL_YMTIMER, "timer a set to %i, %i", 1024 - TAnew, Pico.t.timer_a_next_oflow>>8);
  857. }
  858. return 0;
  859. }
  860. case 0x26: // timer B
  861. if (ym2612.OPN.ST.TB != d) {
  862. //elprintf(EL_STATUS, "timer b set %i", d);
  863. ym2612.OPN.ST.TB = d;
  864. //ym2612.OPN.ST.TBC = (256-d) * 288;
  865. //ym2612.OPN.ST.TBT = 0;
  866. Pico.t.timer_b_step = TIMER_B_TICK_ZCYCLES * (256 - d); // 262800
  867. if (ym2612.OPN.ST.mode & 2) {
  868. int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
  869. Pico.t.timer_b_next_oflow = (cycles << 8) + Pico.t.timer_b_step;
  870. }
  871. elprintf(EL_YMTIMER, "timer b set to %i, %i", 256 - d, Pico.t.timer_b_next_oflow>>8);
  872. }
  873. return 0;
  874. case 0x27: { /* mode, timer control */
  875. int old_mode = ym2612.OPN.ST.mode;
  876. int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
  877. ym2612.OPN.ST.mode = d;
  878. elprintf(EL_YMTIMER, "st mode %02x", d);
  879. ym2612_sync_timers(cycles, old_mode, d);
  880. /* reset Timer a flag */
  881. if (d & 0x10)
  882. ym2612.OPN.ST.status &= ~1;
  883. /* reset Timer b flag */
  884. if (d & 0x20)
  885. ym2612.OPN.ST.status &= ~2;
  886. if ((d ^ old_mode) & 0xc0) {
  887. #ifdef __GP2X__
  888. if (PicoIn.opt & POPT_EXT_FM) return YM2612Write_940(a, d, get_scanline(is_from_z80));
  889. #endif
  890. PsndDoFM(cycles);
  891. return 1;
  892. }
  893. return 0;
  894. }
  895. case 0x2b: { /* DAC Sel (YM2612) */
  896. ym2612.dacen = d & 0x80;
  897. #ifdef __GP2X__
  898. if (PicoIn.opt & POPT_EXT_FM) YM2612Write_940(a, d, get_scanline(is_from_z80));
  899. #endif
  900. return 0;
  901. }
  902. }
  903. break;
  904. case 2: /* address port 1 */
  905. ym2612.OPN.ST.address = d;
  906. ym2612.addr_A1 = 1;
  907. #ifdef __GP2X__
  908. if (PicoIn.opt & POPT_EXT_FM) YM2612Write_940(a, d, -1);
  909. #endif
  910. return 0;
  911. case 3: /* data port 1 */
  912. if (ym2612.addr_A1 != 1)
  913. return 0;
  914. addr = ym2612.OPN.ST.address | 0x100;
  915. ym2612.REGS[addr] = d;
  916. break;
  917. }
  918. #ifdef __GP2X__
  919. if (PicoIn.opt & POPT_EXT_FM)
  920. return YM2612Write_940(a, d, get_scanline(is_from_z80));
  921. #endif
  922. PsndDoFM(is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k());
  923. return YM2612Write_(a, d);
  924. }
  925. #define ym2612_read_local() \
  926. if (xcycles >= Pico.t.timer_a_next_oflow) \
  927. ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 1; \
  928. if (xcycles >= Pico.t.timer_b_next_oflow) \
  929. ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 2
  930. static u32 ym2612_read_local_z80(void)
  931. {
  932. int xcycles = z80_cyclesDone() << 8;
  933. ym2612_read_local();
  934. elprintf(EL_YMTIMER, "timer z80 read %i, sched %i, %i @ %i|%i",
  935. ym2612.OPN.ST.status, Pico.t.timer_a_next_oflow >> 8,
  936. Pico.t.timer_b_next_oflow >> 8, xcycles >> 8, (xcycles >> 8) / 228);
  937. return ym2612.OPN.ST.status;
  938. }
  939. static u32 ym2612_read_local_68k(void)
  940. {
  941. int xcycles = z80_cycles_from_68k() << 8;
  942. ym2612_read_local();
  943. elprintf(EL_YMTIMER, "timer 68k read %i, sched %i, %i @ %i|%i",
  944. ym2612.OPN.ST.status, Pico.t.timer_a_next_oflow >> 8,
  945. Pico.t.timer_b_next_oflow >> 8, xcycles >> 8, (xcycles >> 8) / 228);
  946. return ym2612.OPN.ST.status;
  947. }
  948. void ym2612_pack_state(void)
  949. {
  950. // timers are saved as tick counts, in 16.16 int format
  951. int tac, tat = 0, tbc, tbt = 0;
  952. tac = 1024 - ym2612.OPN.ST.TA;
  953. tbc = 256 - ym2612.OPN.ST.TB;
  954. if (Pico.t.timer_a_next_oflow != TIMER_NO_OFLOW)
  955. tat = (int)((double)(Pico.t.timer_a_step - Pico.t.timer_a_next_oflow)
  956. / (double)Pico.t.timer_a_step * tac * 65536);
  957. if (Pico.t.timer_b_next_oflow != TIMER_NO_OFLOW)
  958. tbt = (int)((double)(Pico.t.timer_b_step - Pico.t.timer_b_next_oflow)
  959. / (double)Pico.t.timer_b_step * tbc * 65536);
  960. elprintf(EL_YMTIMER, "save: timer a %i/%i", tat >> 16, tac);
  961. elprintf(EL_YMTIMER, "save: timer b %i/%i", tbt >> 16, tbc);
  962. #ifdef __GP2X__
  963. if (PicoIn.opt & POPT_EXT_FM)
  964. YM2612PicoStateSave2_940(tat, tbt);
  965. else
  966. #endif
  967. YM2612PicoStateSave2(tat, tbt);
  968. }
  969. void ym2612_unpack_state(void)
  970. {
  971. int i, ret, tac, tat, tbc, tbt;
  972. YM2612PicoStateLoad();
  973. // feed all the registers and update internal state
  974. for (i = 0x20; i < 0xA0; i++) {
  975. ym2612_write_local(0, i, 0);
  976. ym2612_write_local(1, ym2612.REGS[i], 0);
  977. }
  978. for (i = 0x30; i < 0xA0; i++) {
  979. ym2612_write_local(2, i, 0);
  980. ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
  981. }
  982. for (i = 0xAF; i >= 0xA0; i--) { // must apply backwards
  983. ym2612_write_local(2, i, 0);
  984. ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
  985. ym2612_write_local(0, i, 0);
  986. ym2612_write_local(1, ym2612.REGS[i], 0);
  987. }
  988. for (i = 0xB0; i < 0xB8; i++) {
  989. ym2612_write_local(0, i, 0);
  990. ym2612_write_local(1, ym2612.REGS[i], 0);
  991. ym2612_write_local(2, i, 0);
  992. ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
  993. }
  994. #ifdef __GP2X__
  995. if (PicoIn.opt & POPT_EXT_FM)
  996. ret = YM2612PicoStateLoad2_940(&tat, &tbt);
  997. else
  998. #endif
  999. ret = YM2612PicoStateLoad2(&tat, &tbt);
  1000. if (ret != 0) {
  1001. elprintf(EL_STATUS, "old ym2612 state");
  1002. return; // no saved timers
  1003. }
  1004. tac = (1024 - ym2612.OPN.ST.TA) << 16;
  1005. tbc = (256 - ym2612.OPN.ST.TB) << 16;
  1006. if (ym2612.OPN.ST.mode & 1)
  1007. Pico.t.timer_a_next_oflow = (int)((double)(tac - tat) / (double)tac * Pico.t.timer_a_step);
  1008. else
  1009. Pico.t.timer_a_next_oflow = TIMER_NO_OFLOW;
  1010. if (ym2612.OPN.ST.mode & 2)
  1011. Pico.t.timer_b_next_oflow = (int)((double)(tbc - tbt) / (double)tbc * Pico.t.timer_b_step);
  1012. else
  1013. Pico.t.timer_b_next_oflow = TIMER_NO_OFLOW;
  1014. elprintf(EL_YMTIMER, "load: %i/%i, timer_a_next_oflow %i", tat>>16, tac>>16, Pico.t.timer_a_next_oflow >> 8);
  1015. elprintf(EL_YMTIMER, "load: %i/%i, timer_b_next_oflow %i", tbt>>16, tbc>>16, Pico.t.timer_b_next_oflow >> 8);
  1016. }
  1017. #if defined(NO_32X) && defined(_ASM_MEMORY_C)
  1018. // referenced by asm code
  1019. u32 PicoRead8_32x(u32 a) { return 0; }
  1020. u32 PicoRead16_32x(u32 a) { return 0; }
  1021. void PicoWrite8_32x(u32 a, u32 d) {}
  1022. void PicoWrite16_32x(u32 a, u32 d) {}
  1023. #endif
  1024. // -----------------------------------------------------------------
  1025. // z80 memhandlers
  1026. static unsigned char z80_md_vdp_read(unsigned short a)
  1027. {
  1028. z80_subCLeft(2);
  1029. if ((a & 0x00f0) == 0x0000) {
  1030. switch (a & 0x0d)
  1031. {
  1032. case 0x00: return PicoVideoRead8DataH(1);
  1033. case 0x01: return PicoVideoRead8DataL(1);
  1034. case 0x04: return PicoVideoRead8CtlH(1);
  1035. case 0x05: return PicoVideoRead8CtlL(1);
  1036. case 0x08:
  1037. case 0x0c: return get_scanline(1); // FIXME: make it proper
  1038. case 0x09:
  1039. case 0x0d: return Pico.m.rotate++;
  1040. }
  1041. }
  1042. elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, 0xff);
  1043. return 0xff;
  1044. }
  1045. static unsigned char z80_md_bank_read(unsigned short a)
  1046. {
  1047. unsigned int addr68k;
  1048. unsigned char ret;
  1049. z80_subCLeft(3);
  1050. addr68k = Pico.m.z80_bank68k << 15;
  1051. addr68k |= a & 0x7fff;
  1052. ret = m68k_read8(addr68k);
  1053. elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);
  1054. return ret;
  1055. }
  1056. static void z80_md_ym2612_write(unsigned int a, unsigned char data)
  1057. {
  1058. if (PicoIn.opt & POPT_EN_FM)
  1059. ym2612_write_local(a, data, 1);
  1060. }
  1061. static void z80_md_vdp_br_write(unsigned int a, unsigned char data)
  1062. {
  1063. if ((a&0xfff9) == 0x7f11) // 7f11 7f13 7f15 7f17
  1064. {
  1065. psg_write_z80(data);
  1066. return;
  1067. }
  1068. // at least VDP data writes hang my machine
  1069. if ((a>>8) == 0x60)
  1070. {
  1071. Pico.m.z80_bank68k >>= 1;
  1072. Pico.m.z80_bank68k |= data << 8;
  1073. Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one
  1074. return;
  1075. }
  1076. elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);
  1077. }
  1078. static void z80_md_bank_write(unsigned int a, unsigned char data)
  1079. {
  1080. unsigned int addr68k;
  1081. addr68k = Pico.m.z80_bank68k << 15;
  1082. addr68k += a & 0x7fff;
  1083. elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);
  1084. m68k_write8(addr68k, data);
  1085. }
  1086. // -----------------------------------------------------------------
  1087. static unsigned char z80_md_in(unsigned short p)
  1088. {
  1089. elprintf(EL_ANOMALY, "Z80 port %04x read", p);
  1090. return 0xff;
  1091. }
  1092. static void z80_md_out(unsigned short p, unsigned char d)
  1093. {
  1094. elprintf(EL_ANOMALY, "Z80 port %04x write %02x", p, d);
  1095. }
  1096. static void z80_mem_setup(void)
  1097. {
  1098. z80_map_set(z80_read_map, 0x0000, 0x1fff, PicoMem.zram, 0);
  1099. z80_map_set(z80_read_map, 0x2000, 0x3fff, PicoMem.zram, 0);
  1100. z80_map_set(z80_read_map, 0x4000, 0x5fff, ym2612_read_local_z80, 1);
  1101. z80_map_set(z80_read_map, 0x6000, 0x7fff, z80_md_vdp_read, 1);
  1102. z80_map_set(z80_read_map, 0x8000, 0xffff, z80_md_bank_read, 1);
  1103. z80_map_set(z80_write_map, 0x0000, 0x1fff, PicoMem.zram, 0);
  1104. z80_map_set(z80_write_map, 0x2000, 0x3fff, PicoMem.zram, 0);
  1105. z80_map_set(z80_write_map, 0x4000, 0x5fff, z80_md_ym2612_write, 1);
  1106. z80_map_set(z80_write_map, 0x6000, 0x7fff, z80_md_vdp_br_write, 1);
  1107. z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write, 1);
  1108. #ifdef _USE_DRZ80
  1109. drZ80.z80_in = z80_md_in;
  1110. drZ80.z80_out = z80_md_out;
  1111. #endif
  1112. #ifdef _USE_CZ80
  1113. Cz80_Set_Fetch(&CZ80, 0x0000, 0x1fff, (FPTR)PicoMem.zram); // main RAM
  1114. Cz80_Set_Fetch(&CZ80, 0x2000, 0x3fff, (FPTR)PicoMem.zram); // mirror
  1115. Cz80_Set_INPort(&CZ80, z80_md_in);
  1116. Cz80_Set_OUTPort(&CZ80, z80_md_out);
  1117. #endif
  1118. }
  1119. // vim:shiftwidth=2:ts=2:expandtab