eeprom.c 6.7 KB

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  1. /*
  2. * rarely used EEPROM code
  3. *
  4. * (see Genesis Plus for Wii/GC code and docs for info,
  5. * full game list and better code).
  6. */
  7. #include "pico_int.h"
  8. static unsigned int last_write = 0xffff0000;
  9. // eeprom_status: LA.. s.la (L=pending SCL, A=pending SDA,
  10. // s=started, l=old SCL, a=old SDA)
  11. static void EEPROM_write_do(unsigned int d) // ???? ??la (l=SCL, a=SDA)
  12. {
  13. unsigned int sreg = Pico.m.eeprom_status, saddr = Pico.m.eeprom_addr;
  14. unsigned int scyc = Pico.m.eeprom_cycle, ssa = Pico.m.eeprom_slave;
  15. elprintf(EL_EEPROM, "eeprom: scl/sda: %i/%i -> %i/%i, newtime=%i", (sreg&2)>>1, sreg&1,
  16. (d&2)>>1, d&1, SekCyclesDoneT() - last_write);
  17. saddr &= 0x1fff;
  18. if(sreg & d & 2) {
  19. // SCL was and is still high..
  20. if((sreg & 1) && !(d&1)) {
  21. // ..and SDA went low, means it's a start command, so clear internal addr reg and clock counter
  22. elprintf(EL_EEPROM, "eeprom: -start-");
  23. //saddr = 0;
  24. scyc = 0;
  25. sreg |= 8;
  26. } else if(!(sreg & 1) && (d&1)) {
  27. // SDA went high == stop command
  28. elprintf(EL_EEPROM, "eeprom: -stop-");
  29. sreg &= ~8;
  30. }
  31. }
  32. else if((sreg & 8) && !(sreg & 2) && (d&2))
  33. {
  34. // we are started and SCL went high - next cycle
  35. scyc++; // pre-increment
  36. if(SRam.eeprom_type) {
  37. // X24C02+
  38. if((ssa&1) && scyc == 18) {
  39. scyc = 9;
  40. saddr++; // next address in read mode
  41. /*if(SRam.eeprom_type==2) saddr&=0xff; else*/ saddr&=0x1fff; // mask
  42. }
  43. else if(SRam.eeprom_type == 2 && scyc == 27) scyc = 18;
  44. else if(scyc == 36) scyc = 27;
  45. } else {
  46. // X24C01
  47. if(scyc == 18) {
  48. scyc = 9; // wrap
  49. if(saddr&1) { saddr+=2; saddr&=0xff; } // next addr in read mode
  50. }
  51. }
  52. elprintf(EL_EEPROM, "eeprom: scyc: %i", scyc);
  53. }
  54. else if((sreg & 8) && (sreg & 2) && !(d&2))
  55. {
  56. // we are started and SCL went low (falling edge)
  57. if(SRam.eeprom_type) {
  58. // X24C02+
  59. if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles
  60. else if( (SRam.eeprom_type == 3 && scyc > 27) || (SRam.eeprom_type == 2 && scyc > 18) ) {
  61. if(!(ssa&1)) {
  62. // data write
  63. unsigned char *pm=SRam.data+saddr;
  64. *pm <<= 1; *pm |= d&1;
  65. if(scyc == 26 || scyc == 35) {
  66. saddr=(saddr&~0xf)|((saddr+1)&0xf); // only 4 (?) lowest bits are incremented
  67. elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr, *pm);
  68. }
  69. SRam.changed = 1;
  70. }
  71. } else if(scyc > 9) {
  72. if(!(ssa&1)) {
  73. // we latch another addr bit
  74. saddr<<=1;
  75. if(SRam.eeprom_type == 2) saddr&=0xff; else saddr&=0x1fff; // mask
  76. saddr|=d&1;
  77. if(scyc==17||scyc==26) {
  78. elprintf(EL_EEPROM, "eeprom: addr reg done: %x", saddr);
  79. if(scyc==17&&SRam.eeprom_type==2) { saddr&=0xff; saddr|=(ssa<<7)&0x700; } // add device bits too
  80. }
  81. }
  82. } else {
  83. // slave address
  84. ssa<<=1; ssa|=d&1;
  85. if(scyc==8) elprintf(EL_EEPROM, "eeprom: slave done: %x", ssa);
  86. }
  87. } else {
  88. // X24C01
  89. if(scyc == 9); // ACK cycle, do nothing
  90. else if(scyc > 9) {
  91. if(!(saddr&1)) {
  92. // data write
  93. unsigned char *pm=SRam.data+(saddr>>1);
  94. *pm <<= 1; *pm |= d&1;
  95. if(scyc == 17) {
  96. saddr=(saddr&0xf9)|((saddr+2)&6); // only 2 lowest bits are incremented
  97. elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr>>1, *pm);
  98. }
  99. SRam.changed = 1;
  100. }
  101. } else {
  102. // we latch another addr bit
  103. saddr<<=1; saddr|=d&1; saddr&=0xff;
  104. if(scyc==8) elprintf(EL_EEPROM, "eeprom: addr done: %x", saddr>>1);
  105. }
  106. }
  107. }
  108. sreg &= ~3; sreg |= d&3; // remember SCL and SDA
  109. Pico.m.eeprom_status = (unsigned char) sreg;
  110. Pico.m.eeprom_cycle = (unsigned char) scyc;
  111. Pico.m.eeprom_slave = (unsigned char) ssa;
  112. Pico.m.eeprom_addr = (unsigned short)saddr;
  113. }
  114. static void EEPROM_upd_pending(unsigned int d)
  115. {
  116. unsigned int d1, sreg = Pico.m.eeprom_status;
  117. sreg &= ~0xc0;
  118. // SCL
  119. d1 = (d >> SRam.eeprom_bit_cl) & 1;
  120. sreg |= d1 << 7;
  121. // SDA in
  122. d1 = (d >> SRam.eeprom_bit_in) & 1;
  123. sreg |= d1 << 6;
  124. Pico.m.eeprom_status = (unsigned char) sreg;
  125. }
  126. void EEPROM_write16(unsigned int d)
  127. {
  128. // this diff must be at most 16 for NBA Jam to work
  129. if (SekCyclesDoneT() - last_write < 16) {
  130. // just update pending state
  131. elprintf(EL_EEPROM, "eeprom: skip because cycles=%i",
  132. SekCyclesDoneT() - last_write);
  133. EEPROM_upd_pending(d);
  134. } else {
  135. int srs = Pico.m.eeprom_status;
  136. EEPROM_write_do(srs >> 6); // execute pending
  137. EEPROM_upd_pending(d);
  138. if ((srs ^ Pico.m.eeprom_status) & 0xc0) // update time only if SDA/SCL changed
  139. last_write = SekCyclesDoneT();
  140. }
  141. }
  142. void EEPROM_write8(unsigned int a, unsigned int d)
  143. {
  144. unsigned char *wb = Pico.m.eeprom_wb;
  145. wb[a & 1] = d;
  146. EEPROM_write16((wb[0] << 8) | wb[1]);
  147. }
  148. unsigned int EEPROM_read(void)
  149. {
  150. unsigned int shift, d;
  151. unsigned int sreg, saddr, scyc, ssa, interval;
  152. // flush last pending write
  153. EEPROM_write_do(Pico.m.eeprom_status>>6);
  154. sreg = Pico.m.eeprom_status; saddr = Pico.m.eeprom_addr&0x1fff; scyc = Pico.m.eeprom_cycle; ssa = Pico.m.eeprom_slave;
  155. interval = SekCyclesDoneT() - last_write;
  156. d = (sreg>>6)&1; // use SDA as "open bus"
  157. // NBA Jam is nasty enough to read <before> raising the SCL and starting the new cycle.
  158. // this is probably valid because data changes occur while SCL is low and data can be read
  159. // before it's actual cycle begins.
  160. if (!(sreg&0x80) && interval >= 24) {
  161. elprintf(EL_EEPROM, "eeprom: early read, cycles=%i", interval);
  162. scyc++;
  163. }
  164. if (!(sreg & 8)); // not started, use open bus
  165. else if (scyc == 9 || scyc == 18 || scyc == 27) {
  166. elprintf(EL_EEPROM, "eeprom: r ack");
  167. d = 0;
  168. } else if (scyc > 9 && scyc < 18) {
  169. // started and first command word received
  170. shift = 17-scyc;
  171. if (SRam.eeprom_type) {
  172. // X24C02+
  173. if (ssa&1) {
  174. elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);
  175. if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr]);
  176. d = (SRam.data[saddr]>>shift)&1;
  177. }
  178. } else {
  179. // X24C01
  180. if (saddr&1) {
  181. elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr>>1, scyc, sreg);
  182. if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr>>1]);
  183. d = (SRam.data[saddr>>1]>>shift)&1;
  184. }
  185. }
  186. }
  187. return (d << SRam.eeprom_bit_out);
  188. }