ssp16.c 34 KB

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  1. // basic, incomplete SSP160x (SSP1601?) interpreter
  2. // with SVP memory controller emu
  3. // (c) Copyright 2008, Grazvydas "notaz" Ignotas
  4. // Free for non-commercial use.
  5. // For commercial use, separate licencing terms must be obtained.
  6. //#define USE_DEBUGGER
  7. /* detect ops with unimplemented/invalid fields.
  8. * Useful for homebrew or if a new VR revision pops up. */
  9. //#define DO_CHECKS
  10. /*
  11. * Register info
  12. *
  13. * 0. "-"
  14. * size: 16
  15. * desc: Constant register with all bits set (0xffff).
  16. *
  17. * 1. "X"
  18. * size: 16
  19. * desc: Generic register. When set, updates P (P = X * Y * 2)
  20. *
  21. * 2. "Y"
  22. * size: 16
  23. * desc: Generic register. When set, updates P (P = X * Y * 2)
  24. *
  25. * 3. "A"
  26. * size: 32
  27. * desc: Accumulator.
  28. *
  29. * 4. "ST"
  30. * size: 16
  31. * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
  32. * fedc ba98 7654 3210
  33. * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
  34. * modulo-increment and modulo-decrement. The value shows which
  35. * power of 2 to use, i.e. 4 means modulo by 16.
  36. * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
  37. * 43 - RB (?)
  38. * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
  39. * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
  40. * datasheet says these (5,6) bits correspond to hardware pins.
  41. * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
  42. * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
  43. * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
  44. * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
  45. * a - GPI_0 Interrupt 0 enable/status?
  46. * b - GPI_1 Interrupt 1 enable/status?
  47. * c - L L flag. Carry?
  48. * d - Z Zero flag.
  49. * e - OV Overflow flag.
  50. * f - N Negative flag.
  51. * seen directly changing code sequences:
  52. * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
  53. * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
  54. * ld ST, A ld ST, A ori 3
  55. * ld ST, A
  56. *
  57. * 5. "STACK"
  58. * size: 16
  59. * desc: hw stack of 6 levels (according to datasheet)
  60. *
  61. * 6. "PC"
  62. * size: 16
  63. * desc: Program counter.
  64. *
  65. * 7. "P"
  66. * size: 32
  67. * desc: multiply result register. P = X * Y * 2
  68. * probably affected by MACS bit in ST.
  69. *
  70. * 8. "PM0" (PM from PMAR name from Tasco's docs)
  71. * size: 16?
  72. * desc: Programmable Memory access register.
  73. * On reset, or when one (both?) GP0 bits are clear,
  74. * acts as status for XST, mapped at 015004 at 68k side:
  75. * bit0: ssp has written something to XST (cleared when 015004 is read)
  76. * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read)
  77. *
  78. * 9. "PM1"
  79. * size: 16?
  80. * desc: Programmable Memory access register.
  81. * This reg. is only used as PMAR.
  82. *
  83. * 10. "PM2"
  84. * size: 16?
  85. * desc: Programmable Memory access register.
  86. * This reg. is only used as PMAR.
  87. *
  88. * 11. "XST"
  89. * size: 16?
  90. * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side.
  91. * Can be programmed as PMAR? (only seen in test mode code)
  92. * Affects PM0 when written to?
  93. *
  94. * 12. "PM4"
  95. * size: 16?
  96. * desc: Programmable Memory access register.
  97. * This reg. is only used as PMAR. The most used PMAR by VR.
  98. *
  99. * 13. (unused by VR)
  100. *
  101. * 14. "PMC" (PMC from PMAC name from Tasco's docs)
  102. * size: 32?
  103. * desc: Programmable Memory access Control. Set using 2 16bit writes,
  104. * first address, then mode word. After setting PMAC, PMAR sould
  105. * be blind accessed (ld -, PMx or ld PMx, -) to program it for
  106. * reading and writing respectively.
  107. * Reading the register also shifts it's state (from "waiting for
  108. * address" to "waiting for mode" and back). Reads always return
  109. * address related to last PMx register accressed.
  110. * (note: addresses do not wrap).
  111. *
  112. * 15. "AL"
  113. * size: 16
  114. * desc: Accumulator Low. 16 least significant bits of accumulator.
  115. * (normally reading acc (ld X, A) you get 16 most significant bits).
  116. *
  117. *
  118. * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
  119. * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
  120. * which work similar to * and ** operators in C, only they use different memory banks and
  121. * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
  122. * program memory at address read from (rX), and increments value in (rX).
  123. *
  124. * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
  125. * 3 modifiers can be applied (optional):
  126. * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
  127. * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
  128. * +!: post-increment, unaffected by RPL (probably).
  129. * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
  130. * ar probably invalid.
  131. *
  132. * r3 and r7 are special and can not be changed (at least Samsung samples and VR code never do).
  133. * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
  134. * Samsung's old DSP page claims that).
  135. * 1 of these 4 modifiers must be used (short form direct addressing?):
  136. * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
  137. * |01: RAMx[1]
  138. * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
  139. * |11: RAMx[3]
  140. *
  141. *
  142. * Instruction notes
  143. *
  144. * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
  145. *
  146. * mld (rj), (ri) [, b]
  147. * operation: A = 0; P = (rj) * (ri)
  148. * notes: based on IIR_4B.SC sample. flags? what is b???
  149. *
  150. * mpya (rj), (ri) [, b]
  151. * name: multiply and add?
  152. * operation: A += P; P = (rj) * (ri)
  153. *
  154. * mpys (rj), (ri), b
  155. * name: multiply and subtract?
  156. * notes: not used by VR code.
  157. *
  158. * mod cond, op
  159. * mod cond, shr does arithmetic shift
  160. *
  161. * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns
  162. *
  163. * memory map:
  164. * 000000 - 1fffff ROM, accessable by both
  165. * 200000 - 2fffff unused?
  166. * 300000 - 31ffff DRAM, both
  167. * 320000 - 38ffff unused?
  168. * 390000 - 3907ff IRAM. can only be accessed by ssp?
  169. * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only?
  170. * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different
  171. *
  172. * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
  173. * 30fe06 - also sync related.
  174. * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by VR.
  175. *
  176. * Assumptions and limitations in this code
  177. * only Z and N status flags are emulated (others unused by VR)
  178. * so all condition checks except N and Z are ignored (not used by VR)
  179. * modifiers for 'OP a, ri' and ((ri)) are ignored (not used by VR)
  180. * loop repeat mode when (ri) is destination is ignored
  181. * ops not used by VR are not implemented
  182. */
  183. #include "../../pico_int.h"
  184. #define u32 unsigned int
  185. // 0
  186. #define rX ssp->gr[SSP_X].h
  187. #define rY ssp->gr[SSP_Y].h
  188. #define rA ssp->gr[SSP_A].h
  189. #define rST ssp->gr[SSP_ST].h // 4
  190. #define rSTACK ssp->gr[SSP_STACK].h
  191. #define rPC ssp->gr[SSP_PC].h
  192. #define rP ssp->gr[SSP_P]
  193. #define rPM0 ssp->gr[SSP_PM0].h // 8
  194. #define rPM1 ssp->gr[SSP_PM1].h
  195. #define rPM2 ssp->gr[SSP_PM2].h
  196. #define rXST ssp->gr[SSP_XST].h
  197. #define rPM4 ssp->gr[SSP_PM4].h // 12
  198. // 13
  199. #define rPMC ssp->gr[SSP_PMC] // will keep addr in .l, mode in .h
  200. #define rAL ssp->gr[SSP_A].l
  201. #define rA32 ssp->gr[SSP_A].v
  202. #define rIJ ssp->r
  203. #define IJind (((op>>6)&4)|(op&3))
  204. #define GET_PC() (PC - (unsigned short *)svp->iram_rom)
  205. #define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
  206. #define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
  207. #define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
  208. #define REG_WRITE(r,d) { \
  209. int r1 = r; \
  210. if (r1 >= 4) write_handlers[r1](d); \
  211. else if (r1 > 0) ssp->gr[r1].h = d; \
  212. }
  213. // flags
  214. #define SSP_FLAG_L (1<<0xc)
  215. #define SSP_FLAG_Z (1<<0xd)
  216. #define SSP_FLAG_V (1<<0xe)
  217. #define SSP_FLAG_N (1<<0xf)
  218. // update ZN according to 32bit ACC.
  219. #define UPD_ACC_ZN \
  220. rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
  221. if (!rA32) rST |= SSP_FLAG_Z; \
  222. else rST |= (rA32>>16)&SSP_FLAG_N;
  223. // it seems SVP code never checks for L and OV, so we leave them out.
  224. // rST |= (t>>4)&SSP_FLAG_L;
  225. #define UPD_LZVN \
  226. rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
  227. if (!rA32) rST |= SSP_FLAG_Z; \
  228. else rST |= (rA32>>16)&SSP_FLAG_N;
  229. // standard cond processing.
  230. // again, only Z and N is checked, as VR doesn't seem to use any other conds.
  231. #define COND_CHECK \
  232. switch (op&0xf0) { \
  233. case 0x00: cond = 1; break; /* always true */ \
  234. case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
  235. case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
  236. default:elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
  237. }
  238. // ops with accumulator.
  239. // how is low word really affected by these?
  240. // nearly sure 'ld A' doesn't affect flags
  241. #define OP_LDA(x) \
  242. ssp->gr[SSP_A].h = x
  243. #define OP_LDA32(x) \
  244. rA32 = x
  245. #define OP_SUBA(x) { \
  246. rA32 -= (x) << 16; \
  247. UPD_LZVN \
  248. }
  249. #define OP_SUBA32(x) { \
  250. rA32 -= (x); \
  251. UPD_LZVN \
  252. }
  253. #define OP_CMPA(x) { \
  254. u32 t = rA32 - ((x) << 16); \
  255. rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
  256. if (!t) rST |= SSP_FLAG_Z; \
  257. else rST |= (t>>16)&SSP_FLAG_N; \
  258. }
  259. #define OP_CMPA32(x) { \
  260. u32 t = rA32 - (x); \
  261. rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
  262. if (!t) rST |= SSP_FLAG_Z; \
  263. else rST |= (t>>16)&SSP_FLAG_N; \
  264. }
  265. #define OP_ADDA(x) { \
  266. rA32 += (x) << 16; \
  267. UPD_LZVN \
  268. }
  269. #define OP_ADDA32(x) { \
  270. rA32 += (x); \
  271. UPD_LZVN \
  272. }
  273. #define OP_ANDA(x) \
  274. rA32 &= (x) << 16; \
  275. UPD_ACC_ZN
  276. #define OP_ANDA32(x) \
  277. rA32 &= (x); \
  278. UPD_ACC_ZN
  279. #define OP_ORA(x) \
  280. rA32 |= (x) << 16; \
  281. UPD_ACC_ZN
  282. #define OP_ORA32(x) \
  283. rA32 |= (x); \
  284. UPD_ACC_ZN
  285. #define OP_EORA(x) \
  286. rA32 ^= (x) << 16; \
  287. UPD_ACC_ZN
  288. #define OP_EORA32(x) \
  289. rA32 ^= (x); \
  290. UPD_ACC_ZN
  291. #define OP_CHECK32(OP) { \
  292. if ((op & 0x0f) == SSP_P) { /* A <- P */ \
  293. read_P(); /* update P */ \
  294. OP(rP.v); \
  295. break; \
  296. } \
  297. if ((op & 0x0f) == SSP_A) { /* A <- A */ \
  298. OP(rA32); \
  299. break; \
  300. } \
  301. }
  302. #ifdef DO_CHECKS
  303. #define CHECK_IMM16() if (op&0x1ff) elprintf(EL_ANOMALY, "imm bits! %04x @ %04x", op, GET_PPC_OFFS())
  304. #define CHECK_B_SET() if (op&0x100) elprintf(EL_ANOMALY, "b set! %04x @ %04x", op, GET_PPC_OFFS())
  305. #define CHECK_B_CLEAR() if (!(op&0x100)) elprintf(EL_ANOMALY, "b clear! %04x @ %04x", op, GET_PPC_OFFS())
  306. #define CHECK_MOD() if (op&0x00c) elprintf(EL_ANOMALY, "mod bits! %04x @ %04x", op, GET_PPC_OFFS())
  307. #define CHECK_10f() if (op&0x10f) elprintf(EL_ANOMALY, "bits 10f! %04x @ %04x", op, GET_PPC_OFFS())
  308. #define CHECK_008() if (op&0x008) elprintf(EL_ANOMALY, "bits 008! %04x @ %04x", op, GET_PPC_OFFS())
  309. #define CHECK_00f() if (op&0x00f) elprintf(EL_ANOMALY, "bits 00f! %04x @ %04x", op, GET_PPC_OFFS())
  310. #define CHECK_0f0() if (op&0x0f0) elprintf(EL_ANOMALY, "bits 0f0! %04x @ %04x", op, GET_PPC_OFFS())
  311. #define CHECK_1f0() if (op&0x1f0) elprintf(EL_ANOMALY, "bits 1f0! %04x @ %04x", op, GET_PPC_OFFS())
  312. #define CHECK_RPL() if (rST&7) elprintf(EL_ANOMALY, "unhandled RPL! %04x @ %04x", op, GET_PPC_OFFS())
  313. #define CHECK_ST(d) if((rST^d)&0xf98)elprintf(EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS())
  314. #else
  315. #define CHECK_IMM16()
  316. #define CHECK_B_SET()
  317. #define CHECK_B_CLEAR()
  318. #define CHECK_MOD()
  319. #define CHECK_10f()
  320. #define CHECK_008()
  321. #define CHECK_00f()
  322. #define CHECK_0f0()
  323. #define CHECK_1f0()
  324. #define CHECK_RPL()
  325. #define CHECK_ST(d)
  326. #endif
  327. ssp1601_t *ssp = NULL;
  328. static unsigned short *PC;
  329. static int g_cycles;
  330. #ifdef USE_DEBUGGER
  331. static int running = 0;
  332. static int last_iram = 0;
  333. #endif
  334. // -----------------------------------------------------
  335. // register i/o handlers
  336. // 0-4, 13
  337. static u32 read_unknown(void)
  338. {
  339. elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS());
  340. return 0;
  341. }
  342. static void write_unknown(u32 d)
  343. {
  344. elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS());
  345. }
  346. // 4
  347. static void write_ST(u32 d)
  348. {
  349. CHECK_ST(d);
  350. rST = d;
  351. }
  352. // 5
  353. static u32 read_STACK(void)
  354. {
  355. --rSTACK;
  356. if ((short)rSTACK < 0) {
  357. rSTACK = 5;
  358. elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
  359. }
  360. return ssp->stack[rSTACK];
  361. }
  362. static void write_STACK(u32 d)
  363. {
  364. if (rSTACK >= 6) {
  365. elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
  366. rSTACK = 0;
  367. }
  368. ssp->stack[rSTACK++] = d;
  369. }
  370. // 6
  371. static u32 read_PC(void)
  372. {
  373. return GET_PC();
  374. }
  375. static void write_PC(u32 d)
  376. {
  377. SET_PC(d);
  378. g_cycles--;
  379. }
  380. // 7
  381. static u32 read_P(void)
  382. {
  383. int m1 = (signed short)rX;
  384. int m2 = (signed short)rY;
  385. rP.v = (m1 * m2 * 2);
  386. return rP.h;
  387. }
  388. // -----------------------------------------------------
  389. static int get_inc(int mode)
  390. {
  391. int inc = (mode >> 11) & 7;
  392. if (inc != 0) {
  393. if (inc != 7) inc--;
  394. inc = 1 << inc; // 0 1 2 4 8 16 32 128
  395. if (mode & 0x8000) inc = -inc; // decrement mode
  396. }
  397. return inc;
  398. }
  399. #define overwrite_write(dst, d) \
  400. { \
  401. if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
  402. if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
  403. if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
  404. if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
  405. }
  406. static u32 pm_io(int reg, int write, u32 d)
  407. {
  408. if (ssp->emu_status & SSP_PMC_SET)
  409. {
  410. // this MUST be blind r or w
  411. if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
  412. elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
  413. reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
  414. ssp->emu_status &= ~SSP_PMC_SET;
  415. return 0;
  416. }
  417. elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
  418. ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
  419. ssp->emu_status &= ~SSP_PMC_SET;
  420. if ((rPMC.v & 0x7fffff) == 0x1c8000 || (rPMC.v & 0x7fffff) == 0x1c8240) {
  421. elprintf(EL_SVP, "ssp IRAM copy from %06x to %04x", (ssp->RAM1[0]-1)<<1, (rPMC.v&0x7fff)<<1);
  422. #ifdef USE_DEBUGGER
  423. last_iram = (ssp->RAM1[0]-1)<<1;
  424. #endif
  425. }
  426. return 0;
  427. }
  428. // just in case
  429. if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
  430. elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x",
  431. reg, write ? 'w' : 'r', GET_PPC_OFFS());
  432. ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
  433. }
  434. if (reg == 4 || (rST & 0x60))
  435. {
  436. #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
  437. unsigned short *dram = (unsigned short *)svp->dram;
  438. if (write)
  439. {
  440. int mode = ssp->pmac_write[reg]>>16;
  441. int addr = ssp->pmac_write[reg]&0xffff;
  442. if ((mode & 0xb800) == 0xb800)
  443. elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: mode %04x", mode);
  444. if ((mode & 0x43ff) == 0x0018) // DRAM
  445. {
  446. int inc = get_inc(mode);
  447. elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
  448. reg, CADDR, d, inc, (mode>>10)&1);
  449. if (mode & 0x0400) {
  450. overwrite_write(dram[addr], d);
  451. } else dram[addr] = d;
  452. ssp->pmac_write[reg] += inc;
  453. }
  454. else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
  455. {
  456. elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
  457. reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
  458. if (mode & 0x0400) {
  459. overwrite_write(dram[addr], d);
  460. } else dram[addr] = d;
  461. ssp->pmac_write[reg] += (addr&1) ? 31 : 1;
  462. }
  463. else if ((mode & 0x47ff) == 0x001c) // IRAM
  464. {
  465. int inc = get_inc(mode);
  466. if ((addr&0xfc00) != 0x8000)
  467. elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
  468. elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
  469. ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
  470. ssp->pmac_write[reg] += inc;
  471. }
  472. else
  473. {
  474. elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
  475. reg, mode, CADDR, d, GET_PPC_OFFS());
  476. }
  477. }
  478. else
  479. {
  480. int mode = ssp->pmac_read[reg]>>16;
  481. int addr = ssp->pmac_read[reg]&0xffff;
  482. if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct
  483. {
  484. elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
  485. ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
  486. ssp->pmac_read[reg] += 1;
  487. d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
  488. }
  489. else if ((mode & 0x47ff) == 0x0018) // DRAM
  490. {
  491. int inc = get_inc(mode);
  492. elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr]);
  493. d = dram[addr];
  494. ssp->pmac_read[reg] += inc;
  495. }
  496. else
  497. {
  498. elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x",
  499. reg, mode, CADDR, GET_PPC_OFFS());
  500. d = 0;
  501. }
  502. }
  503. // PMC value corresponds to last PMR accessed (not sure).
  504. rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
  505. return d;
  506. }
  507. return (u32)-1;
  508. }
  509. // 8
  510. static u32 read_PM0(void)
  511. {
  512. u32 d = pm_io(0, 0, 0);
  513. if (d != (u32)-1) return d;
  514. elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
  515. d = rPM0;
  516. if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
  517. ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
  518. }
  519. rPM0 &= ~2; // ?
  520. return d;
  521. }
  522. static void write_PM0(u32 d)
  523. {
  524. u32 r = pm_io(0, 1, d);
  525. if (r != (u32)-1) return;
  526. elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
  527. rPM0 = d;
  528. }
  529. // 9
  530. static u32 read_PM1(void)
  531. {
  532. u32 d = pm_io(1, 0, 0);
  533. if (d != (u32)-1) return d;
  534. // can be removed?
  535. elprintf(EL_SVP|EL_ANOMALY, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
  536. return rPM1;
  537. }
  538. static void write_PM1(u32 d)
  539. {
  540. u32 r = pm_io(1, 1, d);
  541. if (r != (u32)-1) return;
  542. // can be removed?
  543. elprintf(EL_SVP|EL_ANOMALY, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
  544. rPM1 = d;
  545. }
  546. // 10
  547. static u32 read_PM2(void)
  548. {
  549. u32 d = pm_io(2, 0, 0);
  550. if (d != (u32)-1) return d;
  551. // can be removed?
  552. elprintf(EL_SVP|EL_ANOMALY, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
  553. return rPM2;
  554. }
  555. static void write_PM2(u32 d)
  556. {
  557. u32 r = pm_io(2, 1, d);
  558. if (r != (u32)-1) return;
  559. // can be removed?
  560. elprintf(EL_SVP|EL_ANOMALY, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
  561. rPM2 = d;
  562. }
  563. // 11
  564. static u32 read_XST(void)
  565. {
  566. // can be removed?
  567. u32 d = pm_io(3, 0, 0);
  568. if (d != (u32)-1) return d;
  569. elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
  570. return rXST;
  571. }
  572. static void write_XST(u32 d)
  573. {
  574. // can be removed?
  575. u32 r = pm_io(3, 1, d);
  576. if (r != (u32)-1) return;
  577. elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
  578. rPM0 |= 1;
  579. rXST = d;
  580. }
  581. // 12
  582. static u32 read_PM4(void)
  583. {
  584. u32 d = pm_io(4, 0, 0);
  585. /* TODO?
  586. if (d == 0) {
  587. switch (GET_PPC_OFFS()) {
  588. case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
  589. case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
  590. }
  591. }
  592. */
  593. if (d != (u32)-1) return d;
  594. // can be removed?
  595. elprintf(EL_SVP|EL_ANOMALY, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
  596. return rPM4;
  597. }
  598. static void write_PM4(u32 d)
  599. {
  600. u32 r = pm_io(4, 1, d);
  601. if (r != (u32)-1) return;
  602. // can be removed?
  603. elprintf(EL_SVP|EL_ANOMALY, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
  604. rPM4 = d;
  605. }
  606. // 14
  607. static u32 read_PMC(void)
  608. {
  609. elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.l,
  610. (ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS());
  611. if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
  612. //if (ssp->emu_status & SSP_PMC_SET)
  613. // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
  614. ssp->emu_status |= SSP_PMC_SET;
  615. ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
  616. return ((rPMC.l << 4) & 0xfff0) | ((rPMC.l >> 4) & 0xf);
  617. } else {
  618. ssp->emu_status |= SSP_PMC_HAVE_ADDR;
  619. return rPMC.l;
  620. }
  621. }
  622. static void write_PMC(u32 d)
  623. {
  624. if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
  625. //if (ssp->emu_status & SSP_PMC_SET)
  626. // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
  627. ssp->emu_status |= SSP_PMC_SET;
  628. ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
  629. rPMC.h = d;
  630. elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.h, GET_PPC_OFFS());
  631. } else {
  632. ssp->emu_status |= SSP_PMC_HAVE_ADDR;
  633. rPMC.l = d;
  634. elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.l, GET_PPC_OFFS());
  635. }
  636. }
  637. // 15
  638. static u32 read_AL(void)
  639. {
  640. if (*(PC-1) == 0x000f)
  641. elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
  642. ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
  643. return rAL;
  644. }
  645. static void write_AL(u32 d)
  646. {
  647. rAL = d;
  648. }
  649. typedef u32 (*read_func_t)(void);
  650. typedef void (*write_func_t)(u32 d);
  651. static read_func_t read_handlers[16] =
  652. {
  653. read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
  654. read_unknown, // 4 ST
  655. read_STACK,
  656. read_PC,
  657. read_P,
  658. read_PM0, // 8
  659. read_PM1,
  660. read_PM2,
  661. read_XST,
  662. read_PM4, // 12
  663. read_unknown, // 13 gr13
  664. read_PMC,
  665. read_AL
  666. };
  667. static write_func_t write_handlers[16] =
  668. {
  669. write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
  670. // write_unknown, // 4 ST
  671. write_ST, // 4 ST (debug hook)
  672. write_STACK,
  673. write_PC,
  674. write_unknown, // 7 P
  675. write_PM0, // 8
  676. write_PM1,
  677. write_PM2,
  678. write_XST,
  679. write_PM4, // 12
  680. write_unknown, // 13 gr13
  681. write_PMC,
  682. write_AL
  683. };
  684. // -----------------------------------------------------
  685. // pointer register handlers
  686. //
  687. #define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
  688. static u32 ptr1_read_(int ri, int isj2, int modi3)
  689. {
  690. //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
  691. u32 mask, add = 0, t = ri | isj2 | modi3;
  692. unsigned char *rp = NULL;
  693. switch (t)
  694. {
  695. // mod=0 (00)
  696. case 0x00:
  697. case 0x01:
  698. case 0x02: return ssp->RAM0[ssp->r0[t&3]];
  699. case 0x03: return ssp->RAM0[0];
  700. case 0x04:
  701. case 0x05:
  702. case 0x06: return ssp->RAM1[ssp->r1[t&3]];
  703. case 0x07: return ssp->RAM1[0];
  704. // mod=1 (01), "+!"
  705. case 0x08:
  706. case 0x09:
  707. case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
  708. case 0x0b: return ssp->RAM0[1];
  709. case 0x0c:
  710. case 0x0d:
  711. case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
  712. case 0x0f: return ssp->RAM1[1];
  713. // mod=2 (10), "-"
  714. case 0x10:
  715. case 0x11:
  716. case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
  717. if (!(rST&7)) { (*rp)--; return t; }
  718. add = -1; goto modulo;
  719. case 0x13: return ssp->RAM0[2];
  720. case 0x14:
  721. case 0x15:
  722. case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
  723. if (!(rST&7)) { (*rp)--; return t; }
  724. add = -1; goto modulo;
  725. case 0x17: return ssp->RAM1[2];
  726. // mod=3 (11), "+"
  727. case 0x18:
  728. case 0x19:
  729. case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
  730. if (!(rST&7)) { (*rp)++; return t; }
  731. add = 1; goto modulo;
  732. case 0x1b: return ssp->RAM0[3];
  733. case 0x1c:
  734. case 0x1d:
  735. case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
  736. if (!(rST&7)) { (*rp)++; return t; }
  737. add = 1; goto modulo;
  738. case 0x1f: return ssp->RAM1[3];
  739. }
  740. return 0;
  741. modulo:
  742. mask = (1 << (rST&7)) - 1;
  743. *rp = (*rp & ~mask) | ((*rp + add) & mask);
  744. return t;
  745. }
  746. static void ptr1_write(int op, u32 d)
  747. {
  748. int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
  749. switch (t)
  750. {
  751. // mod=0 (00)
  752. case 0x00:
  753. case 0x01:
  754. case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
  755. case 0x03: ssp->RAM0[0] = d; return;
  756. case 0x04:
  757. case 0x05:
  758. case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
  759. case 0x07: ssp->RAM1[0] = d; return;
  760. // mod=1 (01), "+!"
  761. // mod=3, "+"
  762. case 0x08:
  763. case 0x09:
  764. case 0x0a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
  765. case 0x0b: ssp->RAM0[1] = d; return;
  766. case 0x0c:
  767. case 0x0d:
  768. case 0x0e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
  769. case 0x0f: ssp->RAM1[1] = d; return;
  770. // mod=2 (10), "-"
  771. case 0x10:
  772. case 0x11:
  773. case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; CHECK_RPL(); return;
  774. case 0x13: ssp->RAM0[2] = d; return;
  775. case 0x14:
  776. case 0x15:
  777. case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; CHECK_RPL(); return;
  778. case 0x17: ssp->RAM1[2] = d; return;
  779. // mod=3 (11), "+"
  780. case 0x18:
  781. case 0x19:
  782. case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; CHECK_RPL(); return;
  783. case 0x1b: ssp->RAM0[3] = d; return;
  784. case 0x1c:
  785. case 0x1d:
  786. case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; CHECK_RPL(); return;
  787. case 0x1f: ssp->RAM1[3] = d; return;
  788. }
  789. }
  790. static u32 ptr2_read(int op)
  791. {
  792. int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
  793. switch (t)
  794. {
  795. // mod=0 (00)
  796. case 0x00:
  797. case 0x01:
  798. case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
  799. case 0x03: mv = ssp->RAM0[0]++; break;
  800. case 0x04:
  801. case 0x05:
  802. case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
  803. case 0x07: mv = ssp->RAM1[0]++; break;
  804. // mod=1 (01)
  805. case 0x0b: mv = ssp->RAM0[1]++; break;
  806. case 0x0f: mv = ssp->RAM1[1]++; break;
  807. // mod=2 (10)
  808. case 0x13: mv = ssp->RAM0[2]++; break;
  809. case 0x17: mv = ssp->RAM1[2]++; break;
  810. // mod=3 (11)
  811. case 0x1b: mv = ssp->RAM0[3]++; break;
  812. case 0x1f: mv = ssp->RAM1[3]++; break;
  813. default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
  814. return 0;
  815. }
  816. return ((unsigned short *)svp->iram_rom)[mv];
  817. }
  818. // -----------------------------------------------------
  819. #if defined(USE_DEBUGGER)
  820. static void debug_dump2file(const char *fname, void *mem, int len)
  821. {
  822. FILE *f = fopen(fname, "wb");
  823. unsigned short *p = mem;
  824. int i;
  825. if (f) {
  826. for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
  827. fwrite(mem, 1, len, f);
  828. fclose(f);
  829. for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
  830. printf("dumped to %s\n", fname);
  831. }
  832. else
  833. printf("dump failed\n");
  834. }
  835. #endif
  836. #ifdef USE_DEBUGGER
  837. static void debug_dump(void)
  838. {
  839. printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
  840. printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, rP.v);
  841. printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
  842. printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, rPMC.v);
  843. printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
  844. rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
  845. printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
  846. ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
  847. printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
  848. elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
  849. }
  850. static void debug_dump_mem(void)
  851. {
  852. int h, i;
  853. printf("RAM0\n");
  854. for (h = 0; h < 32; h++)
  855. {
  856. if (h == 16) printf("RAM1\n");
  857. printf("%03x:", h*16);
  858. for (i = 0; i < 16; i++)
  859. printf(" %04x", ssp->RAM[h*16+i]);
  860. printf("\n");
  861. }
  862. }
  863. static int bpts[10] = { 0, };
  864. static void debug(unsigned int pc, unsigned int op)
  865. {
  866. static char buffo[64] = {0,};
  867. char buff[64] = {0,};
  868. int i;
  869. if (running) {
  870. for (i = 0; i < 10; i++)
  871. if (pc != 0 && bpts[i] == pc) {
  872. printf("breakpoint %i\n", i);
  873. running = 0;
  874. break;
  875. }
  876. }
  877. if (running) return;
  878. printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
  879. while (1)
  880. {
  881. printf("dbg> ");
  882. fflush(stdout);
  883. fgets(buff, sizeof(buff), stdin);
  884. if (buff[0] == '\n') strcpy(buff, buffo);
  885. else strcpy(buffo, buff);
  886. switch (buff[0]) {
  887. case 0: exit(0);
  888. case 'c':
  889. case 'r': running = 1; return;
  890. case 's':
  891. case 'n': return;
  892. case 'x': debug_dump(); break;
  893. case 'm': debug_dump_mem(); break;
  894. case 'b': {
  895. char *baddr = buff + 2;
  896. i = 0;
  897. if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
  898. bpts[i] = strtol(baddr, NULL, 16) >> 1;
  899. printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
  900. break;
  901. }
  902. case 'd':
  903. sprintf(buff, "iramrom_%04x.bin", last_iram);
  904. debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
  905. debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
  906. break;
  907. default: printf("unknown command\n"); break;
  908. }
  909. }
  910. }
  911. #endif // USE_DEBUGGER
  912. void ssp1601_reset(ssp1601_t *l_ssp)
  913. {
  914. ssp = l_ssp;
  915. ssp->emu_status = 0;
  916. ssp->gr[SSP_GR0].v = 0xffff0000;
  917. rPC = 0x400;
  918. rSTACK = 0; // ? using ascending stack
  919. rST = 0;
  920. }
  921. void ssp1601_run(int cycles)
  922. {
  923. SET_PC(rPC);
  924. g_cycles = cycles;
  925. while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
  926. {
  927. int op;
  928. u32 tmpv;
  929. op = *PC++;
  930. #ifdef USE_DEBUGGER
  931. debug(GET_PC()-1, op);
  932. #endif
  933. switch (op >> 9)
  934. {
  935. // ld d, s
  936. case 0x00:
  937. CHECK_B_SET();
  938. if (op == 0) break; // nop
  939. if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
  940. read_P(); // update P
  941. rA32 = rP.v;
  942. }
  943. else
  944. {
  945. tmpv = REG_READ(op & 0x0f);
  946. REG_WRITE((op & 0xf0) >> 4, tmpv);
  947. }
  948. break;
  949. // ld d, (ri)
  950. case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
  951. // ld (ri), s
  952. case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
  953. // ldi d, imm
  954. case 0x04: CHECK_10f(); tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles--; break;
  955. // ld d, ((ri))
  956. case 0x05: CHECK_MOD(); tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles -= 2; break;
  957. // ldi (ri), imm
  958. case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); g_cycles--; break;
  959. // ld adr, a
  960. case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
  961. // ld d, ri
  962. case 0x09: CHECK_MOD(); tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
  963. // ld ri, s
  964. case 0x0a: CHECK_MOD(); rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
  965. // ldi ri, simm
  966. case 0x0c:
  967. case 0x0d:
  968. case 0x0e:
  969. case 0x0f: rIJ[(op>>8)&7] = op; break;
  970. // call cond, addr
  971. case 0x24: {
  972. int cond = 0;
  973. CHECK_00f();
  974. COND_CHECK
  975. if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); SET_PC(new_PC); }
  976. else PC++;
  977. g_cycles--; // always 2 cycles
  978. break;
  979. }
  980. // ld d, (a)
  981. case 0x25:
  982. CHECK_10f();
  983. tmpv = ((unsigned short *)svp->iram_rom)[rA];
  984. REG_WRITE((op & 0xf0) >> 4, tmpv);
  985. g_cycles -= 2; // 3 cycles total
  986. break;
  987. // bra cond, addr
  988. case 0x26: {
  989. int cond = 0;
  990. CHECK_00f();
  991. COND_CHECK
  992. if (cond) { int new_PC = *PC++; SET_PC(new_PC); }
  993. else PC++;
  994. g_cycles--;
  995. break;
  996. }
  997. // mod cond, op
  998. case 0x48: {
  999. int cond = 0;
  1000. CHECK_008();
  1001. COND_CHECK
  1002. if (cond) {
  1003. switch (op & 7) {
  1004. case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
  1005. case 3: rA32 <<= 1; break; // shl
  1006. case 6: rA32 = -(signed int)rA32; break; // neg
  1007. case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
  1008. default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
  1009. op&7, GET_PPC_OFFS());
  1010. }
  1011. UPD_ACC_ZN
  1012. }
  1013. break;
  1014. }
  1015. // mpys?
  1016. case 0x1b:
  1017. CHECK_B_CLEAR();
  1018. read_P(); // update P
  1019. rA32 -= rP.v;
  1020. UPD_ACC_ZN
  1021. rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
  1022. rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
  1023. break;
  1024. // mpya (rj), (ri), b
  1025. case 0x4b:
  1026. CHECK_B_CLEAR();
  1027. read_P(); // update P
  1028. rA32 += rP.v;
  1029. UPD_ACC_ZN
  1030. rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
  1031. rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
  1032. break;
  1033. // mld (rj), (ri), b
  1034. case 0x5b:
  1035. CHECK_B_CLEAR();
  1036. rA32 = 0;
  1037. rST &= 0x0fff;
  1038. rST |= SSP_FLAG_Z;
  1039. rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
  1040. rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
  1041. break;
  1042. // OP a, s
  1043. case 0x10: CHECK_1f0(); OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
  1044. case 0x30: CHECK_1f0(); OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
  1045. case 0x40: CHECK_1f0(); OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
  1046. case 0x50: CHECK_1f0(); OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
  1047. case 0x60: CHECK_1f0(); OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
  1048. case 0x70: CHECK_1f0(); OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
  1049. // OP a, (ri)
  1050. case 0x11: CHECK_0f0(); tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
  1051. case 0x31: CHECK_0f0(); tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
  1052. case 0x41: CHECK_0f0(); tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
  1053. case 0x51: CHECK_0f0(); tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
  1054. case 0x61: CHECK_0f0(); tmpv = ptr1_read(op); OP_ORA (tmpv); break;
  1055. case 0x71: CHECK_0f0(); tmpv = ptr1_read(op); OP_EORA(tmpv); break;
  1056. // OP a, adr
  1057. case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
  1058. case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
  1059. case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
  1060. case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
  1061. case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
  1062. case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
  1063. case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
  1064. // OP a, imm
  1065. case 0x14: CHECK_IMM16(); tmpv = *PC++; OP_SUBA(tmpv); g_cycles--; break;
  1066. case 0x34: CHECK_IMM16(); tmpv = *PC++; OP_CMPA(tmpv); g_cycles--; break;
  1067. case 0x44: CHECK_IMM16(); tmpv = *PC++; OP_ADDA(tmpv); g_cycles--; break;
  1068. case 0x54: CHECK_IMM16(); tmpv = *PC++; OP_ANDA(tmpv); g_cycles--; break;
  1069. case 0x64: CHECK_IMM16(); tmpv = *PC++; OP_ORA (tmpv); g_cycles--; break;
  1070. case 0x74: CHECK_IMM16(); tmpv = *PC++; OP_EORA(tmpv); g_cycles--; break;
  1071. // OP a, ((ri))
  1072. case 0x15: CHECK_MOD(); tmpv = ptr2_read(op); OP_SUBA(tmpv); g_cycles -= 2; break;
  1073. case 0x35: CHECK_MOD(); tmpv = ptr2_read(op); OP_CMPA(tmpv); g_cycles -= 2; break;
  1074. case 0x45: CHECK_MOD(); tmpv = ptr2_read(op); OP_ADDA(tmpv); g_cycles -= 2; break;
  1075. case 0x55: CHECK_MOD(); tmpv = ptr2_read(op); OP_ANDA(tmpv); g_cycles -= 2; break;
  1076. case 0x65: CHECK_MOD(); tmpv = ptr2_read(op); OP_ORA (tmpv); g_cycles -= 2; break;
  1077. case 0x75: CHECK_MOD(); tmpv = ptr2_read(op); OP_EORA(tmpv); g_cycles -= 2; break;
  1078. // OP a, ri
  1079. case 0x19: CHECK_MOD(); tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
  1080. case 0x39: CHECK_MOD(); tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
  1081. case 0x49: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
  1082. case 0x59: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
  1083. case 0x69: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
  1084. case 0x79: CHECK_MOD(); tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
  1085. // OP simm
  1086. case 0x1c: CHECK_B_SET(); OP_SUBA(op & 0xff); break;
  1087. case 0x3c: CHECK_B_SET(); OP_CMPA(op & 0xff); break;
  1088. case 0x4c: CHECK_B_SET(); OP_ADDA(op & 0xff); break;
  1089. case 0x5c: CHECK_B_SET(); OP_ANDA(op & 0xff); break;
  1090. case 0x6c: CHECK_B_SET(); OP_ORA (op & 0xff); break;
  1091. case 0x7c: CHECK_B_SET(); OP_EORA(op & 0xff); break;
  1092. default:
  1093. elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
  1094. break;
  1095. }
  1096. g_cycles--;
  1097. }
  1098. rPC = GET_PC();
  1099. read_P(); // update P
  1100. }