carthw.c 24 KB

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  1. /*
  2. * Support for a few cart mappers and some protection.
  3. * (C) notaz, 2008-2011
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. */
  8. #include "../pico_int.h"
  9. #include "../memory.h"
  10. #include "eeprom_spi.h"
  11. static int have_bank(u32 base)
  12. {
  13. // the loader allocs in 512K quantities
  14. if (base >= Pico.romsize) {
  15. elprintf(EL_ANOMALY|EL_STATUS, "carthw: missing bank @ %06x", base);
  16. return 0;
  17. }
  18. return 1;
  19. }
  20. /* standard/ssf2 mapper */
  21. int carthw_ssf2_active;
  22. unsigned char carthw_ssf2_banks[8];
  23. static carthw_state_chunk carthw_ssf2_state[] =
  24. {
  25. { CHUNK_CARTHW, sizeof(carthw_ssf2_banks), &carthw_ssf2_banks },
  26. { 0, 0, NULL }
  27. };
  28. void carthw_ssf2_write8(u32 a, u32 d)
  29. {
  30. u32 target, base;
  31. if ((a & ~0x0e) != 0xa130f1 || a == 0xa130f1) {
  32. PicoWrite8_io(a, d);
  33. return;
  34. }
  35. a &= 0x0e;
  36. if (a == 0)
  37. return;
  38. if (carthw_ssf2_banks[a >> 1] == d)
  39. return;
  40. base = d << 19;
  41. target = a << 18;
  42. if (!have_bank(base))
  43. return;
  44. carthw_ssf2_banks[a >> 1] = d;
  45. cpu68k_map_set(m68k_read8_map, target, target + 0x80000 - 1, Pico.rom + base, 0);
  46. cpu68k_map_set(m68k_read16_map, target, target + 0x80000 - 1, Pico.rom + base, 0);
  47. }
  48. void carthw_ssf2_write16(u32 a, u32 d)
  49. {
  50. PicoWrite16_io(a, d);
  51. if ((a & ~0x0f) == 0xa130f0)
  52. carthw_ssf2_write8(a + 1, d);
  53. }
  54. static void carthw_ssf2_mem_setup(void)
  55. {
  56. cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, carthw_ssf2_write8, 1);
  57. cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, carthw_ssf2_write16, 1);
  58. }
  59. static void carthw_ssf2_statef(void)
  60. {
  61. int i, reg;
  62. for (i = 1; i < 8; i++) {
  63. reg = carthw_ssf2_banks[i];
  64. carthw_ssf2_banks[i] = i;
  65. carthw_ssf2_write8(0xa130f1 | (i << 1), reg);
  66. }
  67. }
  68. static void carthw_ssf2_unload(void)
  69. {
  70. memset(carthw_ssf2_banks, 0, sizeof(carthw_ssf2_banks));
  71. carthw_ssf2_active = 0;
  72. }
  73. void carthw_ssf2_startup(void)
  74. {
  75. int i;
  76. elprintf(EL_STATUS, "SSF2 mapper startup");
  77. // default map
  78. for (i = 0; i < 8; i++)
  79. carthw_ssf2_banks[i] = i;
  80. PicoCartMemSetup = carthw_ssf2_mem_setup;
  81. PicoLoadStateHook = carthw_ssf2_statef;
  82. PicoCartUnloadHook = carthw_ssf2_unload;
  83. carthw_chunks = carthw_ssf2_state;
  84. carthw_ssf2_active = 1;
  85. }
  86. /* Common *-in-1 pirate mapper.
  87. * Switches banks based on addr lines when /TIME is set.
  88. * TODO: verify
  89. */
  90. static unsigned int carthw_Xin1_baddr = 0;
  91. static void carthw_Xin1_do(u32 a, int mask, int shift)
  92. {
  93. int len;
  94. carthw_Xin1_baddr = a;
  95. a &= mask;
  96. a <<= shift;
  97. len = Pico.romsize - a;
  98. if (len <= 0) {
  99. elprintf(EL_ANOMALY|EL_STATUS, "X-in-1: missing bank @ %06x", a);
  100. return;
  101. }
  102. len = (len + M68K_BANK_MASK) & ~M68K_BANK_MASK;
  103. cpu68k_map_set(m68k_read8_map, 0x000000, len - 1, Pico.rom + a, 0);
  104. cpu68k_map_set(m68k_read16_map, 0x000000, len - 1, Pico.rom + a, 0);
  105. }
  106. static carthw_state_chunk carthw_Xin1_state[] =
  107. {
  108. { CHUNK_CARTHW, sizeof(carthw_Xin1_baddr), &carthw_Xin1_baddr },
  109. { 0, 0, NULL }
  110. };
  111. // TODO: test a0, reads, w16
  112. static void carthw_Xin1_write8(u32 a, u32 d)
  113. {
  114. if ((a & 0xffff00) != 0xa13000) {
  115. PicoWrite8_io(a, d);
  116. return;
  117. }
  118. carthw_Xin1_do(a, 0x3f, 16);
  119. }
  120. static void carthw_Xin1_mem_setup(void)
  121. {
  122. cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, carthw_Xin1_write8, 1);
  123. }
  124. static void carthw_Xin1_reset(void)
  125. {
  126. carthw_Xin1_write8(0xa13000, 0);
  127. }
  128. static void carthw_Xin1_statef(void)
  129. {
  130. carthw_Xin1_write8(carthw_Xin1_baddr, 0);
  131. }
  132. void carthw_Xin1_startup(void)
  133. {
  134. elprintf(EL_STATUS, "X-in-1 mapper startup");
  135. PicoCartMemSetup = carthw_Xin1_mem_setup;
  136. PicoResetHook = carthw_Xin1_reset;
  137. PicoLoadStateHook = carthw_Xin1_statef;
  138. carthw_chunks = carthw_Xin1_state;
  139. }
  140. /* Realtec, based on TascoDLX doc
  141. * http://www.sharemation.com/TascoDLX/REALTEC%20Cart%20Mapper%20-%20description%20v1.txt
  142. */
  143. static int realtec_bank = 0x80000000, realtec_size = 0x80000000;
  144. static void carthw_realtec_write8(u32 a, u32 d)
  145. {
  146. int i, bank_old = realtec_bank, size_old = realtec_size;
  147. if (a == 0x400000)
  148. {
  149. realtec_bank &= 0x0e0000;
  150. realtec_bank |= 0x300000 & (d << 19);
  151. if (realtec_bank != bank_old)
  152. elprintf(EL_ANOMALY, "write [%06x] %02x @ %06x", a, d, SekPc);
  153. }
  154. else if (a == 0x402000)
  155. {
  156. realtec_size = (d << 17) & 0x3e0000;
  157. if (realtec_size != size_old)
  158. elprintf(EL_ANOMALY, "write [%06x] %02x @ %06x", a, d, SekPc);
  159. }
  160. else if (a == 0x404000)
  161. {
  162. realtec_bank &= 0x300000;
  163. realtec_bank |= 0x0e0000 & (d << 17);
  164. if (realtec_bank != bank_old)
  165. elprintf(EL_ANOMALY, "write [%06x] %02x @ %06x", a, d, SekPc);
  166. }
  167. else
  168. elprintf(EL_ANOMALY, "realtec: unexpected write [%06x] %02x @ %06x", a, d, SekPc);
  169. if (realtec_bank >= 0 && realtec_size >= 0 &&
  170. (realtec_bank != bank_old || realtec_size != size_old))
  171. {
  172. elprintf(EL_ANOMALY, "realtec: new bank %06x, size %06x", realtec_bank, realtec_size, SekPc);
  173. if (realtec_size > Pico.romsize - realtec_bank)
  174. {
  175. elprintf(EL_ANOMALY, "realtec: bank too large / out of range?");
  176. return;
  177. }
  178. for (i = 0; i < 0x400000; i += realtec_size) {
  179. cpu68k_map_set(m68k_read8_map, i, realtec_size - 1, Pico.rom + realtec_bank, 0);
  180. cpu68k_map_set(m68k_read16_map, i, realtec_size - 1, Pico.rom + realtec_bank, 0);
  181. }
  182. }
  183. }
  184. static void carthw_realtec_reset(void)
  185. {
  186. int i;
  187. /* map boot code */
  188. for (i = 0; i < 0x400000; i += M68K_BANK_SIZE) {
  189. cpu68k_map_set(m68k_read8_map, i, i + M68K_BANK_SIZE - 1, Pico.rom + Pico.romsize, 0);
  190. cpu68k_map_set(m68k_read16_map, i, i + M68K_BANK_SIZE - 1, Pico.rom + Pico.romsize, 0);
  191. }
  192. cpu68k_map_set(m68k_write8_map, 0x400000, 0x400000 + M68K_BANK_SIZE - 1, carthw_realtec_write8, 1);
  193. realtec_bank = realtec_size = 0x80000000;
  194. }
  195. void carthw_realtec_startup(void)
  196. {
  197. int i;
  198. elprintf(EL_STATUS, "Realtec mapper startup");
  199. // allocate additional bank for boot code
  200. // (we know those ROMs have aligned size)
  201. i = PicoCartResize(Pico.romsize + M68K_BANK_SIZE);
  202. if (i != 0) {
  203. elprintf(EL_STATUS, "OOM");
  204. return;
  205. }
  206. // create bank for boot code
  207. for (i = 0; i < M68K_BANK_SIZE; i += 0x2000)
  208. memcpy(Pico.rom + Pico.romsize + i, Pico.rom + Pico.romsize - 0x2000, 0x2000);
  209. PicoResetHook = carthw_realtec_reset;
  210. }
  211. /* Radica mapper, based on DevSter's info
  212. * http://devster.monkeeh.com/sega/radica/
  213. * XXX: mostly the same as X-in-1, merge?
  214. */
  215. static u32 carthw_radica_read16(u32 a)
  216. {
  217. if ((a & 0xffff00) != 0xa13000)
  218. return PicoRead16_io(a);
  219. carthw_Xin1_do(a, 0x7e, 15);
  220. return 0;
  221. }
  222. static void carthw_radica_mem_setup(void)
  223. {
  224. cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, carthw_radica_read16, 1);
  225. }
  226. static void carthw_radica_statef(void)
  227. {
  228. carthw_radica_read16(carthw_Xin1_baddr);
  229. }
  230. static void carthw_radica_reset(void)
  231. {
  232. carthw_radica_read16(0xa13000);
  233. }
  234. void carthw_radica_startup(void)
  235. {
  236. elprintf(EL_STATUS, "Radica mapper startup");
  237. PicoCartMemSetup = carthw_radica_mem_setup;
  238. PicoResetHook = carthw_radica_reset;
  239. PicoLoadStateHook = carthw_radica_statef;
  240. carthw_chunks = carthw_Xin1_state;
  241. }
  242. /* Pier Solar. Based on my own research */
  243. static unsigned char pier_regs[8];
  244. static unsigned char pier_dump_prot;
  245. static carthw_state_chunk carthw_pier_state[] =
  246. {
  247. { CHUNK_CARTHW, sizeof(pier_regs), pier_regs },
  248. { CHUNK_CARTHW + 1, sizeof(pier_dump_prot), &pier_dump_prot },
  249. { CHUNK_CARTHW + 2, 0, NULL }, // filled later
  250. { 0, 0, NULL }
  251. };
  252. static void carthw_pier_write8(u32 a, u32 d)
  253. {
  254. u32 a8, target, base;
  255. if ((a & 0xffff00) != 0xa13000) {
  256. PicoWrite8_io(a, d);
  257. return;
  258. }
  259. a8 = a & 0x0f;
  260. pier_regs[a8 / 2] = d;
  261. elprintf(EL_UIO, "pier w8 [%06x] %02x @%06x", a, d & 0xffff, SekPc);
  262. switch (a8) {
  263. case 0x01:
  264. break;
  265. case 0x03:
  266. if (!(pier_regs[0] & 2))
  267. goto unmapped;
  268. target = 0x280000;
  269. base = d << 19;
  270. goto do_map;
  271. case 0x05:
  272. if (!(pier_regs[0] & 2))
  273. goto unmapped;
  274. target = 0x300000;
  275. base = d << 19;
  276. goto do_map;
  277. case 0x07:
  278. if (!(pier_regs[0] & 2))
  279. goto unmapped;
  280. target = 0x380000;
  281. base = d << 19;
  282. goto do_map;
  283. case 0x09:
  284. Pico.sv.changed = 1;
  285. eeprom_spi_write(d);
  286. break;
  287. case 0x0b:
  288. // eeprom read
  289. default:
  290. unmapped:
  291. //elprintf(EL_UIO, "pier w8 [%06x] %02x @%06x", a, d & 0xffff, SekPc);
  292. elprintf(EL_STATUS, "-- unmapped w8 [%06x] %02x @%06x", a, d & 0xffff, SekPc);
  293. break;
  294. }
  295. return;
  296. do_map:
  297. if (!have_bank(base))
  298. return;
  299. cpu68k_map_set(m68k_read8_map, target, target + 0x80000 - 1, Pico.rom + base, 0);
  300. cpu68k_map_set(m68k_read16_map, target, target + 0x80000 - 1, Pico.rom + base, 0);
  301. }
  302. static void carthw_pier_write16(u32 a, u32 d)
  303. {
  304. if ((a & 0xffff00) != 0xa13000) {
  305. PicoWrite16_io(a, d);
  306. return;
  307. }
  308. elprintf(EL_UIO, "pier w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  309. carthw_pier_write8(a + 1, d);
  310. }
  311. static u32 carthw_pier_read8(u32 a)
  312. {
  313. if ((a & 0xffff00) != 0xa13000)
  314. return PicoRead8_io(a);
  315. if (a == 0xa1300b)
  316. return eeprom_spi_read(a);
  317. elprintf(EL_UIO, "pier r8 [%06x] @%06x", a, SekPc);
  318. return 0;
  319. }
  320. static void carthw_pier_statef(void);
  321. static u32 carthw_pier_prot_read8(u32 a)
  322. {
  323. /* it takes more than just these reads here to disable ROM protection,
  324. * but for game emulation purposes this is enough. */
  325. if (pier_dump_prot > 0)
  326. pier_dump_prot--;
  327. if (pier_dump_prot == 0) {
  328. carthw_pier_statef();
  329. elprintf(EL_STATUS, "prot off on r8 @%06x", SekPc);
  330. }
  331. elprintf(EL_UIO, "pier r8 [%06x] @%06x", a, SekPc);
  332. return Pico.rom[MEM_BE2(a & 0x7fff)];
  333. }
  334. static void carthw_pier_mem_setup(void)
  335. {
  336. cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, carthw_pier_write8, 1);
  337. cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, carthw_pier_write16, 1);
  338. cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, carthw_pier_read8, 1);
  339. }
  340. static void carthw_pier_prot_mem_setup(int prot_enable)
  341. {
  342. if (prot_enable) {
  343. /* the dump protection.. */
  344. int a;
  345. for (a = 0x000000; a < 0x400000; a += M68K_BANK_SIZE) {
  346. cpu68k_map_set(m68k_read8_map, a, a + 0xffff, Pico.rom + Pico.romsize, 0);
  347. cpu68k_map_set(m68k_read16_map, a, a + 0xffff, Pico.rom + Pico.romsize, 0);
  348. }
  349. cpu68k_map_set(m68k_read8_map, M68K_BANK_SIZE, M68K_BANK_SIZE * 2 - 1,
  350. carthw_pier_prot_read8, 1);
  351. }
  352. else {
  353. cpu68k_map_set(m68k_read8_map, 0, 0x27ffff, Pico.rom, 0);
  354. cpu68k_map_set(m68k_read16_map, 0, 0x27ffff, Pico.rom, 0);
  355. }
  356. }
  357. static void carthw_pier_statef(void)
  358. {
  359. carthw_pier_prot_mem_setup(pier_dump_prot);
  360. if (!pier_dump_prot) {
  361. /* setup all banks */
  362. u32 r0 = pier_regs[0];
  363. carthw_pier_write8(0xa13001, 3);
  364. carthw_pier_write8(0xa13003, pier_regs[1]);
  365. carthw_pier_write8(0xa13005, pier_regs[2]);
  366. carthw_pier_write8(0xa13007, pier_regs[3]);
  367. carthw_pier_write8(0xa13001, r0);
  368. }
  369. }
  370. static void carthw_pier_reset(void)
  371. {
  372. pier_regs[0] = 1;
  373. pier_regs[1] = pier_regs[2] = pier_regs[3] = 0;
  374. carthw_pier_statef();
  375. eeprom_spi_init(NULL);
  376. }
  377. void carthw_pier_startup(void)
  378. {
  379. void *eeprom_state;
  380. int eeprom_size = 0;
  381. int i;
  382. elprintf(EL_STATUS, "Pier Solar mapper startup");
  383. // mostly same as for realtec..
  384. i = PicoCartResize(Pico.romsize + M68K_BANK_SIZE);
  385. if (i != 0) {
  386. elprintf(EL_STATUS, "OOM");
  387. return;
  388. }
  389. pier_dump_prot = 3;
  390. // create dump protection bank
  391. for (i = 0; i < M68K_BANK_SIZE; i += 0x8000)
  392. memcpy(Pico.rom + Pico.romsize + i, Pico.rom, 0x8000);
  393. // save EEPROM
  394. eeprom_state = eeprom_spi_init(&eeprom_size);
  395. Pico.sv.flags = 0;
  396. Pico.sv.size = 0x10000;
  397. Pico.sv.data = calloc(1, Pico.sv.size);
  398. if (!Pico.sv.data)
  399. Pico.sv.size = 0;
  400. carthw_pier_state[2].ptr = eeprom_state;
  401. carthw_pier_state[2].size = eeprom_size;
  402. PicoCartMemSetup = carthw_pier_mem_setup;
  403. PicoResetHook = carthw_pier_reset;
  404. PicoLoadStateHook = carthw_pier_statef;
  405. carthw_chunks = carthw_pier_state;
  406. }
  407. /* superfighter mappers, see mame: mame/src/devices/bus/megadrive/rom.cpp */
  408. unsigned int carthw_sf00x_reg;
  409. static carthw_state_chunk carthw_sf00x_state[] =
  410. {
  411. { CHUNK_CARTHW, sizeof(carthw_sf00x_reg), &carthw_sf00x_reg },
  412. { 0, 0, NULL }
  413. };
  414. // SF-001
  415. // additionally map SRAM at 0x3c0000 for the newer version of sf001
  416. static u32 carthw_sf001_read8_sram(u32 a)
  417. {
  418. return m68k_read8((a & 0xffff) + Pico.sv.start);
  419. }
  420. static u32 carthw_sf001_read16_sram(u32 a)
  421. {
  422. return m68k_read16((a & 0xffff) + Pico.sv.start);
  423. }
  424. static void carthw_sf001_write8_sram(u32 a, u32 d)
  425. {
  426. m68k_write8((a & 0xffff) + Pico.sv.start, d);
  427. }
  428. static void carthw_sf001_write16_sram(u32 a, u32 d)
  429. {
  430. m68k_write16((a & 0xffff) + Pico.sv.start, d);
  431. }
  432. static void carthw_sf001_write8(u32 a, u32 d)
  433. {
  434. if ((a & 0xf00) != 0xe00 || (carthw_sf00x_reg & 0x20)) // wrong addr / locked
  435. return;
  436. if (d & 0x80) {
  437. // bank 0xe at addr 0x000000
  438. cpu68k_map_set(m68k_read8_map, 0x000000, 0x040000-1, Pico.rom+0x380000, 0);
  439. cpu68k_map_set(m68k_read16_map, 0x000000, 0x040000-1, Pico.rom+0x380000, 0);
  440. // SRAM also at 0x3c0000 for newer mapper version
  441. cpu68k_map_set(m68k_read8_map, 0x3c0000, 0x400000-1, carthw_sf001_read8_sram, 1);
  442. cpu68k_map_set(m68k_read16_map, 0x3c0000, 0x400000-1, carthw_sf001_read16_sram, 1);
  443. cpu68k_map_set(m68k_write8_map, 0x3c0000, 0x400000-1, carthw_sf001_write8_sram, 1);
  444. cpu68k_map_set(m68k_write16_map,0x3c0000, 0x400000-1, carthw_sf001_write16_sram, 1);
  445. } else {
  446. // bank 0x0 at addr 0x000000
  447. cpu68k_map_set(m68k_read8_map, 0x000000, 0x040000-1, Pico.rom, 0);
  448. cpu68k_map_set(m68k_read16_map, 0x000000, 0x040000-1, Pico.rom, 0);
  449. // SRAM off, bank 0xf at addr 0x3c0000
  450. cpu68k_map_set(m68k_read8_map, 0x3c0000, 0x400000-1, Pico.rom+0x3c0000, 0);
  451. cpu68k_map_set(m68k_read16_map, 0x3c0000, 0x400000-1, Pico.rom+0x3c0000, 0);
  452. cpu68k_map_set(m68k_write8_map, 0x3c0000, 0x400000-1, Pico.rom+0x3c0000, 0);
  453. cpu68k_map_set(m68k_write16_map,0x3c0000, 0x400000-1, Pico.rom+0x3c0000, 0);
  454. }
  455. carthw_sf00x_reg = d;
  456. }
  457. static void carthw_sf001_write16(u32 a, u32 d)
  458. {
  459. carthw_sf001_write8(a + 1, d);
  460. }
  461. static void carthw_sf001_mem_setup(void)
  462. {
  463. // writing to low cartridge addresses
  464. cpu68k_map_set(m68k_write8_map, 0x000000, 0x00ffff, carthw_sf001_write8, 1);
  465. cpu68k_map_set(m68k_write16_map, 0x000000, 0x00ffff, carthw_sf001_write16, 1);
  466. }
  467. static void carthw_sf001_reset(void)
  468. {
  469. carthw_sf00x_reg = 0;
  470. carthw_sf001_write8(0x0e01, 0);
  471. }
  472. static void carthw_sf001_statef(void)
  473. {
  474. int reg = carthw_sf00x_reg;
  475. carthw_sf00x_reg = 0;
  476. carthw_sf001_write8(0x0e01, reg);
  477. }
  478. void carthw_sf001_startup(void)
  479. {
  480. PicoCartMemSetup = carthw_sf001_mem_setup;
  481. PicoResetHook = carthw_sf001_reset;
  482. PicoLoadStateHook = carthw_sf001_statef;
  483. carthw_chunks = carthw_sf00x_state;
  484. }
  485. // SF-002
  486. static void carthw_sf002_write8(u32 a, u32 d)
  487. {
  488. if ((a & 0xf00) != 0xe00)
  489. return;
  490. if (d & 0x80) {
  491. // bank 0x00-0x0e on addr 0x20000
  492. cpu68k_map_set(m68k_read8_map, 0x200000, 0x3c0000-1, Pico.rom, 0);
  493. cpu68k_map_set(m68k_read16_map, 0x200000, 0x3c0000-1, Pico.rom, 0);
  494. } else {
  495. // bank 0x10-0x1e on addr 0x20000
  496. cpu68k_map_set(m68k_read8_map, 0x200000, 0x3c0000-1, Pico.rom+0x200000, 0);
  497. cpu68k_map_set(m68k_read16_map, 0x200000, 0x3c0000-1, Pico.rom+0x200000, 0);
  498. }
  499. carthw_sf00x_reg = d;
  500. }
  501. static void carthw_sf002_write16(u32 a, u32 d)
  502. {
  503. carthw_sf002_write8(a + 1, d);
  504. }
  505. static void carthw_sf002_mem_setup(void)
  506. {
  507. // writing to low cartridge addresses
  508. cpu68k_map_set(m68k_write8_map, 0x000000, 0x00ffff, carthw_sf002_write8, 1);
  509. cpu68k_map_set(m68k_write16_map, 0x000000, 0x00ffff, carthw_sf002_write16, 1);
  510. }
  511. static void carthw_sf002_reset(void)
  512. {
  513. carthw_sf002_write8(0x0e01, 0);
  514. }
  515. static void carthw_sf002_statef(void)
  516. {
  517. carthw_sf002_write8(0x0e01, carthw_sf00x_reg);
  518. }
  519. void carthw_sf002_startup(void)
  520. {
  521. PicoCartMemSetup = carthw_sf002_mem_setup;
  522. PicoResetHook = carthw_sf002_reset;
  523. PicoLoadStateHook = carthw_sf002_statef;
  524. carthw_chunks = carthw_sf00x_state;
  525. }
  526. // SF-004
  527. // reading from cartridge I/O region returns the current bank index
  528. static u32 carthw_sf004_read8(u32 a)
  529. {
  530. if ((a & ~0xff) == 0xa13000)
  531. return carthw_sf00x_reg & 0xf0; // bank index
  532. return PicoRead8_io(a);
  533. }
  534. static u32 carthw_sf004_read16(u32 a)
  535. {
  536. if ((a & ~0xff) == 0xa13000)
  537. return carthw_sf00x_reg & 0xf0;
  538. return PicoRead16_io(a);
  539. }
  540. // writing to low cartridge adresses changes mappings
  541. static void carthw_sf004_write8(u32 a, u32 d)
  542. {
  543. int idx, i;
  544. unsigned bs = 0x40000; // bank size
  545. // there are 3 byte-sized regs, stored together in carthw_sf00x_reg
  546. if (!(carthw_sf00x_reg & 0x8000))
  547. return; // locked
  548. switch (a & 0xf00) {
  549. case 0xd00:
  550. carthw_sf00x_reg = (carthw_sf00x_reg & ~0xff0000) | ((d & 0xff) << 16);
  551. return PicoWrite8_io(0xa130f1, (d & 0x80) ? SRR_MAPPED : 0); // SRAM mapping
  552. case 0xe00:
  553. carthw_sf00x_reg = (carthw_sf00x_reg & ~0x00ff00) | ((d & 0xff) << 8);
  554. break;
  555. case 0xf00:
  556. carthw_sf00x_reg = (carthw_sf00x_reg & ~0x0000ff) | ((d & 0xff) << 0);
  557. break;
  558. default:
  559. return; // wrong addr
  560. }
  561. // bank mapping changed
  562. idx = ((carthw_sf00x_reg>>4) & 0x7); // bank index
  563. if ((carthw_sf00x_reg>>8) & 0x40) {
  564. // linear bank mapping, starting at idx
  565. for (i = 0; i < 8; i++, idx = (idx+1) & 0x7) {
  566. cpu68k_map_set(m68k_read8_map, i*bs, (i+1)*bs-1, Pico.rom + idx*bs, 0);
  567. cpu68k_map_set(m68k_read16_map, i*bs, (i+1)*bs-1, Pico.rom + idx*bs, 0);
  568. }
  569. } else {
  570. // single bank mapping
  571. for (i = 0; i < 8; i++) {
  572. cpu68k_map_set(m68k_read8_map, i*bs, (i+1)*bs-1, Pico.rom + idx*bs, 0);
  573. cpu68k_map_set(m68k_read16_map, i*bs, (i+1)*bs-1, Pico.rom + idx*bs, 0);
  574. }
  575. }
  576. }
  577. static void carthw_sf004_write16(u32 a, u32 d)
  578. {
  579. carthw_sf004_write8(a + 1, d);
  580. }
  581. static void carthw_sf004_mem_setup(void)
  582. {
  583. // writing to low cartridge addresses
  584. cpu68k_map_set(m68k_write8_map, 0x000000, 0x00ffff, carthw_sf004_write8, 1);
  585. cpu68k_map_set(m68k_write16_map, 0x000000, 0x00ffff, carthw_sf004_write16, 1);
  586. // reading from the cartridge I/O region
  587. cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, carthw_sf004_read8, 1);
  588. cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, carthw_sf004_read16, 1);
  589. }
  590. static void carthw_sf004_reset(void)
  591. {
  592. carthw_sf00x_reg = -1;
  593. carthw_sf004_write8(0x0d01, 0);
  594. carthw_sf004_write8(0x0f01, 0);
  595. carthw_sf004_write8(0x0e01, 0x80);
  596. }
  597. static void carthw_sf004_statef(void)
  598. {
  599. int reg = carthw_sf00x_reg;
  600. carthw_sf00x_reg = -1;
  601. carthw_sf004_write8(0x0d01, reg >> 16);
  602. carthw_sf004_write8(0x0f01, reg >> 0);
  603. carthw_sf004_write8(0x0e01, reg >> 8);
  604. }
  605. void carthw_sf004_startup(void)
  606. {
  607. PicoCartMemSetup = carthw_sf004_mem_setup;
  608. PicoResetHook = carthw_sf004_reset;
  609. PicoLoadStateHook = carthw_sf004_statef;
  610. carthw_chunks = carthw_sf00x_state;
  611. }
  612. /* Simple unlicensed ROM protection emulation */
  613. static struct {
  614. u32 addr;
  615. u32 mask;
  616. u16 val;
  617. u16 readonly;
  618. } *sprot_items;
  619. static int sprot_item_alloc;
  620. static int sprot_item_count;
  621. static u16 *carthw_sprot_get_val(u32 a, int rw_only)
  622. {
  623. int i;
  624. for (i = 0; i < sprot_item_count; i++)
  625. if ((a & sprot_items[i].mask) == sprot_items[i].addr)
  626. if (!rw_only || !sprot_items[i].readonly)
  627. return &sprot_items[i].val;
  628. return NULL;
  629. }
  630. static u32 PicoRead8_sprot(u32 a)
  631. {
  632. u16 *val;
  633. u32 d;
  634. if (0xa10000 <= a && a < 0xa12000)
  635. return PicoRead8_io(a);
  636. val = carthw_sprot_get_val(a, 0);
  637. if (val != NULL) {
  638. d = *val;
  639. if (!(a & 1))
  640. d >>= 8;
  641. elprintf(EL_UIO, "prot r8 [%06x] %02x @%06x", a, d, SekPc);
  642. return d;
  643. }
  644. else {
  645. elprintf(EL_UIO, "prot r8 [%06x] MISS @%06x", a, SekPc);
  646. return 0;
  647. }
  648. }
  649. static u32 PicoRead16_sprot(u32 a)
  650. {
  651. u16 *val;
  652. if (0xa10000 <= a && a < 0xa12000)
  653. return PicoRead16_io(a);
  654. val = carthw_sprot_get_val(a, 0);
  655. if (val != NULL) {
  656. elprintf(EL_UIO, "prot r16 [%06x] %04x @%06x", a, *val, SekPc);
  657. return *val;
  658. }
  659. else {
  660. elprintf(EL_UIO, "prot r16 [%06x] MISS @%06x", a, SekPc);
  661. return 0;
  662. }
  663. }
  664. static void PicoWrite8_sprot(u32 a, u32 d)
  665. {
  666. u16 *val;
  667. if (0xa10000 <= a && a < 0xa12000) {
  668. PicoWrite8_io(a, d);
  669. return;
  670. }
  671. val = carthw_sprot_get_val(a, 1);
  672. if (val != NULL) {
  673. if (a & 1)
  674. *val = (*val & 0xff00) | (d | 0xff);
  675. else
  676. *val = (*val & 0x00ff) | (d << 8);
  677. elprintf(EL_UIO, "prot w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  678. }
  679. else
  680. elprintf(EL_UIO, "prot w8 [%06x] %02x MISS @%06x", a, d & 0xff, SekPc);
  681. }
  682. static void PicoWrite16_sprot(u32 a, u32 d)
  683. {
  684. u16 *val;
  685. if (0xa10000 <= a && a < 0xa12000) {
  686. PicoWrite16_io(a, d);
  687. return;
  688. }
  689. val = carthw_sprot_get_val(a, 1);
  690. if (val != NULL) {
  691. *val = d;
  692. elprintf(EL_UIO, "prot w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
  693. }
  694. else
  695. elprintf(EL_UIO, "prot w16 [%06x] %04x MISS @%06x", a, d & 0xffff, SekPc);
  696. }
  697. void carthw_sprot_new_location(unsigned int a, unsigned int mask, unsigned short val, int is_ro)
  698. {
  699. if (sprot_items == NULL) {
  700. sprot_items = calloc(8, sizeof(sprot_items[0]));
  701. sprot_item_alloc = 8;
  702. sprot_item_count = 0;
  703. }
  704. if (sprot_item_count == sprot_item_alloc) {
  705. void *tmp;
  706. sprot_item_alloc *= 2;
  707. tmp = realloc(sprot_items, sprot_item_alloc);
  708. if (tmp == NULL) {
  709. elprintf(EL_STATUS, "OOM");
  710. return;
  711. }
  712. sprot_items = tmp;
  713. }
  714. sprot_items[sprot_item_count].addr = a;
  715. sprot_items[sprot_item_count].mask = mask;
  716. sprot_items[sprot_item_count].val = val;
  717. sprot_items[sprot_item_count].readonly = is_ro;
  718. sprot_item_count++;
  719. }
  720. static void carthw_sprot_unload(void)
  721. {
  722. free(sprot_items);
  723. sprot_items = NULL;
  724. sprot_item_count = sprot_item_alloc = 0;
  725. }
  726. static void carthw_sprot_mem_setup(void)
  727. {
  728. int start;
  729. // map ROM - 0x7fffff, /TIME areas (which are tipically used)
  730. start = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
  731. cpu68k_map_set(m68k_read8_map, start, 0x7fffff, PicoRead8_sprot, 1);
  732. cpu68k_map_set(m68k_read16_map, start, 0x7fffff, PicoRead16_sprot, 1);
  733. cpu68k_map_set(m68k_write8_map, start, 0x7fffff, PicoWrite8_sprot, 1);
  734. cpu68k_map_set(m68k_write16_map, start, 0x7fffff, PicoWrite16_sprot, 1);
  735. cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_sprot, 1);
  736. cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_sprot, 1);
  737. cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_sprot, 1);
  738. cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_sprot, 1);
  739. }
  740. void carthw_sprot_startup(void)
  741. {
  742. elprintf(EL_STATUS, "Prot emu startup");
  743. PicoCartMemSetup = carthw_sprot_mem_setup;
  744. PicoCartUnloadHook = carthw_sprot_unload;
  745. }
  746. /* Protection emulation for Lion King 3. Credits go to Haze */
  747. static u8 prot_lk3_cmd, prot_lk3_data;
  748. static u32 PicoRead8_plk3(u32 a)
  749. {
  750. u32 d = 0;
  751. switch (prot_lk3_cmd) {
  752. case 1: d = prot_lk3_data >> 1; break;
  753. case 2: // nibble rotate
  754. d = ((prot_lk3_data >> 4) | (prot_lk3_data << 4)) & 0xff;
  755. break;
  756. case 3: // bit rotate
  757. d = prot_lk3_data;
  758. d = (d >> 4) | (d << 4);
  759. d = ((d & 0xcc) >> 2) | ((d & 0x33) << 2);
  760. d = ((d & 0xaa) >> 1) | ((d & 0x55) << 1);
  761. break;
  762. /* Top Fighter 2000 MK VIII (Unl)
  763. case 0x98: d = 0x50; break; // prot_lk3_data == a8 here
  764. case 0x67: d = 0xde; break; // prot_lk3_data == 7b here (rot!)
  765. case 0xb5: d = 0x9f; break; // prot_lk3_data == 4a
  766. */
  767. default:
  768. elprintf(EL_UIO, "unhandled prot cmd %02x @%06x", prot_lk3_cmd, SekPc);
  769. break;
  770. }
  771. elprintf(EL_UIO, "prot r8 [%06x] %02x @%06x", a, d, SekPc);
  772. return d;
  773. }
  774. static void PicoWrite8_plk3p(u32 a, u32 d)
  775. {
  776. elprintf(EL_UIO, "prot w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  777. if (a & 2)
  778. prot_lk3_cmd = d;
  779. else
  780. prot_lk3_data = d;
  781. }
  782. static void PicoWrite8_plk3b(u32 a, u32 d)
  783. {
  784. int addr;
  785. elprintf(EL_UIO, "prot w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
  786. addr = d << 15;
  787. if (addr + 0x8000 > Pico.romsize) {
  788. elprintf(EL_UIO|EL_ANOMALY, "prot_lk3: bank too large: %02x", d);
  789. return;
  790. }
  791. if (addr == 0)
  792. memcpy(Pico.rom, Pico.rom + Pico.romsize, 0x8000);
  793. else
  794. memcpy(Pico.rom, Pico.rom + addr, 0x8000);
  795. }
  796. static void carthw_prot_lk3_mem_setup(void)
  797. {
  798. cpu68k_map_set(m68k_read8_map, 0x600000, 0x7fffff, PicoRead8_plk3, 1);
  799. cpu68k_map_set(m68k_write8_map, 0x600000, 0x6fffff, PicoWrite8_plk3p, 1);
  800. cpu68k_map_set(m68k_write8_map, 0x700000, 0x7fffff, PicoWrite8_plk3b, 1);
  801. }
  802. void carthw_prot_lk3_startup(void)
  803. {
  804. int ret;
  805. elprintf(EL_STATUS, "lk3 prot emu startup");
  806. // allocate space for bank0 backup
  807. ret = PicoCartResize(Pico.romsize + 0x8000);
  808. if (ret != 0) {
  809. elprintf(EL_STATUS, "OOM");
  810. return;
  811. }
  812. memcpy(Pico.rom + Pico.romsize, Pico.rom, 0x8000);
  813. PicoCartMemSetup = carthw_prot_lk3_mem_setup;
  814. }
  815. // vim:ts=2:sw=2:expandtab