pico_int.h 29 KB

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  1. /*
  2. * PicoDrive - Internal Header File
  3. * (c) Copyright Dave, 2004
  4. * (C) notaz, 2006-2010
  5. *
  6. * This work is licensed under the terms of MAME license.
  7. * See COPYING file in the top-level directory.
  8. */
  9. #ifndef PICO_INTERNAL_INCLUDED
  10. #define PICO_INTERNAL_INCLUDED
  11. #include <stdio.h>
  12. #include <stdlib.h>
  13. #include <string.h>
  14. #include "pico.h"
  15. #include "carthw/carthw.h"
  16. //
  17. #define USE_POLL_DETECT
  18. #ifndef PICO_INTERNAL
  19. #define PICO_INTERNAL
  20. #endif
  21. #ifndef PICO_INTERNAL_ASM
  22. #define PICO_INTERNAL_ASM
  23. #endif
  24. // to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project
  25. #ifdef __cplusplus
  26. extern "C" {
  27. #endif
  28. // ----------------------- 68000 CPU -----------------------
  29. #ifdef EMU_C68K
  30. #include "../cpu/cyclone/Cyclone.h"
  31. extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;
  32. #define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run
  33. #define SekCyclesLeft \
  34. (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)
  35. #define SekCyclesLeftS68k \
  36. ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)
  37. #define SekEndTimeslice(after) PicoCpuCM68k.cycles=after
  38. #define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after
  39. #define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)
  40. #define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)
  41. #define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])
  42. #define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])
  43. #define SekSr CycloneGetSr(&PicoCpuCM68k)
  44. #define SekSrS68k CycloneGetSr(&PicoCpuCS68k)
  45. #define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }
  46. #define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }
  47. #define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)
  48. #define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)
  49. #define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))
  50. #define SekInterrupt(i) PicoCpuCM68k.irq=i
  51. #define SekIrqLevel PicoCpuCM68k.irq
  52. #ifdef EMU_M68K
  53. #define EMU_CORE_DEBUG
  54. #endif
  55. #endif
  56. #ifdef EMU_F68K
  57. #include "../cpu/fame/fame.h"
  58. extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;
  59. #define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter
  60. #define SekCyclesLeft \
  61. (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)
  62. #define SekCyclesLeftS68k \
  63. ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)
  64. #define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after
  65. #define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after
  66. #define SekPc fm68k_get_pc(&PicoCpuFM68k)
  67. #define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)
  68. #define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)
  69. #define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)
  70. #define SekSr PicoCpuFM68k.sr
  71. #define SekSrS68k PicoCpuFS68k.sr
  72. #define SekSetStop(x) { \
  73. PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \
  74. if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \
  75. }
  76. #define SekSetStopS68k(x) { \
  77. PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \
  78. if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \
  79. }
  80. #define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)
  81. #define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)
  82. #define SekShouldInterrupt fm68k_would_interrupt()
  83. #define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq
  84. #define SekIrqLevel PicoCpuFM68k.interrupts[0]
  85. #ifdef EMU_M68K
  86. #define EMU_CORE_DEBUG
  87. #endif
  88. #endif
  89. #ifdef EMU_M68K
  90. #include "../cpu/musashi/m68kcpu.h"
  91. extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;
  92. #ifndef SekCyclesLeft
  93. #define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles
  94. #define SekCyclesLeft \
  95. (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)
  96. #define SekCyclesLeftS68k \
  97. ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)
  98. #define SekEndTimeslice(after) SET_CYCLES(after)
  99. #define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after
  100. #define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)
  101. #define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)
  102. #define SekDar(x) PicoCpuMM68k.dar[x]
  103. #define SekDarS68k(x) PicoCpuMS68k.dar[x]
  104. #define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)
  105. #define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)
  106. #define SekSetStop(x) { \
  107. if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \
  108. else PicoCpuMM68k.stopped=0; \
  109. }
  110. #define SekSetStopS68k(x) { \
  111. if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \
  112. else PicoCpuMS68k.stopped=0; \
  113. }
  114. #define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)
  115. #define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)
  116. #define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)
  117. #define SekInterrupt(irq) { \
  118. void *oldcontext = m68ki_cpu_p; \
  119. m68k_set_context(&PicoCpuMM68k); \
  120. m68k_set_irq(irq); \
  121. m68k_set_context(oldcontext); \
  122. }
  123. #define SekIrqLevel (PicoCpuMM68k.int_level >> 8)
  124. #endif
  125. #endif // EMU_M68K
  126. extern int SekCycleCnt; // cycles done in this frame
  127. extern int SekCycleAim; // cycle aim
  128. extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame
  129. #define SekCyclesReset() { \
  130. SekCycleCntT+=SekCycleAim; \
  131. SekCycleCnt-=SekCycleAim; \
  132. SekCycleAim=0; \
  133. }
  134. #define SekCyclesBurn(c) SekCycleCnt+=c
  135. #define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)
  136. #define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom
  137. #define SekCyclesDoneT2() (SekCycleCntT + SekCycleCnt) // same as above but not from memhandlers
  138. #define SekEndRun(after) { \
  139. SekCycleCnt -= SekCyclesLeft - (after); \
  140. if (SekCycleCnt < 0) SekCycleCnt = 0; \
  141. SekEndTimeslice(after); \
  142. }
  143. #define SekEndRunS68k(after) { \
  144. SekCycleCntS68k -= SekCyclesLeftS68k - (after); \
  145. if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \
  146. SekEndTimesliceS68k(after); \
  147. }
  148. extern int SekCycleCntS68k;
  149. extern int SekCycleAimS68k;
  150. #define SekCyclesResetS68k() { \
  151. SekCycleCntS68k-=SekCycleAimS68k; \
  152. SekCycleAimS68k=0; \
  153. }
  154. #define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)
  155. #ifdef EMU_CORE_DEBUG
  156. extern int dbg_irq_level;
  157. #undef SekEndTimeslice
  158. #undef SekCyclesBurn
  159. #undef SekEndRun
  160. #undef SekInterrupt
  161. #define SekEndTimeslice(c)
  162. #define SekCyclesBurn(c) c
  163. #define SekEndRun(c)
  164. #define SekInterrupt(irq) dbg_irq_level=irq
  165. #endif
  166. // ----------------------- Z80 CPU -----------------------
  167. #if defined(_USE_DRZ80)
  168. #include "../cpu/DrZ80/drz80.h"
  169. extern struct DrZ80 drZ80;
  170. #define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))
  171. #define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)
  172. #define z80_int() drZ80.Z80_IRQ = 1
  173. #define z80_cyclesLeft drZ80.cycles
  174. #define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)
  175. #elif defined(_USE_CZ80)
  176. #include "../cpu/cz80/cz80.h"
  177. #define z80_run(cycles) Cz80_Exec(&CZ80, cycles)
  178. #define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)
  179. #define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)
  180. #define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)
  181. #define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)
  182. #else
  183. #define z80_run(cycles) (cycles)
  184. #define z80_run_nr(cycles)
  185. #define z80_int()
  186. #endif
  187. #define Z80_STATE_SIZE 0x60
  188. extern int z80stopCycle; /* in 68k cycles */
  189. extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */
  190. extern int z80_cycle_aim;
  191. extern int z80_scanline;
  192. extern int z80_scanline_cycles; /* cycles done until z80_scanline */
  193. #define z80_resetCycles() \
  194. z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;
  195. #define z80_cyclesDone() \
  196. (z80_cycle_aim - z80_cyclesLeft)
  197. #define cycles_68k_to_z80(x) ((x)*957 >> 11)
  198. // ----------------------- SH2 CPU -----------------------
  199. #include "cpu/sh2/sh2.h"
  200. extern SH2 sh2s[2];
  201. #define msh2 sh2s[0]
  202. #define ssh2 sh2s[1]
  203. #ifndef DRC_SH2
  204. # define sh2_end_run(sh2, after_) do { \
  205. if ((sh2)->icount > (after_)) { \
  206. (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \
  207. (sh2)->icount = after_; \
  208. } \
  209. } while (0)
  210. # define sh2_cycles_left(sh2) (sh2)->icount
  211. # define sh2_pc(sh2) (sh2)->ppc
  212. #else
  213. # define sh2_end_run(sh2, after_) do { \
  214. int left_ = (signed int)(sh2)->sr >> 12; \
  215. if (left_ > (after_)) { \
  216. (sh2)->cycles_timeslice -= left_ - (after_); \
  217. (sh2)->sr &= 0xfff; \
  218. (sh2)->sr |= (after_) << 12; \
  219. } \
  220. } while (0)
  221. # define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)
  222. # define sh2_pc(sh2) (sh2)->pc
  223. #endif
  224. #define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))
  225. #define sh2_cycles_done_t(sh2) \
  226. ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))
  227. #define sh2_cycles_done_m68k(sh2) \
  228. ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))
  229. #define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]
  230. #define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr
  231. #define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr
  232. #define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)
  233. #define sh2_set_gbr(c, v) \
  234. { if (c) ssh2.gbr = v; else msh2.gbr = v; }
  235. #define sh2_set_vbr(c, v) \
  236. { if (c) ssh2.vbr = v; else msh2.vbr = v; }
  237. // ---------------------------------------------------------
  238. // main oscillator clock which controls timing
  239. #define OSC_NTSC 53693100
  240. #define OSC_PAL 53203424
  241. struct PicoVideo
  242. {
  243. unsigned char reg[0x20];
  244. unsigned int command; // 32-bit Command
  245. unsigned char pending; // 1 if waiting for second half of 32-bit command
  246. unsigned char type; // Command type (v/c/vsram read/write)
  247. unsigned short addr; // Read/Write address
  248. int status; // Status bits
  249. unsigned char pending_ints; // pending interrupts: ??VH????
  250. signed char lwrite_cnt; // VDP write count during active display line
  251. unsigned short v_counter; // V-counter
  252. unsigned char pad[0x10];
  253. };
  254. struct PicoMisc
  255. {
  256. unsigned char rotate;
  257. unsigned char z80Run;
  258. unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches
  259. unsigned short scanline; // 04 0 to 261||311
  260. char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)
  261. unsigned char hardware; // 07 Hardware value for country
  262. unsigned char pal; // 08 1=PAL 0=NTSC
  263. unsigned char sram_reg; // 09 SRAM reg. See SRR_* below
  264. unsigned short z80_bank68k; // 0a
  265. unsigned short pad0;
  266. unsigned char pad1;
  267. unsigned char z80_reset; // 0f z80 reset held
  268. unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay
  269. unsigned short eeprom_addr; // EEPROM address register
  270. unsigned char eeprom_cycle; // EEPROM cycle number
  271. unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs
  272. unsigned char eeprom_status;
  273. unsigned char pad2;
  274. unsigned short dma_xfers; // 18
  275. unsigned char eeprom_wb[2]; // EEPROM latch/write buffer
  276. unsigned int frame_count; // 1c for movies and idle det
  277. };
  278. struct PicoMS
  279. {
  280. unsigned char carthw[0x10];
  281. unsigned char io_ctl;
  282. unsigned char pad[0x4f];
  283. };
  284. // some assembly stuff depend on these, do not touch!
  285. struct Pico
  286. {
  287. unsigned char ram[0x10000]; // 0x00000 scratch ram
  288. union { // vram is byteswapped for easier reads when drawing
  289. unsigned short vram[0x8000]; // 0x10000
  290. unsigned char vramb[0x4000]; // VRAM in SMS mode
  291. };
  292. unsigned char zram[0x2000]; // 0x20000 Z80 ram
  293. unsigned char ioports[0x10]; // XXX: fix asm and mv
  294. unsigned char pad[0xf0]; // unused
  295. unsigned short cram[0x40]; // 0x22100
  296. unsigned short vsram[0x40]; // 0x22180
  297. unsigned char *rom; // 0x22200
  298. unsigned int romsize; // 0x22204
  299. struct PicoMisc m;
  300. struct PicoVideo video;
  301. struct PicoMS ms;
  302. };
  303. // sram
  304. #define SRR_MAPPED (1 << 0)
  305. #define SRR_READONLY (1 << 1)
  306. #define SRF_ENABLED (1 << 0)
  307. #define SRF_EEPROM (1 << 1)
  308. struct PicoSRAM
  309. {
  310. unsigned char *data; // actual data
  311. unsigned int start; // start address in 68k address space
  312. unsigned int end;
  313. unsigned char flags; // 0c: SRF_*
  314. unsigned char unused2;
  315. unsigned char changed;
  316. unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words
  317. unsigned char unused3;
  318. unsigned char eeprom_bit_cl; // bit number for cl
  319. unsigned char eeprom_bit_in; // bit number for in
  320. unsigned char eeprom_bit_out; // bit number for out
  321. unsigned int size;
  322. };
  323. // MCD
  324. #include "cd/cd_sys.h"
  325. #include "cd/LC89510.h"
  326. #include "cd/gfx_cd.h"
  327. struct mcd_pcm
  328. {
  329. unsigned char control; // reg7
  330. unsigned char enabled; // reg8
  331. unsigned char cur_ch;
  332. unsigned char bank;
  333. int pad1;
  334. struct pcm_chan // 08, size 0x10
  335. {
  336. unsigned char regs[8];
  337. unsigned int addr; // .08: played sample address
  338. int pad;
  339. } ch[8];
  340. };
  341. struct mcd_misc
  342. {
  343. unsigned short hint_vector;
  344. unsigned char busreq;
  345. unsigned char s68k_pend_ints;
  346. unsigned int state_flags; // 04: emu state: reset_pending
  347. unsigned int counter75hz;
  348. unsigned int pad0;
  349. int timer_int3; // 10
  350. unsigned int timer_stopwatch;
  351. unsigned char bcram_reg; // 18: battery-backed RAM cart register
  352. unsigned char pad2;
  353. unsigned short pad3;
  354. int pad[9];
  355. };
  356. typedef struct
  357. {
  358. unsigned char bios[0x20000]; // 000000: 128K
  359. union { // 020000: 512K
  360. unsigned char prg_ram[0x80000];
  361. unsigned char prg_ram_b[4][0x20000];
  362. };
  363. union { // 0a0000: 256K
  364. struct {
  365. unsigned char word_ram2M[0x40000];
  366. unsigned char unused0[0x20000];
  367. };
  368. struct {
  369. unsigned char unused1[0x20000];
  370. unsigned char word_ram1M[2][0x20000];
  371. };
  372. };
  373. union { // 100000: 64K
  374. unsigned char pcm_ram[0x10000];
  375. unsigned char pcm_ram_b[0x10][0x1000];
  376. };
  377. unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs
  378. unsigned char bram[0x2000]; // 110200: 8K
  379. struct mcd_misc m; // 112200: misc
  380. struct mcd_pcm pcm; // 112240:
  381. _scd_toc TOC; // not to be saved
  382. CDD cdd;
  383. CDC cdc;
  384. _scd scd;
  385. Rot_Comp rot_comp;
  386. } mcd_state;
  387. // XXX: this will need to be reworked for cart+cd support.
  388. #define Pico_mcd ((mcd_state *)Pico.rom)
  389. // 32X
  390. #define P32XS_FM (1<<15)
  391. #define P32XS_REN (1<< 7)
  392. #define P32XS_nRES (1<< 1)
  393. #define P32XS_ADEN (1<< 0)
  394. #define P32XS2_ADEN (1<< 9)
  395. #define P32XS_FULL (1<< 7) // DREQ FIFO full
  396. #define P32XS_68S (1<< 2)
  397. #define P32XS_DMA (1<< 1)
  398. #define P32XS_RV (1<< 0)
  399. #define P32XV_nPAL (1<<15) // VDP
  400. #define P32XV_PRI (1<< 7)
  401. #define P32XV_Mx (3<< 0) // display mode mask
  402. #define P32XV_SFT (1<< 0)
  403. #define P32XV_VBLK (1<<15)
  404. #define P32XV_HBLK (1<<14)
  405. #define P32XV_PEN (1<<13)
  406. #define P32XV_nFEN (1<< 1)
  407. #define P32XV_FS (1<< 0)
  408. #define P32XP_RTP (1<<7) // PWM control
  409. #define P32XP_FULL (1<<15) // PWM pulse
  410. #define P32XP_EMPTY (1<<14)
  411. #define P32XF_68KCPOLL (1 << 0)
  412. #define P32XF_68KVPOLL (1 << 1)
  413. #define P32XI_VRES (1 << 14/2) // IRL/2
  414. #define P32XI_VINT (1 << 12/2)
  415. #define P32XI_HINT (1 << 10/2)
  416. #define P32XI_CMD (1 << 8/2)
  417. #define P32XI_PWM (1 << 6/2)
  418. // peripheral reg access
  419. #define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]
  420. // real one is 4*2, but we use more because we don't lockstep
  421. #define DMAC_FIFO_LEN (4*4)
  422. #define PWM_BUFF_LEN 1024 // in one channel samples
  423. #define SH2_DRCBLK_RAM_SHIFT 1
  424. #define SH2_DRCBLK_DA_SHIFT 1
  425. #define SH2_READ_SHIFT 25
  426. #define SH2_WRITE_SHIFT 25
  427. struct Pico32x
  428. {
  429. unsigned short regs[0x20];
  430. unsigned short vdp_regs[0x10]; // 0x40
  431. unsigned short sh2_regs[3]; // 0x60
  432. unsigned char pending_fb;
  433. unsigned char dirty_pal;
  434. unsigned int emu_flags;
  435. unsigned char sh2irq_mask[2];
  436. unsigned char sh2irqi[2]; // individual
  437. unsigned int sh2irqs; // common irqs
  438. unsigned short dmac_fifo[DMAC_FIFO_LEN];
  439. unsigned int dmac0_fifo_ptr;
  440. unsigned int pad;
  441. unsigned char comm_dirty_68k;
  442. unsigned char comm_dirty_sh2;
  443. unsigned char pwm_irq_cnt;
  444. unsigned char pad1;
  445. unsigned short pwm_p[2]; // pwm pos in fifo
  446. unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)
  447. unsigned int reserved[6];
  448. };
  449. struct Pico32xMem
  450. {
  451. unsigned char sdram[0x40000];
  452. #ifdef DRC_SH2
  453. unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];
  454. #endif
  455. unsigned short dram[2][0x20000/2]; // AKA fb
  456. union {
  457. unsigned char m68k_rom[0x100];
  458. unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE
  459. };
  460. #ifdef DRC_SH2
  461. unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];
  462. #endif
  463. unsigned char sh2_rom_m[0x800];
  464. unsigned char sh2_rom_s[0x400];
  465. unsigned short pal[0x100];
  466. unsigned short pal_native[0x100]; // converted to native (for renderer)
  467. signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame
  468. signed short pwm_fifo[2][4]; // [0] - current, others - fifo entries
  469. };
  470. // area.c
  471. extern void (*PicoLoadStateHook)(void);
  472. typedef struct {
  473. int chunk;
  474. int size;
  475. void *ptr;
  476. } carthw_state_chunk;
  477. extern carthw_state_chunk *carthw_chunks;
  478. #define CHUNK_CARTHW 64
  479. // cart.c
  480. extern int PicoCartResize(int newsize);
  481. extern void Byteswap(void *dst, const void *src, int len);
  482. extern void (*PicoCartMemSetup)(void);
  483. extern void (*PicoCartUnloadHook)(void);
  484. // debug.c
  485. int CM_compareRun(int cyc, int is_sub);
  486. // draw.c
  487. PICO_INTERNAL void PicoFrameStart(void);
  488. void PicoDrawSync(int to, int blank_last_line);
  489. void BackFill(int reg7, int sh);
  490. void FinalizeLine555(int sh, int line);
  491. extern int (*PicoScanBegin)(unsigned int num);
  492. extern int (*PicoScanEnd)(unsigned int num);
  493. extern int DrawScanline;
  494. #define MAX_LINE_SPRITES 29
  495. extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];
  496. extern void *DrawLineDestBase;
  497. extern int DrawLineDestIncrement;
  498. // draw2.c
  499. PICO_INTERNAL void PicoFrameFull();
  500. // mode4.c
  501. void PicoFrameStartMode4(void);
  502. void PicoLineMode4(int line);
  503. void PicoDoHighPal555M4(void);
  504. void PicoDrawSetOutputMode4(pdso_t which);
  505. // memory.c
  506. PICO_INTERNAL void PicoMemSetup(void);
  507. unsigned int PicoRead8_io(unsigned int a);
  508. unsigned int PicoRead16_io(unsigned int a);
  509. void PicoWrite8_io(unsigned int a, unsigned int d);
  510. void PicoWrite16_io(unsigned int a, unsigned int d);
  511. void p32x_dreq1_trigger(void);
  512. // pico/memory.c
  513. PICO_INTERNAL void PicoMemSetupPico(void);
  514. // cd/memory.c
  515. PICO_INTERNAL void PicoMemSetupCD(void);
  516. void PicoMemStateLoaded(void);
  517. // pico.c
  518. extern struct Pico Pico;
  519. extern struct PicoSRAM SRam;
  520. extern int PicoPadInt[2];
  521. extern int emustatus;
  522. extern int scanlines_total;
  523. extern void (*PicoResetHook)(void);
  524. extern void (*PicoLineHook)(void);
  525. PICO_INTERNAL int CheckDMA(void);
  526. PICO_INTERNAL void PicoDetectRegion(void);
  527. PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);
  528. // cd/pico.c
  529. PICO_INTERNAL void PicoInitMCD(void);
  530. PICO_INTERNAL void PicoExitMCD(void);
  531. PICO_INTERNAL void PicoPowerMCD(void);
  532. PICO_INTERNAL int PicoResetMCD(void);
  533. PICO_INTERNAL void PicoFrameMCD(void);
  534. // pico/pico.c
  535. PICO_INTERNAL void PicoInitPico(void);
  536. PICO_INTERNAL void PicoReratePico(void);
  537. // pico/xpcm.c
  538. PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);
  539. PICO_INTERNAL void PicoPicoPCMReset(void);
  540. PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);
  541. // sek.c
  542. PICO_INTERNAL void SekInit(void);
  543. PICO_INTERNAL int SekReset(void);
  544. PICO_INTERNAL void SekState(int *data);
  545. PICO_INTERNAL void SekSetRealTAS(int use_real);
  546. PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);
  547. PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);
  548. void SekStepM68k(void);
  549. void SekInitIdleDet(void);
  550. void SekFinishIdleDet(void);
  551. #if defined(CPU_CMP_R) || defined(CPU_CMP_W)
  552. void SekTrace(int is_s68k);
  553. #else
  554. #define SekTrace(x)
  555. #endif
  556. // cd/sek.c
  557. PICO_INTERNAL void SekInitS68k(void);
  558. PICO_INTERNAL int SekResetS68k(void);
  559. PICO_INTERNAL int SekInterruptS68k(int irq);
  560. // sound/sound.c
  561. PICO_INTERNAL void cdda_start_play();
  562. extern short cdda_out_buffer[2*1152];
  563. extern int PsndLen_exc_cnt;
  564. extern int PsndLen_exc_add;
  565. extern int timer_a_next_oflow, timer_a_step; // in z80 cycles
  566. extern int timer_b_next_oflow, timer_b_step;
  567. void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);
  568. void ym2612_pack_state(void);
  569. void ym2612_unpack_state(void);
  570. #define TIMER_NO_OFLOW 0x70000000
  571. // tA = 72 * (1024 - NA) / M
  572. #define TIMER_A_TICK_ZCYCLES 17203
  573. // tB = 1152 * (256 - NA) / M
  574. #define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura
  575. #define timers_cycle() \
  576. if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \
  577. timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \
  578. if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \
  579. timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \
  580. ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);
  581. #define timers_reset() \
  582. timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \
  583. timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \
  584. timer_b_step = TIMER_B_TICK_ZCYCLES * 256;
  585. // videoport.c
  586. PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);
  587. PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);
  588. PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);
  589. extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);
  590. // misc.c
  591. PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);
  592. PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);
  593. PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count
  594. PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);
  595. // eeprom.c
  596. void EEPROM_write8(unsigned int a, unsigned int d);
  597. void EEPROM_write16(unsigned int d);
  598. unsigned int EEPROM_read(void);
  599. // z80 functionality wrappers
  600. PICO_INTERNAL void z80_init(void);
  601. PICO_INTERNAL void z80_pack(void *data);
  602. PICO_INTERNAL int z80_unpack(const void *data);
  603. PICO_INTERNAL void z80_reset(void);
  604. PICO_INTERNAL void z80_exit(void);
  605. // cd/misc.c
  606. PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);
  607. PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);
  608. // cd/buffering.c
  609. PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);
  610. // sound/sound.c
  611. PICO_INTERNAL void PsndReset(void);
  612. PICO_INTERNAL void PsndDoDAC(int line_to);
  613. PICO_INTERNAL void PsndClear(void);
  614. PICO_INTERNAL void PsndGetSamples(int y);
  615. PICO_INTERNAL void PsndGetSamplesMS(void);
  616. extern int PsndDacLine;
  617. // sms.c
  618. #ifndef NO_SMS
  619. void PicoPowerMS(void);
  620. void PicoResetMS(void);
  621. void PicoMemSetupMS(void);
  622. void PicoStateLoadedMS(void);
  623. void PicoFrameMS(void);
  624. void PicoFrameDrawOnlyMS(void);
  625. #else
  626. #define PicoPowerMS()
  627. #define PicoResetMS()
  628. #define PicoMemSetupMS()
  629. #define PicoStateLoadedMS()
  630. #define PicoFrameMS()
  631. #define PicoFrameDrawOnlyMS()
  632. #endif
  633. // 32x/32x.c
  634. #ifndef NO_32X
  635. extern struct Pico32x Pico32x;
  636. enum p32x_event {
  637. P32X_EVENT_PWM,
  638. P32X_EVENT_FILLEND,
  639. P32X_EVENT_COUNT,
  640. };
  641. extern unsigned int event_times[P32X_EVENT_COUNT];
  642. void Pico32xInit(void);
  643. void PicoPower32x(void);
  644. void PicoReset32x(void);
  645. void Pico32xStartup(void);
  646. void PicoUnload32x(void);
  647. void PicoFrame32x(void);
  648. void Pico32xStateLoaded(int is_early);
  649. void p32x_sync_sh2s(unsigned int m68k_target);
  650. void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);
  651. void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);
  652. void p32x_reset_sh2s(void);
  653. void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);
  654. void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);
  655. // 32x/memory.c
  656. struct Pico32xMem *Pico32xMem;
  657. unsigned int PicoRead8_32x(unsigned int a);
  658. unsigned int PicoRead16_32x(unsigned int a);
  659. void PicoWrite8_32x(unsigned int a, unsigned int d);
  660. void PicoWrite16_32x(unsigned int a, unsigned int d);
  661. void PicoMemSetup32x(void);
  662. void Pico32xSwapDRAM(int b);
  663. void Pico32xMemStateLoaded(void);
  664. void p32x_m68k_poll_event(unsigned int flags);
  665. void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);
  666. // 32x/draw.c
  667. void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);
  668. void FinalizeLine32xRGB555(int sh, int line);
  669. void PicoDraw32xLayer(int offs, int lines, int mdbg);
  670. void PicoDraw32xLayerMdOnly(int offs, int lines);
  671. extern int (*PicoScan32xBegin)(unsigned int num);
  672. extern int (*PicoScan32xEnd)(unsigned int num);
  673. enum {
  674. PDM32X_OFF,
  675. PDM32X_32X_ONLY,
  676. PDM32X_BOTH,
  677. };
  678. extern int Pico32xDrawMode;
  679. // 32x/pwm.c
  680. unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,
  681. unsigned int m68k_cycles);
  682. void p32x_pwm_write16(unsigned int a, unsigned int d,
  683. SH2 *sh2, unsigned int m68k_cycles);
  684. void p32x_pwm_update(int *buf32, int length, int stereo);
  685. void p32x_pwm_ctl_changed(void);
  686. void p32x_pwm_schedule(unsigned int m68k_now);
  687. void p32x_pwm_schedule_sh2(SH2 *sh2);
  688. void p32x_pwm_irq_event(unsigned int m68k_now);
  689. void p32x_pwm_state_loaded(void);
  690. // 32x/sh2soc.c
  691. void p32x_dreq0_trigger(void);
  692. void p32x_dreq1_trigger(void);
  693. void p32x_timers_recalc(void);
  694. void p32x_timers_do(unsigned int m68k_slice);
  695. unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);
  696. unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);
  697. unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);
  698. void sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);
  699. void sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);
  700. void sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);
  701. #else
  702. #define Pico32xInit()
  703. #define PicoPower32x()
  704. #define PicoReset32x()
  705. #define PicoFrame32x()
  706. #define PicoUnload32x()
  707. #define Pico32xStateLoaded()
  708. #define FinalizeLine32xRGB555 NULL
  709. #define p32x_pwm_update(...)
  710. #define p32x_timers_recalc()
  711. #endif
  712. /* avoid dependency on newer glibc */
  713. static __inline int isspace_(int c)
  714. {
  715. return (0x09 <= c && c <= 0x0d) || c == ' ';
  716. }
  717. #ifndef ARRAY_SIZE
  718. #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
  719. #endif
  720. // emulation event logging
  721. #ifndef EL_LOGMASK
  722. # ifdef __x86_64__ // HACK
  723. # define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)
  724. # else
  725. # define EL_LOGMASK (EL_STATUS)
  726. # endif
  727. #endif
  728. #define EL_HVCNT 0x00000001 /* hv counter reads */
  729. #define EL_SR 0x00000002 /* SR reads */
  730. #define EL_INTS 0x00000004 /* ints and acks */
  731. #define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */
  732. #define EL_INTSW 0x00000010 /* log irq switching on/off */
  733. #define EL_ASVDP 0x00000020 /* VDP accesses during active scan */
  734. #define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */
  735. #define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */
  736. #define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */
  737. #define EL_SRAMIO 0x00000200 /* sram i/o */
  738. #define EL_EEPROM 0x00000400 /* eeprom debug */
  739. #define EL_UIO 0x00000800 /* unmapped i/o */
  740. #define EL_IO 0x00001000 /* all i/o */
  741. #define EL_CDPOLL 0x00002000 /* MCD: log poll detection */
  742. #define EL_SVP 0x00004000 /* SVP stuff */
  743. #define EL_PICOHW 0x00008000 /* Pico stuff */
  744. #define EL_IDLE 0x00010000 /* idle loop det. */
  745. #define EL_CDREGS 0x00020000 /* MCD: register access */
  746. #define EL_CDREG3 0x00040000 /* MCD: register 3 only */
  747. #define EL_32X 0x00080000
  748. #define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */
  749. #define EL_32XP 0x00200000 /* 32X peripherals */
  750. #define EL_STATUS 0x40000000 /* status messages */
  751. #define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */
  752. #if EL_LOGMASK
  753. #define elprintf(w,f,...) \
  754. do { \
  755. if ((w) & EL_LOGMASK) \
  756. lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \
  757. } while (0)
  758. #elif defined(_MSC_VER)
  759. #define elprintf
  760. #else
  761. #define elprintf(w,f,...)
  762. #endif
  763. // profiling
  764. #ifdef PPROF
  765. #include <platform/linux/pprof.h>
  766. #else
  767. #define pprof_init()
  768. #define pprof_finish()
  769. #define pprof_start(x)
  770. #define pprof_end(...)
  771. #define pprof_end_sub(...)
  772. #endif
  773. #ifdef EVT_LOG
  774. enum evt {
  775. EVT_FRAME_START,
  776. EVT_NEXT_LINE,
  777. EVT_RUN_START,
  778. EVT_RUN_END,
  779. EVT_POLL_START,
  780. EVT_POLL_END,
  781. EVT_CNT
  782. };
  783. enum evt_cpu {
  784. EVT_M68K,
  785. EVT_S68K,
  786. EVT_MSH2,
  787. EVT_SSH2,
  788. EVT_CPU_CNT
  789. };
  790. void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);
  791. void pevt_dump(void);
  792. #define pevt_log_m68k(e) \
  793. pevt_log(SekCyclesDoneT(), EVT_M68K, e)
  794. #define pevt_log_m68k_o(e) \
  795. pevt_log(SekCyclesDoneT2(), EVT_M68K, e)
  796. #define pevt_log_sh2(sh2, e) \
  797. pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)
  798. #define pevt_log_sh2_o(sh2, e) \
  799. pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)
  800. #else
  801. #define pevt_log(c, e)
  802. #define pevt_log_m68k(e)
  803. #define pevt_log_m68k_o(e)
  804. #define pevt_log_sh2(sh2, e)
  805. #define pevt_log_sh2_o(sh2, e)
  806. #define pevt_dump()
  807. #endif
  808. // misc
  809. #ifdef _MSC_VER
  810. #define cdprintf
  811. #else
  812. #define cdprintf(x...)
  813. #endif
  814. #ifdef __i386__
  815. #define REGPARM(x) __attribute__((regparm(x)))
  816. #else
  817. #define REGPARM(x)
  818. #endif
  819. #ifdef __GNUC__
  820. #define NOINLINE __attribute__((noinline))
  821. #else
  822. #define NOINLINE
  823. #endif
  824. #ifdef __cplusplus
  825. } // End of extern "C"
  826. #endif
  827. #endif // PICO_INTERNAL_INCLUDED