32x.c 15 KB

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  1. /*
  2. * PicoDrive
  3. * (C) notaz, 2009,2010,2013
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. */
  8. #include "../pico_int.h"
  9. #include "../sound/ym2612.h"
  10. #include "../../cpu/sh2/compiler.h"
  11. struct Pico32x Pico32x;
  12. SH2 sh2s[2];
  13. #define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_SLEEP)
  14. static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
  15. {
  16. if (sh2->pending_irl > sh2->pending_int_irq) {
  17. elprintf_sh2(sh2, EL_32X, "ack/irl %d @ %08x",
  18. level, sh2_pc(sh2));
  19. return 64 + sh2->pending_irl / 2;
  20. } else {
  21. elprintf_sh2(sh2, EL_32X, "ack/int %d/%d @ %08x",
  22. level, sh2->pending_int_vector, sh2_pc(sh2));
  23. sh2->pending_int_irq = 0; // auto-clear
  24. sh2->pending_level = sh2->pending_irl;
  25. return sh2->pending_int_vector;
  26. }
  27. }
  28. // MUST specify active_sh2 when called from sh2 memhandlers
  29. void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
  30. {
  31. int irqs, mlvl = 0, slvl = 0;
  32. int mrun, srun;
  33. if (active_sh2 != NULL)
  34. m68k_cycles = sh2_cycles_done_m68k(active_sh2);
  35. // msh2
  36. irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0];
  37. while ((irqs >>= 1))
  38. mlvl++;
  39. mlvl *= 2;
  40. // ssh2
  41. irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1];
  42. while ((irqs >>= 1))
  43. slvl++;
  44. slvl *= 2;
  45. mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 == &msh2);
  46. if (mrun) {
  47. p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
  48. if (active_sh2 == &msh2)
  49. sh2_end_run(active_sh2, 1);
  50. }
  51. srun = sh2_irl_irq(&ssh2, slvl, active_sh2 == &ssh2);
  52. if (srun) {
  53. p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
  54. if (active_sh2 == &ssh2)
  55. sh2_end_run(active_sh2, 1);
  56. }
  57. elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
  58. }
  59. // the mask register is inconsistent, CMD is supposed to be a mask,
  60. // while others are actually irq trigger enables?
  61. // TODO: test on hw..
  62. void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask)
  63. {
  64. Pico32x.sh2irqs |= mask & P32XI_VRES;
  65. Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3);
  66. Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3);
  67. p32x_update_irls(sh2, m68k_cycles);
  68. }
  69. void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles)
  70. {
  71. if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1))
  72. Pico32x.sh2irqi[0] |= P32XI_CMD;
  73. else
  74. Pico32x.sh2irqi[0] &= ~P32XI_CMD;
  75. if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2))
  76. Pico32x.sh2irqi[1] |= P32XI_CMD;
  77. else
  78. Pico32x.sh2irqi[1] &= ~P32XI_CMD;
  79. p32x_update_irls(sh2, m68k_cycles);
  80. }
  81. void Pico32xStartup(void)
  82. {
  83. elprintf(EL_STATUS|EL_32X, "32X startup");
  84. // TODO: OOM handling
  85. PicoAHW |= PAHW_32X;
  86. sh2_init(&msh2, 0, &ssh2);
  87. msh2.irq_callback = sh2_irq_cb;
  88. sh2_init(&ssh2, 1, &msh2);
  89. ssh2.irq_callback = sh2_irq_cb;
  90. PicoMemSetup32x();
  91. p32x_pwm_ctl_changed();
  92. p32x_timers_recalc();
  93. if (!Pico.m.pal)
  94. Pico32x.vdp_regs[0] |= P32XV_nPAL;
  95. rendstatus_old = -1;
  96. emu_32x_startup();
  97. }
  98. #define HWSWAP(x) (((x) << 16) | ((x) >> 16))
  99. void p32x_reset_sh2s(void)
  100. {
  101. elprintf(EL_32X, "sh2 reset");
  102. sh2_reset(&msh2);
  103. sh2_reset(&ssh2);
  104. sh2_peripheral_reset(&msh2);
  105. sh2_peripheral_reset(&ssh2);
  106. // if we don't have BIOS set, perform it's work here.
  107. // MSH2
  108. if (p32x_bios_m == NULL) {
  109. unsigned int idl_src, idl_dst, idl_size; // initial data load
  110. unsigned int vbr;
  111. // initial data
  112. idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000;
  113. idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000;
  114. idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc));
  115. if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize ||
  116. idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) {
  117. elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x",
  118. idl_src, idl_dst, idl_size);
  119. }
  120. else
  121. memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size);
  122. // GBR/VBR
  123. vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8));
  124. sh2_set_gbr(0, 0x20004000);
  125. sh2_set_vbr(0, vbr);
  126. // checksum and M_OK
  127. Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e);
  128. // program will set M_OK
  129. }
  130. // SSH2
  131. if (p32x_bios_s == NULL) {
  132. unsigned int vbr;
  133. // GBR/VBR
  134. vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec));
  135. sh2_set_gbr(1, 0x20004000);
  136. sh2_set_vbr(1, vbr);
  137. // program will set S_OK
  138. }
  139. msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone();
  140. }
  141. void Pico32xInit(void)
  142. {
  143. if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0)
  144. Pico32xSetClocks(PICO_MSH2_HZ, 0);
  145. if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0)
  146. Pico32xSetClocks(0, PICO_MSH2_HZ);
  147. }
  148. void PicoPower32x(void)
  149. {
  150. memset(&Pico32x, 0, sizeof(Pico32x));
  151. Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified
  152. Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN;
  153. Pico32x.sh2_regs[0] = P32XS2_ADEN;
  154. }
  155. void PicoUnload32x(void)
  156. {
  157. if (Pico32xMem != NULL)
  158. plat_munmap(Pico32xMem, sizeof(*Pico32xMem));
  159. Pico32xMem = NULL;
  160. sh2_finish(&msh2);
  161. sh2_finish(&ssh2);
  162. PicoAHW &= ~PAHW_32X;
  163. }
  164. void PicoReset32x(void)
  165. {
  166. if (PicoAHW & PAHW_32X) {
  167. msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone();
  168. p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VRES);
  169. p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
  170. p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
  171. p32x_pwm_ctl_changed();
  172. p32x_timers_recalc();
  173. }
  174. }
  175. static void p32x_start_blank(void)
  176. {
  177. if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) {
  178. int offs, lines;
  179. pprof_start(draw);
  180. offs = 8; lines = 224;
  181. if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) {
  182. offs = 0;
  183. lines = 240;
  184. }
  185. // XXX: no proper handling of 32col mode..
  186. if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking
  187. (Pico.video.reg[12] & 1) && // 40col mode
  188. (PicoDrawMask & PDRAW_32X_ON))
  189. {
  190. int md_bg = Pico.video.reg[7] & 0x3f;
  191. // we draw full layer (not line-by-line)
  192. PicoDraw32xLayer(offs, lines, md_bg);
  193. }
  194. else if (Pico32xDrawMode != PDM32X_32X_ONLY)
  195. PicoDraw32xLayerMdOnly(offs, lines);
  196. pprof_end(draw);
  197. }
  198. // enter vblank
  199. Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN;
  200. // FB swap waits until vblank
  201. if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) {
  202. Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS;
  203. Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb;
  204. Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
  205. }
  206. p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VINT);
  207. p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
  208. p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
  209. }
  210. void p32x_schedule_hint(SH2 *sh2, int m68k_cycles)
  211. {
  212. // rather rough, 32x hint is useless in practice
  213. int after;
  214. if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 4))
  215. return; // nobody cares
  216. // note: when Pico.m.scanline is 224, SH2s might
  217. // still be at scanline 93 (or so)
  218. if (!(Pico32x.sh2_regs[0] & 0x80) && Pico.m.scanline > 224)
  219. return;
  220. after = (Pico32x.sh2_regs[4 / 2] + 1) * 488;
  221. if (sh2 != NULL)
  222. p32x_event_schedule_sh2(sh2, P32X_EVENT_HINT, after);
  223. else
  224. p32x_event_schedule(m68k_cycles, P32X_EVENT_HINT, after);
  225. }
  226. /* events */
  227. static void fillend_event(unsigned int now)
  228. {
  229. Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN;
  230. p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, now);
  231. p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now);
  232. }
  233. static void hint_event(unsigned int now)
  234. {
  235. p32x_trigger_irq(NULL, now, P32XI_HINT);
  236. p32x_schedule_hint(NULL, now);
  237. }
  238. typedef void (event_cb)(unsigned int now);
  239. /* times are in m68k (7.6MHz) cycles */
  240. unsigned int p32x_event_times[P32X_EVENT_COUNT];
  241. static unsigned int event_time_next;
  242. static event_cb *p32x_event_cbs[P32X_EVENT_COUNT] = {
  243. [P32X_EVENT_PWM] = p32x_pwm_irq_event,
  244. [P32X_EVENT_FILLEND] = fillend_event,
  245. [P32X_EVENT_HINT] = hint_event,
  246. };
  247. // schedule event at some time 'after', in m68k clocks
  248. void p32x_event_schedule(unsigned int now, enum p32x_event event, int after)
  249. {
  250. unsigned int when;
  251. when = (now + after) | 1;
  252. elprintf(EL_32X, "32x: new event #%u %u->%u", event, now, when);
  253. p32x_event_times[event] = when;
  254. if (event_time_next == 0 || CYCLES_GT(event_time_next, when))
  255. event_time_next = when;
  256. }
  257. void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after)
  258. {
  259. unsigned int now = sh2_cycles_done_m68k(sh2);
  260. int left_to_next;
  261. p32x_event_schedule(now, event, after);
  262. left_to_next = (event_time_next - now) * 3;
  263. sh2_end_run(sh2, left_to_next);
  264. }
  265. static void p32x_run_events(unsigned int until)
  266. {
  267. int oldest, oldest_diff, time;
  268. int i, diff;
  269. while (1) {
  270. oldest = -1, oldest_diff = 0x7fffffff;
  271. for (i = 0; i < P32X_EVENT_COUNT; i++) {
  272. if (p32x_event_times[i]) {
  273. diff = p32x_event_times[i] - until;
  274. if (diff < oldest_diff) {
  275. oldest_diff = diff;
  276. oldest = i;
  277. }
  278. }
  279. }
  280. if (oldest_diff <= 0) {
  281. time = p32x_event_times[oldest];
  282. p32x_event_times[oldest] = 0;
  283. elprintf(EL_32X, "32x: run event #%d %u", oldest, time);
  284. p32x_event_cbs[oldest](time);
  285. }
  286. else if (oldest_diff < 0x7fffffff) {
  287. event_time_next = p32x_event_times[oldest];
  288. break;
  289. }
  290. else {
  291. event_time_next = 0;
  292. break;
  293. }
  294. }
  295. if (oldest != -1)
  296. elprintf(EL_32X, "32x: next event #%d at %u",
  297. oldest, event_time_next);
  298. }
  299. static inline void run_sh2(SH2 *sh2, int m68k_cycles)
  300. {
  301. int cycles, done;
  302. pevt_log_sh2_o(sh2, EVT_RUN_START);
  303. sh2->state |= SH2_STATE_RUN;
  304. cycles = C_M68K_TO_SH2(*sh2, m68k_cycles);
  305. elprintf_sh2(sh2, EL_32X, "+run %u %d @%08x",
  306. sh2->m68krcycles_done, cycles, sh2->pc);
  307. done = sh2_execute(sh2, cycles, PicoOpt & POPT_EN_DRC);
  308. sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done);
  309. sh2->state &= ~SH2_STATE_RUN;
  310. pevt_log_sh2_o(sh2, EVT_RUN_END);
  311. elprintf_sh2(sh2, EL_32X, "-run %u %d",
  312. sh2->m68krcycles_done, done);
  313. }
  314. // sync other sh2 to this one
  315. // note: recursive call
  316. void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
  317. {
  318. SH2 *osh2 = sh2->other_sh2;
  319. int left_to_event;
  320. int m68k_cycles;
  321. if (osh2->state & SH2_STATE_RUN)
  322. return;
  323. m68k_cycles = m68k_target - osh2->m68krcycles_done;
  324. if (m68k_cycles < 200)
  325. return;
  326. if (osh2->state & SH2_IDLE_STATES) {
  327. osh2->m68krcycles_done = m68k_target;
  328. return;
  329. }
  330. elprintf_sh2(osh2, EL_32X, "sync to %u %d",
  331. m68k_target, m68k_cycles);
  332. run_sh2(osh2, m68k_cycles);
  333. // there might be new event to schedule current sh2 to
  334. if (event_time_next) {
  335. left_to_event = event_time_next - m68k_target;
  336. left_to_event *= 3;
  337. if (sh2_cycles_left(sh2) > left_to_event) {
  338. if (left_to_event < 1)
  339. left_to_event = 1;
  340. sh2_end_run(sh2, left_to_event);
  341. }
  342. }
  343. }
  344. #define sync_sh2s_normal p32x_sync_sh2s
  345. //#define sync_sh2s_lockstep p32x_sync_sh2s
  346. /* most timing is in 68k clock */
  347. void sync_sh2s_normal(unsigned int m68k_target)
  348. {
  349. unsigned int now, target, timer_cycles;
  350. int cycles;
  351. elprintf(EL_32X, "sh2 sync to %u", m68k_target);
  352. if (!(Pico32x.regs[0] & P32XS_nRES)) {
  353. msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target;
  354. return; // rare
  355. }
  356. now = msh2.m68krcycles_done;
  357. if (CYCLES_GT(now, ssh2.m68krcycles_done))
  358. now = ssh2.m68krcycles_done;
  359. timer_cycles = now;
  360. while (CYCLES_GT(m68k_target, now))
  361. {
  362. if (event_time_next && CYCLES_GE(now, event_time_next))
  363. p32x_run_events(now);
  364. target = m68k_target;
  365. if (event_time_next && CYCLES_GT(target, event_time_next))
  366. target = event_time_next;
  367. while (CYCLES_GT(target, now))
  368. {
  369. elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target,
  370. target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done,
  371. m68k_target - now, Pico32x.emu_flags);
  372. if (!(ssh2.state & SH2_IDLE_STATES)) {
  373. cycles = target - ssh2.m68krcycles_done;
  374. if (cycles > 0) {
  375. run_sh2(&ssh2, cycles);
  376. if (event_time_next && CYCLES_GT(target, event_time_next))
  377. target = event_time_next;
  378. }
  379. }
  380. if (!(msh2.state & SH2_IDLE_STATES)) {
  381. cycles = target - msh2.m68krcycles_done;
  382. if (cycles > 0) {
  383. run_sh2(&msh2, cycles);
  384. if (event_time_next && CYCLES_GT(target, event_time_next))
  385. target = event_time_next;
  386. }
  387. }
  388. now = target;
  389. if (!(msh2.state & SH2_IDLE_STATES)) {
  390. if (CYCLES_GT(now, msh2.m68krcycles_done))
  391. now = msh2.m68krcycles_done;
  392. }
  393. if (!(ssh2.state & SH2_IDLE_STATES)) {
  394. if (CYCLES_GT(now, ssh2.m68krcycles_done))
  395. now = ssh2.m68krcycles_done;
  396. }
  397. }
  398. p32x_timers_do(now - timer_cycles);
  399. timer_cycles = now;
  400. }
  401. // advance idle CPUs
  402. if (msh2.state & SH2_IDLE_STATES) {
  403. if (CYCLES_GT(m68k_target, msh2.m68krcycles_done))
  404. msh2.m68krcycles_done = m68k_target;
  405. }
  406. if (ssh2.state & SH2_IDLE_STATES) {
  407. if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done))
  408. ssh2.m68krcycles_done = m68k_target;
  409. }
  410. }
  411. #define STEP_68K 24
  412. void sync_sh2s_lockstep(unsigned int m68k_target)
  413. {
  414. unsigned int mcycles;
  415. mcycles = msh2.m68krcycles_done;
  416. if (ssh2.m68krcycles_done < mcycles)
  417. mcycles = ssh2.m68krcycles_done;
  418. while (mcycles < m68k_target) {
  419. mcycles += STEP_68K;
  420. sync_sh2s_normal(mcycles);
  421. }
  422. }
  423. #define CPUS_RUN(m68k_cycles) do { \
  424. SekRunM68k(m68k_cycles); \
  425. if ((Pico32x.emu_flags & P32XF_Z80_32X_IO) && Pico.m.z80Run \
  426. && !Pico.m.z80_reset && (PicoOpt & POPT_EN_Z80)) \
  427. PicoSyncZ80(SekCyclesDone()); \
  428. if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
  429. p32x_sync_sh2s(SekCyclesDone()); \
  430. } while (0)
  431. #define PICO_32X
  432. #include "../pico_cmn.c"
  433. void PicoFrame32x(void)
  434. {
  435. Pico.m.scanline = 0;
  436. Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
  437. if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
  438. Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
  439. if (!(Pico32x.sh2_regs[0] & 0x80))
  440. p32x_schedule_hint(NULL, SekCyclesDone());
  441. p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
  442. p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
  443. PicoFrameStart();
  444. PicoFrameHints();
  445. sh2_drc_frame();
  446. elprintf(EL_32X, "poll: %02x %02x %02x",
  447. Pico32x.emu_flags & 3, msh2.state, ssh2.state);
  448. }
  449. // calculate multipliers against 68k clock (7670442)
  450. // normally * 3, but effectively slower due to high latencies everywhere
  451. // however using something lower breaks MK2 animations
  452. void Pico32xSetClocks(int msh2_hz, int ssh2_hz)
  453. {
  454. float m68k_clk = (float)(OSC_NTSC / 7);
  455. if (msh2_hz > 0) {
  456. msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
  457. msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz);
  458. }
  459. if (ssh2_hz > 0) {
  460. ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
  461. ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz);
  462. }
  463. }
  464. void Pico32xStateLoaded(int is_early)
  465. {
  466. if (is_early) {
  467. Pico32xMemStateLoaded();
  468. return;
  469. }
  470. sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCyclesDone();
  471. p32x_update_irls(NULL, SekCyclesDone());
  472. p32x_pwm_state_loaded();
  473. p32x_run_events(SekCyclesDone());
  474. }
  475. // vim:shiftwidth=2:ts=2:expandtab