sh2.h 3.5 KB

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  1. #ifndef __SH2_H__
  2. #define __SH2_H__
  3. #if !defined(REGPARM) && defined(__i386__)
  4. #define REGPARM(x) __attribute__((regparm(x)))
  5. #else
  6. #define REGPARM(x)
  7. #endif
  8. // registers - matches structure order
  9. typedef enum {
  10. SHR_R0 = 0, SHR_SP = 15,
  11. SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
  12. SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
  13. } sh2_reg_e;
  14. typedef struct SH2_
  15. {
  16. unsigned int r[16]; // 00
  17. unsigned int pc; // 40
  18. unsigned int ppc;
  19. unsigned int pr;
  20. unsigned int sr;
  21. unsigned int gbr, vbr; // 50
  22. unsigned int mach, macl; // 58
  23. // common
  24. const void *read8_map; // 60
  25. const void *read16_map;
  26. const void **write8_tab;
  27. const void **write16_tab;
  28. // drc stuff
  29. int drc_tmp; // 70
  30. int irq_cycles;
  31. void *p_bios; // convenience pointers
  32. void *p_da;
  33. void *p_sdram; // 80
  34. void *p_rom;
  35. unsigned int pdb_io_csum[2];
  36. #define SH2_STATE_RUN (1 << 0) // to prevent recursion
  37. #define SH2_STATE_SLEEP (1 << 1)
  38. #define SH2_STATE_CPOLL (1 << 2) // polling comm regs
  39. #define SH2_STATE_VPOLL (1 << 3) // polling VDP
  40. unsigned int state;
  41. unsigned int poll_addr;
  42. int poll_cycles;
  43. int poll_cnt;
  44. // interpreter stuff
  45. int icount; // cycles left in current timeslice
  46. unsigned int ea;
  47. unsigned int delay;
  48. unsigned int test_irq;
  49. int pending_level; // MAX(pending_irl, pending_int_irq)
  50. int pending_irl;
  51. int pending_int_irq; // internal irq
  52. int pending_int_vector;
  53. int REGPARM(2) (*irq_callback)(struct SH2_ *sh2, int level);
  54. int is_slave;
  55. unsigned int cycles_timeslice;
  56. struct SH2_ *other_sh2;
  57. // we use 68k reference cycles for easier sync
  58. unsigned int m68krcycles_done;
  59. unsigned int mult_m68k_to_sh2;
  60. unsigned int mult_sh2_to_m68k;
  61. unsigned char data_array[0x1000]; // cache (can be used as RAM)
  62. unsigned int peri_regs[0x200/4]; // periphereal regs
  63. } SH2;
  64. #define CYCLE_MULT_SHIFT 10
  65. #define C_M68K_TO_SH2(xsh2, c) \
  66. ((int)((c) * (xsh2).mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)
  67. #define C_SH2_TO_M68K(xsh2, c) \
  68. ((int)((c + 3) * (xsh2).mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)
  69. int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);
  70. void sh2_finish(SH2 *sh2);
  71. void sh2_reset(SH2 *sh2);
  72. int sh2_irl_irq(SH2 *sh2, int level, int nested_call);
  73. void sh2_internal_irq(SH2 *sh2, int level, int vector);
  74. void sh2_do_irq(SH2 *sh2, int level, int vector);
  75. void sh2_pack(const SH2 *sh2, unsigned char *buff);
  76. void sh2_unpack(SH2 *sh2, const unsigned char *buff);
  77. int sh2_execute_drc(SH2 *sh2c, int cycles);
  78. int sh2_execute_interpreter(SH2 *sh2c, int cycles);
  79. static inline int sh2_execute(SH2 *sh2, int cycles, int use_drc)
  80. {
  81. int ret;
  82. sh2->cycles_timeslice = cycles;
  83. #ifdef DRC_SH2
  84. if (use_drc)
  85. ret = sh2_execute_drc(sh2, cycles);
  86. else
  87. #endif
  88. ret = sh2_execute_interpreter(sh2, cycles);
  89. return sh2->cycles_timeslice - ret;
  90. }
  91. // regs, pending_int*, cycles, reserved
  92. #define SH2_STATE_SIZE ((24 + 2 + 2 + 12) * 4)
  93. // pico memhandlers
  94. // XXX: move somewhere else
  95. unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);
  96. unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);
  97. unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);
  98. void REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);
  99. void REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);
  100. void REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);
  101. // debug
  102. #ifdef DRC_CMP
  103. void do_sh2_trace(SH2 *current, int cycles);
  104. void do_sh2_cmp(SH2 *current);
  105. #endif
  106. #endif /* __SH2_H__ */