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@@ -158,7 +158,7 @@ int (*PicoDmaHook)(u32 source, int len, unsigned short **base, u32 *mask) = NULL
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* full total==4
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* wait total>4
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* Conditions:
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- * fifo_slot is always behind slot2cyc[cycles]. Advancing it beyond cycles
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+ * fifo_slot is normally behind slot2cyc[cycles]. Advancing it beyond cycles
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* implies blocking the 68k up to that slot.
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*
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* A FIFO write goes to the end of the FIFO queue, but DMA running in background
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@@ -213,25 +213,23 @@ static __inline int AdvanceFIFOEntry(struct VdpFIFO *vf, struct PicoVideo *pv, i
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if (!(vf->fifo_queue[vf->fifo_qx] & FQ_BGDMA))
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vf->fifo_total -= ((cnt & b) + l) >> b;
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cnt -= l;
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+ pv->fifo_cnt = cnt;
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// if entry has been processed...
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if (cnt == 0) {
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// remove entry from FIFO
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- if (vf->fifo_ql) {
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- vf->fifo_queue[vf->fifo_qx] = 0;
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- vf->fifo_qx = (vf->fifo_qx+1) & 7, vf->fifo_ql --;
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- }
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+ vf->fifo_queue[vf->fifo_qx] = 0;
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+ vf->fifo_qx = (vf->fifo_qx+1) & 7, vf->fifo_ql --;
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// start processing for next entry if there is one
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if (vf->fifo_ql) {
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b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;
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- cnt = (vf->fifo_queue[vf->fifo_qx] >> 3) << b;
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+ pv->fifo_cnt = (vf->fifo_queue[vf->fifo_qx] >> 3) << b;
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} else { // FIFO empty
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pv->status &= ~PVS_FIFORUN;
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vf->fifo_total = 0;
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}
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}
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- pv->fifo_cnt = cnt;
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return l;
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}
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@@ -363,11 +361,11 @@ int PicoVideoFIFOWrite(int count, int flags, unsigned sr_mask,unsigned sr_flags)
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// XXX if interrupting a DMA fill, fill data changes
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if (x == vf->fifo_qx) { // overtaking to queue head?
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int f = vf->fifo_queue[x] & 7;
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- vf->fifo_queue[(x+1) & 7] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;
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+ vf->fifo_queue[x] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;
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pv->status &= ~PVS_FIFORUN;
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- } else
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- // push background DMA back
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- vf->fifo_queue[(x+1) & 7] = vf->fifo_queue[x];
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+ }
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+ // push background DMA back
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+ vf->fifo_queue[(x+1) & 7] = vf->fifo_queue[x];
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x = (x-1) & 7;
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}
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@@ -1152,16 +1150,17 @@ void PicoVideoLoad(void)
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// convert former dma_xfers (why was this in PicoMisc anyway?)
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if (Pico.m.dma_xfers) {
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pv->status |= SR_DMA;
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- pv->fifo_cnt = Pico.m.dma_xfers * (b ? 2 : 1);
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+ pv->fifo_cnt = Pico.m.dma_xfers << b;
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Pico.m.dma_xfers = 0;
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}
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// make an entry in the FIFO if there are outstanding transfers
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vf->fifo_ql = vf->fifo_total = 0;
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if (pv->fifo_cnt) {
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pv->status |= PVS_FIFORUN|PVS_CPUWR;
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- vf->fifo_total = (pv->fifo_cnt + (b)) >> b;
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- if (pv->status & SR_DMA)
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- b |= (pv->status & (PVS_DMAFILL|PVS_DMABG)) ? FQ_BGDMA : FQ_FGDMA;
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+ if (!(pv->status & PVS_DMABG))
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+ vf->fifo_total = (pv->fifo_cnt + b) >> b;
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+ if ((pv->status & SR_DMA) && !(pv->status & PVS_DMAFILL))
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+ b |= (pv->status & PVS_DMABG) ? FQ_BGDMA : FQ_FGDMA;
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vf->fifo_queue[vf->fifo_qx] = (vf->fifo_total << 3) | b;
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vf->fifo_ql = 1;
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}
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