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@@ -47,7 +47,7 @@ static const char str_mars[] = "MARS";
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void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
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struct Pico32xMem *Pico32xMem;
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-static void bank_switch(int b);
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+static void bank_switch_rom_68k(int b);
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// addressing byte in 16bit reg
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#define REG8IN16(ptr, offs) ((u8 *)ptr)[(offs) ^ 1]
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@@ -276,7 +276,7 @@ static void p32x_reg_write8(u32 a, u32 d)
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d &= 3;
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if (r[0x04 / 2] != d) {
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r[0x04 / 2] = d;
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- bank_switch(d);
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+ bank_switch_rom_68k(d);
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}
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return;
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case 0x06: // ignored, always 0
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@@ -862,7 +862,7 @@ static void PicoWrite8_32x_on(u32 a, u32 d)
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else
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PicoWrite8_io(a, d);
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if (a == 0xa130f1)
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- bank_switch(Pico32x.regs[4 / 2]);
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+ bank_switch_rom_68k(Pico32x.regs[4 / 2]);
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return;
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}
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@@ -900,7 +900,7 @@ static void PicoWrite16_32x_on(u32 a, u32 d)
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else
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PicoWrite16_io(a, d);
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if (a == 0xa130f0)
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- bank_switch(Pico32x.regs[4 / 2]);
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+ bank_switch_rom_68k(Pico32x.regs[4 / 2]);
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return;
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}
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@@ -1145,9 +1145,9 @@ static void bank_map_handler(void)
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cpu68k_map_set(m68k_read16_map, 0x900000, 0x9fffff, PicoRead16_bank, 1);
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}
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-static void bank_switch(int b)
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+static void bank_switch_rom_68k(int b)
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{
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- unsigned int rs, bank;
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+ unsigned int rs, bank, bank2;
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if (Pico.m.ncart_in)
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return;
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@@ -1164,15 +1164,25 @@ static void bank_switch(int b)
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return;
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}
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- // 32X ROM (unbanked, XXX: consider mirroring?)
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+ // 32X ROM (XXX: consider mirroring?)
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rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
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- rs -= bank;
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- if (rs > 0x100000)
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- rs = 0x100000;
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- cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
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- cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
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-
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- elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
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+ if (!carthw_ssf2_active) {
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+ rs -= bank;
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+ if (rs > 0x100000)
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+ rs = 0x100000;
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+ cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
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+ cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
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+ elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
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+ }
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+ else {
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+ bank = bank >> 19;
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+ bank2 = carthw_ssf2_banks[bank + 0] << 19;
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+ cpu68k_map_set(m68k_read8_map, 0x900000, 0x97ffff, Pico.rom + bank2, 0);
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+ cpu68k_map_set(m68k_read16_map, 0x900000, 0x97ffff, Pico.rom + bank2, 0);
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+ bank2 = carthw_ssf2_banks[bank + 1] << 19;
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+ cpu68k_map_set(m68k_read8_map, 0x980000, 0x9fffff, Pico.rom + bank2, 0);
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+ cpu68k_map_set(m68k_read16_map, 0x980000, 0x9fffff, Pico.rom + bank2, 0);
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+ }
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}
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// -----------------------------------------------------------------
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@@ -1234,6 +1244,13 @@ static u32 sh2_read8_da(u32 a, SH2 *sh2)
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return sh2->data_array[(a & 0xfff) ^ 1];
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}
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+// for ssf2
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+static u32 sh2_read8_rom(u32 a, SH2 *sh2)
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+{
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+ u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19;
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+ return Pico.rom[(bank + (a & 0x7ffff)) ^ 1];
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+}
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+
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// read16
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static u32 sh2_read16_unmapped(u32 a, SH2 *sh2)
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{
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@@ -1284,6 +1301,12 @@ static u32 sh2_read16_da(u32 a, SH2 *sh2)
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return ((u16 *)sh2->data_array)[(a & 0xfff) / 2];
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}
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+static u32 sh2_read16_rom(u32 a, SH2 *sh2)
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+{
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+ u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19;
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+ return *(u16 *)(Pico.rom + bank + (a & 0x7fffe));
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+}
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+
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// writes
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static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2)
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{
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@@ -1750,6 +1773,19 @@ void Pico32xSwapDRAM(int b)
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sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
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}
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+static void bank_switch_rom_sh2(void)
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+{
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+ if (!carthw_ssf2_active) {
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+ // easy
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+ sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr =
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+ sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
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+ }
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+ else {
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+ sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr = MAP_HANDLER(sh2_read8_rom);
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+ sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_HANDLER(sh2_read16_rom);
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+ }
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+}
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+
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void PicoMemSetup32x(void)
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{
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unsigned int rs;
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@@ -1784,15 +1820,9 @@ void PicoMemSetup32x(void)
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cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
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cpu68k_map_set(m68k_write8_map, 0x880000, 0x880000 + rs - 1, PicoWrite8_cart, 1);
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cpu68k_map_set(m68k_write16_map, 0x880000, 0x880000 + rs - 1, PicoWrite16_cart, 1);
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-#ifdef EMU_F68K
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- // setup FAME fetchmap
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- PicoCpuFM68k.Fetch[0] = (uptr)Pico32xMem->m68k_rom;
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- for (rs = 0x88; rs < 0x90; rs++)
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- PicoCpuFM68k.Fetch[rs] = (uptr)Pico.rom - 0x880000;
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-#endif
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// 32X ROM (banked)
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- bank_switch(0);
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+ bank_switch_rom_68k(0);
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cpu68k_map_set(m68k_write8_map, 0x900000, 0x9fffff, PicoWrite8_bank, 1);
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cpu68k_map_set(m68k_write16_map, 0x900000, 0x9fffff, PicoWrite16_bank, 1);
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}
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@@ -1827,8 +1857,7 @@ void PicoMemSetup32x(void)
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sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
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sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
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// CS1 - ROM
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- sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr =
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- sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
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+ bank_switch_rom_sh2();
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sh2_read8_map[0x02/2].mask = sh2_read8_map[0x22/2].mask =
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sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3fffff; // FIXME
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// CS2 - DRAM - done by Pico32xSwapDRAM()
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@@ -1868,9 +1897,17 @@ void PicoMemSetup32x(void)
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z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write_32x, 1);
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}
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+void p32x_update_banks(void)
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+{
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+ bank_switch_rom_68k(Pico32x.regs[4 / 2]);
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+ bank_switch_rom_sh2();
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+ if (Pico32x.emu_flags & P32XF_DRC_ROM_C)
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+ sh2_drc_flush_all();
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+}
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+
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void Pico32xMemStateLoaded(void)
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{
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- bank_switch(Pico32x.regs[4 / 2]);
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+ bank_switch_rom_68k(Pico32x.regs[4 / 2]);
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Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
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memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
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Pico32x.dirty_pal = 1;
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