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@@ -419,8 +419,8 @@ typedef struct {
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static int rcache_get_tmp(void);
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static int rcache_get_tmp(void);
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static void rcache_free_tmp(int hr);
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static void rcache_free_tmp(int hr);
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-// Note: cache_regs[] must have at least the amount of REG and TEMP registers
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-// used by handlers in worst case (currently 4).
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+// Note: cache_regs[] must have at least the amount of HRF_REG registers used
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+// by handlers in worst case (currently 4).
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// Register assignment goes by ABI convention. Caller save registers are TEMP,
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// Register assignment goes by ABI convention. Caller save registers are TEMP,
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// the others are either static or REG. SR must be static, R0 very recommended.
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// the others are either static or REG. SR must be static, R0 very recommended.
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// VBR, PC, PR must not be static (read from context in utils).
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// VBR, PC, PR must not be static (read from context in utils).
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@@ -2418,7 +2418,7 @@ static void rcache_init(void)
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// NB may return either REG or TEMP
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// NB may return either REG or TEMP
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static int emit_get_rbase_and_offs(SH2 *sh2, sh2_reg_e r, int rmode, u32 *offs)
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static int emit_get_rbase_and_offs(SH2 *sh2, sh2_reg_e r, int rmode, u32 *offs)
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{
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{
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- uptr omask = 0xff; // offset mask, XXX: ARM oriented..
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+ uptr omask = emith_rw_offs_max(); // offset mask
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u32 mask = 0;
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u32 mask = 0;
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u32 a;
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u32 a;
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int poffs;
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int poffs;
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@@ -4447,7 +4447,7 @@ end_op:
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static void sh2_generate_utils(void)
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static void sh2_generate_utils(void)
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{
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{
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- int arg0, arg1, arg2, arg3, sr, tmp;
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+ int arg0, arg1, arg2, arg3, sr, tmp, tmp2;
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host_arg2reg(arg0, 0);
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host_arg2reg(arg0, 0);
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host_arg2reg(arg1, 1);
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host_arg2reg(arg1, 1);
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@@ -4689,18 +4689,18 @@ static void sh2_generate_utils(void)
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emith_sub_r_imm(tmp, 4*2);
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emith_sub_r_imm(tmp, 4*2);
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rcache_clean();
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rcache_clean();
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// push SR
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// push SR
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- tmp = rcache_get_reg_arg(0, SHR_SP, NULL);
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- emith_add_r_imm(tmp, 4);
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+ tmp = rcache_get_reg_arg(0, SHR_SP,&tmp2);
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+ emith_add_r_r_imm(tmp, tmp2, 4);
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tmp = rcache_get_reg_arg(1, SHR_SR, NULL);
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tmp = rcache_get_reg_arg(1, SHR_SR, NULL);
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emith_clear_msb(tmp, tmp, 22);
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emith_clear_msb(tmp, tmp, 22);
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emith_move_r_r_ptr(arg2, CONTEXT_REG);
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emith_move_r_r_ptr(arg2, CONTEXT_REG);
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- rcache_invalidate();
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+ rcache_invalidate_tmp();
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emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
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emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
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// push PC
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// push PC
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rcache_get_reg_arg(0, SHR_SP, NULL);
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rcache_get_reg_arg(0, SHR_SP, NULL);
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emith_ctx_read(arg1, SHR_PC * 4);
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emith_ctx_read(arg1, SHR_PC * 4);
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emith_move_r_r_ptr(arg2, CONTEXT_REG);
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emith_move_r_r_ptr(arg2, CONTEXT_REG);
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- rcache_invalidate();
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+ rcache_invalidate_tmp();
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emith_call(p32x_sh2_write32);
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emith_call(p32x_sh2_write32);
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// update I, cycles, do callback
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// update I, cycles, do callback
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emith_ctx_read(arg1, offsetof(SH2, pending_level));
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emith_ctx_read(arg1, offsetof(SH2, pending_level));
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