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@@ -1562,12 +1562,36 @@ static int emith_cond_check(int cond, int *r)
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// emitter ABI stuff
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#define emith_pool_check() /**/
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#define emith_pool_commit(j) /**/
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-// NB: mips32r2 has SYNCI
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-#define host_instructions_updated(base, end, force) __builtin___clear_cache(base, end)
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#define emith_update_cache() /**/
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#define emith_rw_offs_max() 0x7fff
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#define emith_uext_ptr(r) /**/
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+#if __mips_isa_rev >= 2 && defined(MIPS_USE_SYNCI) && defined(__GNUC__)
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+// this should normally be in libc clear_cache; however, it sometimes isn't.
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+// core function taken from SYNCI description, MIPS32 instruction set manual
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+static NOINLINE void host_instructions_updated(void *base, void *end, int force)
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+{
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+ int step, tmp;
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+ asm volatile(
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+ " bal 0f;" // needed to allow for jr.hb
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+ " b 3f;"
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+
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+ "0: rdhwr %2, $1;"
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+ " beqz %2, 2f;"
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+
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+ "1: synci 0(%0);"
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+ " sltu %3, %0, %1;"
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+ " addu %0, %0, %2;"
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+ " bnez %3, 1b;"
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+
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+ " sync;"
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+ "2: jr.hb $ra;"
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+ "3: " : "+r"(base), "+r"(end), "=r"(step), "=r"(tmp) :: "$31");
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+}
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+#else
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+#define host_instructions_updated(base, end, force) __builtin___clear_cache(base, end)
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+#endif
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+
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// SH2 drc specific
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#define emith_sh2_drc_entry() do { \
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int _c, _z = PTR_SIZE; u32 _m = 0xd0ff0000; \
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