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@@ -21,11 +21,13 @@ typedef unsigned int u32;
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#ifdef _MSC_VER
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#define rdprintf
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#define wrdprintf
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+#define r3printf
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#else
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//#define rdprintf dprintf
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#define rdprintf(...)
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//#define wrdprintf dprintf
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#define wrdprintf(...)
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+#define r3printf(...)
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#endif
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#ifdef EMU_CORE_DEBUG
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@@ -57,7 +59,7 @@ static u32 m68k_reg_read16(u32 a)
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d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);
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// the DMNA delay must only be visible on s68k side (Lunar2, Silpheed)
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if (Pico_mcd->m.state_flags&2) { d &= ~1; d |= 2; }
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- //printf("m68k_regs r3: %02x @%06x\n", (u8)d, SekPc);
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+ r3printf(EL_STATUS, "m68k_regs r3: %02x @%06x", (u8)d, SekPc);
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goto end;
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case 4:
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d = Pico_mcd->s68k_regs[4]<<8;
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@@ -122,7 +124,7 @@ void m68k_reg_write8(u32 a, u32 d)
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return;
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case 3: {
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u32 dold = Pico_mcd->s68k_regs[3]&0x1f;
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- //printf("m68k_regs w3: %02x @%06x\n", (u8)d, SekPc);
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+ r3printf(EL_STATUS, "m68k_regs w3: %02x @%06x", (u8)d, SekPc);
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d &= 0xc2;
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if ((dold>>6) != ((d>>6)&3))
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dprintf("m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));
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@@ -134,10 +136,12 @@ void m68k_reg_write8(u32 a, u32 d)
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} else {
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//dold &= ~2; // ??
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#if 1
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- if ((d & 2) && !(dold & 2)) {
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+ if (d & (d ^ dold) & 2) { // DMNA is being set
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Pico_mcd->m.state_flags |= 2; // we must delay setting DMNA bit (needed for Silpheed)
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d &= ~2;
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}
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+ else
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+ Pico_mcd->m.state_flags &= ~2;
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#else
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if (d & 2) dold &= ~1; // return word RAM to s68k in 2M mode
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#endif
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@@ -239,7 +243,7 @@ u32 s68k_reg_read16(u32 a)
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return ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state
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case 2:
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d = (Pico_mcd->s68k_regs[2]<<8) | (Pico_mcd->s68k_regs[3]&0x1f);
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- //printf("s68k_regs r3: %02x @%06x\n", (u8)d, SekPcS68k);
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+ r3printf(EL_STATUS, "s68k_regs r3: %02x @%06x", (u8)d, SekPcS68k);
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return s68k_poll_detect(a, d);
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case 6:
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return CDC_Read_Reg();
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@@ -289,10 +293,11 @@ void s68k_reg_write8(u32 a, u32 d)
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return; // only m68k can change WP
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case 3: {
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int dold = Pico_mcd->s68k_regs[3];
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- //elprintf(EL_STATUS, "s68k_regs w3: %02x s@%06x", (u8)d, SekPcS68k);
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+ r3printf(EL_STATUS, "s68k_regs w3: %02x @%06x", (u8)d, SekPcS68k);
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d &= 0x1d;
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d |= dold&0xc2;
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- if (d&4) {
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+ if (d&4)
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+ {
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if ((d ^ dold) & 5) {
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d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit
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PicoMemResetCD(d);
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@@ -302,12 +307,14 @@ void s68k_reg_write8(u32 a, u32 d)
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PicoMemResetCDdecode(d);
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#endif
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if (!(dold & 4)) {
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- dprintf("wram mode 2M->1M");
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+ r3printf(EL_STATUS, "wram mode 2M->1M");
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wram_2M_to_1M(Pico_mcd->word_ram2M);
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}
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- } else {
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+ }
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+ else
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+ {
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if (dold & 4) {
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- dprintf("wram mode 1M->2M");
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+ r3printf(EL_STATUS, "wram mode 1M->2M");
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if (!(d&1)) { // it didn't set the ret bit, which means it doesn't want to give WRAM to m68k
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d &= ~3;
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d |= (dold&1) ? 2 : 1; // then give it to the one which had bank0 in 1M mode
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@@ -319,6 +326,7 @@ void s68k_reg_write8(u32 a, u32 d)
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d |= dold&1;
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if (d&1) d &= ~2; // return word RAM to m68k in 2M mode
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}
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+ Pico_mcd->m.state_flags &= ~2;
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break;
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}
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case 4:
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