kernel_005_panel.patch 27 KB

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  1. diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
  2. index 6153972e0..c91f4b7ed 100644
  3. --- a/drivers/gpu/drm/panel/Kconfig
  4. +++ b/drivers/gpu/drm/panel/Kconfig
  5. @@ -500,4 +500,17 @@ config DRM_PANEL_XINPENG_XPP055C272
  6. Say Y here if you want to enable support for the Xinpeng
  7. XPP055C272 controller for 720x1280 LCD panels with MIPI/RGB/SPI
  8. system interfaces.
  9. +
  10. +config DRM_PANEL_CWD686
  11. + tristate "CWD686 panel"
  12. + depends on OF
  13. + depends on DRM_MIPI_DSI
  14. + depends on BACKLIGHT_CLASS_DEVICE
  15. + help
  16. + Say Y here if you want to enable support for CWD686 panel.
  17. + The panel has a 480x1280 resolution and uses 24 bit RGB per pixel.
  18. +
  19. + To compile this driver as a module, choose M here: the module
  20. + will be called panel-cwd686.
  21. +
  22. endmenu
  23. diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
  24. index 2ba560bca..865cca7f6 100644
  25. --- a/drivers/gpu/drm/panel/Makefile
  26. +++ b/drivers/gpu/drm/panel/Makefile
  27. @@ -53,3 +53,4 @@ obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o
  28. obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o
  29. obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o
  30. obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o
  31. +obj-$(CONFIG_DRM_PANEL_CWD686) += panel-cwd686.o
  32. diff --git a/drivers/gpu/drm/panel/panel-cwd686.c b/drivers/gpu/drm/panel/panel-cwd686.c
  33. new file mode 100644
  34. index 000000000..f3005490f
  35. --- /dev/null
  36. +++ b/drivers/gpu/drm/panel/panel-cwd686.c
  37. @@ -0,0 +1,768 @@
  38. +// SPDX-License-Identifier: GPL-2.0+
  39. +
  40. +#include <drm/drm_modes.h>
  41. +#include <drm/drm_mipi_dsi.h>
  42. +#include <drm/drm_panel.h>
  43. +#include <linux/backlight.h>
  44. +#include <linux/gpio/consumer.h>
  45. +#include <linux/regulator/consumer.h>
  46. +#include <linux/delay.h>
  47. +#include <linux/of_device.h>
  48. +#include <linux/module.h>
  49. +
  50. +struct cwd686 {
  51. + struct device *dev;
  52. + struct drm_panel panel;
  53. + struct regulator *supply;
  54. + struct gpio_desc *enable_gpio;
  55. + struct gpio_desc *reset_gpio;
  56. + struct backlight_device *backlight;
  57. + bool prepared;
  58. + bool enabled;
  59. +};
  60. +
  61. +static const struct drm_display_mode default_mode = {
  62. + .clock = 54465,
  63. + .hdisplay = 480,
  64. + .hsync_start = 480 + 150,
  65. + .hsync_end = 480 + 150 + 24,
  66. + .htotal = 480 + 150 + 24 + 40,
  67. + .vdisplay = 1280,
  68. + .vsync_start = 1280 + 12,
  69. + .vsync_end = 1280 + 12+ 6,
  70. + .vtotal = 1280 + 12 + 6 + 10,
  71. +};
  72. +
  73. +static inline struct cwd686 *panel_to_cwd686(struct drm_panel *panel)
  74. +{
  75. + return container_of(panel, struct cwd686, panel);
  76. +}
  77. +
  78. +#define dcs_write_seq(seq...) \
  79. +({ \
  80. + static const u8 d[] = { seq }; \
  81. + mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \
  82. +})
  83. +
  84. +static void cwd686_init_sequence(struct cwd686 *ctx)
  85. +{
  86. + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  87. +
  88. + dcs_write_seq(0xF0,0x5A,0x5A);
  89. + dcs_write_seq(0xF1,0xA5,0xA5);
  90. + dcs_write_seq(0xB6,0x0D,0x0D);
  91. + dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
  92. + dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
  93. + dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x90,0x01,0x90,0x01);
  94. + dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x30,0x01,0x6B,0x01);
  95. + dcs_write_seq(0xB2,0x73);
  96. + dcs_write_seq(0xBD,0x4E,0x0E,0x50,0x50,0x26,0x1D,0x00,0x14,0x42,0x03);
  97. + dcs_write_seq(0xB7,0x01,0x01,0x09,0x11,0x0D,0x55,0x19,0x19,0x21,0x1D,0x00,0x00,0x00,0x00,0x02,0xFF,0x3C);
  98. + dcs_write_seq(0xB8,0x23,0x01,0x30,0x34,0x63);
  99. + dcs_write_seq(0xB9,0xA0,0x22,0x00,0x44);
  100. + dcs_write_seq(0xBA,0x12,0x63);
  101. + dcs_write_seq(0xC1,0x0C,0x16,0x04,0x0C,0x10,0x04);
  102. + dcs_write_seq(0xC2,0x11,0x41);
  103. + dcs_write_seq(0xC3,0x22,0x31,0x04);
  104. + dcs_write_seq(0xC7,0x05,0x23,0x6B,0x49,0x00);
  105. + dcs_write_seq(0xC5,0x00);
  106. + dcs_write_seq(0xD0,0x37,0xFF,0xFF);
  107. + dcs_write_seq(0xD2,0x63,0x0B,0x08,0x88);
  108. + dcs_write_seq(0xD3,0x01,0x00,0x00,0x01,0x01,0x37,0x25,0x38,0x31,0x06,0x07);
  109. + dcs_write_seq(0xC8,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06);//GAMMA2.2
  110. + dcs_write_seq(0xC6,0x00,0x00,0xFF,0x00,0x00,0xFF,0x00,0x00);
  111. + dcs_write_seq(0xF4,0x08,0x77);
  112. + dcs_write_seq(0x36,0x14);
  113. + dcs_write_seq(0x35,0x00);
  114. + dcs_write_seq(0xF1,0x5A,0x5A);
  115. + dcs_write_seq(0xF0,0xA5,0xA5);
  116. +
  117. +}
  118. +
  119. +static int cwd686_disable(struct drm_panel *panel)
  120. +{
  121. + struct cwd686 *ctx = panel_to_cwd686(panel);
  122. + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  123. + int ret;
  124. +
  125. + if (!ctx->enabled)
  126. + return 0;
  127. +
  128. + backlight_disable(ctx->backlight);
  129. +
  130. + ctx->enabled = false;
  131. +
  132. + return 0;
  133. +}
  134. +
  135. +static int cwd686_unprepare(struct drm_panel *panel)
  136. +{
  137. + struct cwd686 *ctx = panel_to_cwd686(panel);
  138. + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  139. + int ret;
  140. +
  141. +#if 0
  142. + if (!ctx->prepared)
  143. + return 0;
  144. +
  145. + ret = mipi_dsi_dcs_set_display_off(dsi);
  146. + if (ret) {
  147. + dev_err(ctx->dev, "failed to turn display off (%d)\n", ret);
  148. + return ret;
  149. + }
  150. + ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
  151. + if (ret) {
  152. + dev_err(ctx->dev, "failed to enter sleep mode (%d)\n", ret);
  153. + return ret;
  154. + }
  155. +
  156. + gpiod_set_value_cansleep(ctx->reset_gpio, 0);
  157. +
  158. + ctx->prepared = false;
  159. +#endif
  160. +
  161. + return 0;
  162. +}
  163. +
  164. +static int cwd686_prepare(struct drm_panel *panel)
  165. +{
  166. + struct cwd686 *ctx = panel_to_cwd686(panel);
  167. + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  168. + int ret;
  169. +
  170. + if (ctx->prepared)
  171. + return 0;
  172. +
  173. + gpiod_set_value_cansleep(ctx->reset_gpio, 0);
  174. + msleep(10);
  175. + gpiod_set_value_cansleep(ctx->reset_gpio, 1);
  176. + msleep(120);
  177. +
  178. + /* Enabe tearing mode: send TE (tearing effect) at VBLANK */
  179. + ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
  180. + if (ret) {
  181. + dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", ret);
  182. + return ret;
  183. + }
  184. + /* Exit sleep mode and power on */
  185. +
  186. + cwd686_init_sequence(ctx);
  187. +
  188. + ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
  189. + if (ret) {
  190. + dev_err(ctx->dev, "failed to exit sleep mode (%d)\n", ret);
  191. + return ret;
  192. + }
  193. + msleep(120);
  194. +
  195. + ret = mipi_dsi_dcs_set_display_on(dsi);
  196. + if (ret) {
  197. + dev_err(ctx->dev, "failed to turn display on (%d)\n", ret);
  198. + return ret;
  199. + }
  200. + msleep(20);
  201. +
  202. + ctx->prepared = true;
  203. +
  204. + return 0;
  205. +}
  206. +
  207. +static int cwd686_enable(struct drm_panel *panel)
  208. +{
  209. + struct cwd686 *ctx = panel_to_cwd686(panel);
  210. + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  211. + int ret;
  212. +
  213. + if (ctx->enabled)
  214. + return 0;
  215. +
  216. + backlight_enable(ctx->backlight);
  217. +
  218. + ctx->enabled = true;
  219. +
  220. + return 0;
  221. +}
  222. +
  223. +static int cwd686_get_modes(struct drm_panel *panel, struct drm_connector *connector)
  224. +{
  225. + struct drm_display_mode *mode;
  226. +
  227. + mode = drm_mode_duplicate(connector->dev, &default_mode);
  228. + if (!mode) {
  229. + dev_err(panel->dev, "bad mode or failed to add mode\n");
  230. + return -EINVAL;
  231. + }
  232. + drm_mode_set_name(mode);
  233. + mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
  234. +
  235. + connector->display_info.width_mm = mode->width_mm;
  236. + connector->display_info.height_mm = mode->height_mm;
  237. +
  238. + drm_mode_probed_add(connector, mode);
  239. +
  240. + return 1; /* Number of modes */
  241. +}
  242. +
  243. +static const struct drm_panel_funcs cwd686_drm_funcs = {
  244. + .disable = cwd686_disable,
  245. + .unprepare = cwd686_unprepare,
  246. + .prepare = cwd686_prepare,
  247. + .enable = cwd686_enable,
  248. + .get_modes = cwd686_get_modes,
  249. +};
  250. +
  251. +static int cwd686_probe(struct mipi_dsi_device *dsi)
  252. +{
  253. + struct device *dev = &dsi->dev;
  254. + struct cwd686 *ctx;
  255. + int ret;
  256. +
  257. + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
  258. + if (!ctx)
  259. + return -ENOMEM;
  260. +
  261. + mipi_dsi_set_drvdata(dsi, ctx);
  262. + ctx->dev = dev;
  263. +
  264. + dsi->lanes = 4;
  265. + dsi->format = MIPI_DSI_FMT_RGB888;
  266. + dsi->mode_flags = MIPI_DSI_MODE_VIDEO |MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
  267. +
  268. + ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
  269. + if (IS_ERR(ctx->reset_gpio)) {
  270. + ret = PTR_ERR(ctx->reset_gpio);
  271. + if (ret != -EPROBE_DEFER)
  272. + dev_err(dev, "failed to request GPIO (%d)\n", ret);
  273. + return ret;
  274. + }
  275. +
  276. + ctx->backlight = devm_of_find_backlight(dev);
  277. + if (IS_ERR(ctx->backlight))
  278. + return PTR_ERR(ctx->backlight);
  279. +
  280. + drm_panel_init(&ctx->panel, dev, &cwd686_drm_funcs, DRM_MODE_CONNECTOR_DSI);
  281. +
  282. + drm_panel_add(&ctx->panel);
  283. +
  284. + ret = mipi_dsi_attach(dsi);
  285. + if (ret < 0) {
  286. + dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
  287. + drm_panel_remove(&ctx->panel);
  288. + return ret;
  289. + }
  290. +
  291. + return 0;
  292. +}
  293. +
  294. +static int cwd686_remove(struct mipi_dsi_device *dsi)
  295. +{
  296. + struct cwd686 *ctx = mipi_dsi_get_drvdata(dsi);
  297. +
  298. + mipi_dsi_detach(dsi);
  299. + drm_panel_remove(&ctx->panel);
  300. +
  301. + return 0;
  302. +}
  303. +
  304. +#if 1
  305. +#include <linux/i2c.h>
  306. +#include <linux/regmap.h>
  307. +
  308. +struct tc358768_priv {
  309. + struct device *dev;
  310. + struct regmap *regmap;
  311. + struct gpio_desc *reset_gpio;
  312. + struct gpio_desc *power_gpio;
  313. +};
  314. +
  315. +#define panel_mini_vdd3v3en(val) gpiod_set_value_cansleep(priv->power_gpio, val)
  316. +#define panel_reset(val) gpiod_set_value_cansleep(priv->reset_gpio, val)
  317. +#define panel_lcd_reset(val) {}
  318. +#define panel_lcd_power(val) {}
  319. +
  320. +static const struct regmap_config tc358768_regmap_config = {
  321. + .reg_bits = 16,
  322. + .val_bits = 16,
  323. + .max_register = 0x062C,
  324. + .cache_type = REGCACHE_NONE,
  325. +// .writeable_reg = tc358768_writeable_reg,
  326. +// .readable_reg = tc358768_readable_reg,
  327. + .reg_format_endian = REGMAP_ENDIAN_BIG,
  328. + .val_format_endian = REGMAP_ENDIAN_BIG,
  329. +};
  330. +
  331. +static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val)
  332. +{
  333. + /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
  334. + int tmpval = val;
  335. + size_t count = 1;
  336. +
  337. + regmap_bulk_write(priv->regmap, reg, &tmpval, count);
  338. +}
  339. +
  340. +static void LCD_power_on(struct tc358768_priv *priv)
  341. +{
  342. +
  343. + panel_reset(0);
  344. + panel_lcd_power(1);
  345. + msleep(5);
  346. + panel_lcd_reset(0);
  347. + msleep(5);
  348. + panel_lcd_reset(1);
  349. + msleep(5);
  350. + panel_lcd_reset(0);
  351. + msleep(5);
  352. + panel_lcd_reset(1);
  353. +// sunxi_lcd_power_enable(sel, 0);//config 775 VDD_MIPI_12 power
  354. + msleep(50);
  355. + panel_mini_vdd3v3en(1);
  356. + msleep(50);
  357. + panel_reset(1);
  358. + msleep(50);
  359. + panel_reset(0);
  360. + msleep(50);
  361. + panel_reset(1);
  362. + msleep(50);
  363. +
  364. +}
  365. +
  366. +static void LCD_power_off(struct tc358768_priv *priv)
  367. +{
  368. + msleep(5);
  369. + panel_reset(0);
  370. + msleep(5);
  371. + panel_lcd_reset(0);
  372. + msleep(20);
  373. +// sunxi_lcd_power_disable(sel, 0);//config lcd_power pin to close lcd power
  374. + panel_mini_vdd3v3en(0);
  375. + panel_lcd_power(0);
  376. +
  377. +}
  378. +
  379. +static void tc358778_panel_init_mipi(struct tc358768_priv *priv)
  380. +{
  381. + __u16 value=0;
  382. + tc358768_write(priv, 0x0002,0x0001);//SYSctl, S/W Reset
  383. + msleep(10);
  384. + tc358768_write(priv, 0x0002,0x0000);//SYSctl, S/W Reset release
  385. + tc358768_write(priv, 0x0016,0x106D);//PLL Control Register 0 (PLL_PRD,PLL_FBD)
  386. + tc358768_write(priv, 0x0018,0x0603);//PLL_FRS,PLL_LBWS, PLL oscillation enable
  387. + msleep(100);
  388. + tc358768_write(priv, 0x0018,0x0613);//PLL_FRS,PLL_LBWS, PLL clock out enable
  389. + tc358768_write(priv, 0x0006,0x0014);//FIFO Control Register
  390. + tc358768_write(priv, 0x0140,0x0000);//D-PHY Clock lane enable
  391. + tc358768_write(priv, 0x0142,0x0000);//
  392. + tc358768_write(priv, 0x0144,0x0000);//D-PHY Data lane0 enable
  393. + tc358768_write(priv, 0x0146,0x0000);//
  394. + tc358768_write(priv, 0x0148,0x0000);//D-PHY Data lane1 enable
  395. + tc358768_write(priv, 0x014A,0x0000);//
  396. + tc358768_write(priv, 0x014C,0x0000);//D-PHY Data lane2 enable
  397. + tc358768_write(priv, 0x014E,0x0000);//
  398. + tc358768_write(priv, 0x0150,0x0000);//D-PHY Data lane3 enable
  399. + tc358768_write(priv, 0x0152,0x0000);//
  400. + tc358768_write(priv, 0x0100,0x0002);//D-PHY Clock lane control
  401. + tc358768_write(priv, 0x0102,0x0000);//
  402. + tc358768_write(priv, 0x0104,0x0002);//D-PHY Data lane0 control
  403. + tc358768_write(priv, 0x0106,0x0000);//
  404. + tc358768_write(priv, 0x0108,0x0002);//D-PHY Data lane1 control
  405. + tc358768_write(priv, 0x010A,0x0000);//
  406. + tc358768_write(priv, 0x010C,0x0002);//D-PHY Data lane2 control
  407. + tc358768_write(priv, 0x010E,0x0000);//
  408. + tc358768_write(priv, 0x0110,0x0002);//D-PHY Data lane3 control
  409. + tc358768_write(priv, 0x0112,0x0000);//
  410. + tc358768_write(priv, 0x0210,0x1770);//LINEINITCNT
  411. + tc358768_write(priv, 0x0212,0x0000);//
  412. + tc358768_write(priv, 0x0214,0x0002);//LPTXTIMECNT
  413. + tc358768_write(priv, 0x0216,0x0000);//
  414. + tc358768_write(priv, 0x0218,0x2301);//TCLK_HEADERCNT
  415. + tc358768_write(priv, 0x021A,0x0000);//
  416. + tc358768_write(priv, 0x0220,0x0803);//THS_HEADERCNT
  417. + tc358768_write(priv, 0x0222,0x0000);//
  418. + tc358768_write(priv, 0x0224,0x4E20);//TWAKEUPCNT
  419. + tc358768_write(priv, 0x0226,0x0000);//
  420. + tc358768_write(priv, 0x022C,0x0000);//THS_TRAILCNT
  421. + tc358768_write(priv, 0x022E,0x0000);//
  422. + tc358768_write(priv, 0x0230,0x0005);//HSTXVREGCNT
  423. + tc358768_write(priv, 0x0232,0x0000);//
  424. + tc358768_write(priv, 0x0234,0x001F);//HSTXVREGEN enable
  425. + tc358768_write(priv, 0x0236,0x0000);//
  426. + tc358768_write(priv, 0x0238,0x0001);//DSI clock Enable/Disable during LP
  427. + tc358768_write(priv, 0x023A,0x0000);//
  428. + tc358768_write(priv, 0x023C,0x0002);//BTACNTRL1
  429. + tc358768_write(priv, 0x023E,0x0002);//
  430. + tc358768_write(priv, 0x0204,0x0001);//STARTCNTRL
  431. + tc358768_write(priv, 0x0206,0x0000);//
  432. + tc358768_write(priv, 0x0620,0x0001);//Sync Pulse/Sync Event mode setting
  433. + tc358768_write(priv, 0x0622,0x001E);//V Control Register1
  434. + tc358768_write(priv, 0x0624,0x0014);//V Control Register2
  435. + tc358768_write(priv, 0x0626,0x0500);//V Control Register3
  436. + tc358768_write(priv, 0x0628,0x00CF);//H Control Register1
  437. + tc358768_write(priv, 0x062A,0x00BA);//H Control Register2
  438. + tc358768_write(priv, 0x062C,0x05A0);//H Control Register3
  439. + tc358768_write(priv, 0x0518,0x0001);//DSI Start
  440. + tc358768_write(priv, 0x051A,0x0000);//
  441. + tc358768_write(priv, 0x0602,0x4029);
  442. + tc358768_write(priv, 0x0604,0x0003);
  443. + tc358768_write(priv, 0x0610,0x5AF0);
  444. + tc358768_write(priv, 0x0612,0x005A);
  445. + tc358768_write(priv, 0x0600,0x0001);
  446. + msleep(50);
  447. + tc358768_write(priv, 0x0602,0x4029);
  448. + tc358768_write(priv, 0x0604,0x0003);
  449. + tc358768_write(priv, 0x0610,0xA5F1);
  450. + tc358768_write(priv, 0x0612,0x00A5);
  451. + tc358768_write(priv, 0x0600,0x0001);
  452. + msleep(50);
  453. + tc358768_write(priv, 0x0602,0x4029);
  454. + tc358768_write(priv, 0x0604,0x0003);
  455. + tc358768_write(priv, 0x0610,0x0DB6);
  456. + tc358768_write(priv, 0x0612,0x000D);
  457. + tc358768_write(priv, 0x0600,0x0001);
  458. + msleep(50);
  459. + tc358768_write(priv, 0x0008,0x0001);
  460. + tc358768_write(priv, 0x0050,0x0029);
  461. + tc358768_write(priv, 0x0022,0x0015);
  462. + tc358768_write(priv, 0x00E0,0x8000);
  463. + tc358768_write(priv, 0x00E8,0x0AB4);
  464. + tc358768_write(priv, 0x00E8,0x1208);
  465. + tc358768_write(priv, 0x00E8,0x0E10);
  466. + tc358768_write(priv, 0x00E8,0x000C);
  467. + tc358768_write(priv, 0x00E8,0x0000);
  468. + tc358768_write(priv, 0x00E8,0x0003);
  469. + tc358768_write(priv, 0x00E8,0x0303);
  470. + tc358768_write(priv, 0x00E8,0x0303);
  471. + tc358768_write(priv, 0x00E8,0x0303);
  472. + tc358768_write(priv, 0x00E8,0x0403);
  473. + tc358768_write(priv, 0x00E8,0x0006);
  474. + tc358768_write(priv, 0x00E0,0xE000);
  475. + msleep(100);
  476. + tc358768_write(priv, 0x00E0,0x2000);
  477. + tc358768_write(priv, 0x00E0,0x0000);
  478. + msleep(10);
  479. + tc358768_write(priv, 0x0008,0x0001);
  480. + tc358768_write(priv, 0x0050,0x0029);
  481. + tc358768_write(priv, 0x0022,0x0015);
  482. + tc358768_write(priv, 0x00E0,0x8000);
  483. + tc358768_write(priv, 0x00E8,0x0BB3);
  484. + tc358768_write(priv, 0x00E8,0x1309);
  485. + tc358768_write(priv, 0x00E8,0x0F11);
  486. + tc358768_write(priv, 0x00E8,0x000D);
  487. + tc358768_write(priv, 0x00E8,0x0000);
  488. + tc358768_write(priv, 0x00E8,0x0003);
  489. + tc358768_write(priv, 0x00E8,0x0303);
  490. + tc358768_write(priv, 0x00E8,0x0303);
  491. + tc358768_write(priv, 0x00E8,0x0303);
  492. + tc358768_write(priv, 0x00E8,0x0503);
  493. + tc358768_write(priv, 0x00E8,0x0007);
  494. + tc358768_write(priv, 0x00E0,0xE000);
  495. + msleep(100);
  496. + tc358768_write(priv, 0x00E0,0x2000);
  497. + tc358768_write(priv, 0x00E0,0x0000);
  498. + msleep(10);
  499. + tc358768_write(priv, 0x0008,0x0001);
  500. + tc358768_write(priv, 0x0050,0x0029);
  501. + tc358768_write(priv, 0x0022,0x000D);
  502. + tc358768_write(priv, 0x00E0,0x8000);
  503. + tc358768_write(priv, 0x00E8,0x54B0);
  504. + tc358768_write(priv, 0x00E8,0x2332);
  505. + tc358768_write(priv, 0x00E8,0x4445);
  506. + tc358768_write(priv, 0x00E8,0x4444);
  507. + tc358768_write(priv, 0x00E8,0x9044);
  508. + tc358768_write(priv, 0x00E8,0x9001);
  509. + tc358768_write(priv, 0x00E8,0x0001);
  510. + tc358768_write(priv, 0x00E0,0xE000);
  511. + msleep(100);
  512. + tc358768_write(priv, 0x00E0,0x2000);
  513. + tc358768_write(priv, 0x00E0,0x0000);
  514. + msleep(10);
  515. + tc358768_write(priv, 0x0008,0x0001);
  516. + tc358768_write(priv, 0x0050,0x0029);
  517. + tc358768_write(priv, 0x0022,0x000D);
  518. + tc358768_write(priv, 0x00E0,0x8000);
  519. + tc358768_write(priv, 0x00E8,0x32B1);
  520. + tc358768_write(priv, 0x00E8,0x0284);
  521. + tc358768_write(priv, 0x00E8,0x0383);
  522. + tc358768_write(priv, 0x00E8,0x6B01);
  523. + tc358768_write(priv, 0x00E8,0x0001);
  524. + tc358768_write(priv, 0x00E0,0xE000);
  525. + msleep(100);
  526. + tc358768_write(priv, 0x00E0,0x2000);
  527. + tc358768_write(priv, 0x00E0,0x0000);
  528. + msleep(10);
  529. + tc358768_write(priv, 0x0602,0x1023);
  530. + tc358768_write(priv, 0x0604,0x0000);
  531. + tc358768_write(priv, 0x0610,0x73B2);
  532. + tc358768_write(priv, 0x0600,0x0001);
  533. + msleep(50);
  534. + tc358768_write(priv, 0x0008,0x0001);
  535. + tc358768_write(priv, 0x0050,0x0029);
  536. + tc358768_write(priv, 0x0022,0x000B);
  537. + tc358768_write(priv, 0x00E0,0x8000);
  538. + tc358768_write(priv, 0x00E8,0x4EBD);
  539. + tc358768_write(priv, 0x00E8,0x500E);
  540. + tc358768_write(priv, 0x00E8,0x2650);
  541. + tc358768_write(priv, 0x00E8,0x001D);
  542. + tc358768_write(priv, 0x00E8,0x4214);
  543. + tc358768_write(priv, 0x00E8,0x0003);
  544. + tc358768_write(priv, 0x00E0,0xE000);
  545. + msleep(100);
  546. + tc358768_write(priv, 0x00E0,0x2000);
  547. + tc358768_write(priv, 0x00E0,0x0000);
  548. + msleep(10);
  549. + tc358768_write(priv, 0x0008,0x0001);
  550. + tc358768_write(priv, 0x0050,0x0029);
  551. + tc358768_write(priv, 0x0022,0x0012);
  552. + tc358768_write(priv, 0x00E0,0x8000);
  553. + tc358768_write(priv, 0x00E8,0x01B7);
  554. + tc358768_write(priv, 0x00E8,0x0901);
  555. + tc358768_write(priv, 0x00E8,0x0D11);
  556. + tc358768_write(priv, 0x00E8,0x1955);
  557. + tc358768_write(priv, 0x00E8,0x2119);
  558. + tc358768_write(priv, 0x00E8,0x001D);
  559. + tc358768_write(priv, 0x00E8,0x0000);
  560. + tc358768_write(priv, 0x00E8,0x0200);
  561. + tc358768_write(priv, 0x00E8,0x3CFF);
  562. + tc358768_write(priv, 0x00E0,0xE000);
  563. + msleep(100);
  564. + tc358768_write(priv, 0x00E0,0x2000);
  565. + tc358768_write(priv, 0x00E0,0x0000);
  566. + msleep(10);
  567. + tc358768_write(priv, 0x0602,0x4029);
  568. + tc358768_write(priv, 0x0604,0x0006);
  569. + tc358768_write(priv, 0x0610,0x23B8);
  570. + tc358768_write(priv, 0x0612,0x3001);
  571. + tc358768_write(priv, 0x0614,0x6334);
  572. + tc358768_write(priv, 0x0600,0x0001);
  573. + msleep(50);
  574. + tc358768_write(priv, 0x0602,0x4029);
  575. + tc358768_write(priv, 0x0604,0x0005);
  576. + tc358768_write(priv, 0x0610,0x23B9);
  577. + tc358768_write(priv, 0x0612,0x0022);
  578. + tc358768_write(priv, 0x0614,0x0044);
  579. + tc358768_write(priv, 0x0600,0x0001);
  580. + msleep(50);
  581. + tc358768_write(priv, 0x0602,0x4029);
  582. + tc358768_write(priv, 0x0604,0x0003);
  583. + tc358768_write(priv, 0x0610,0x12BA);
  584. + tc358768_write(priv, 0x0612,0x0063);
  585. + tc358768_write(priv, 0x0600,0x0001);
  586. + msleep(50);
  587. + tc358768_write(priv, 0x0602,0x4029);
  588. + tc358768_write(priv, 0x0604,0x0007);
  589. + tc358768_write(priv, 0x0610,0x0CC1);
  590. + tc358768_write(priv, 0x0612,0x0416);
  591. + tc358768_write(priv, 0x0614,0x100C);
  592. + tc358768_write(priv, 0x0616,0x0004);
  593. + tc358768_write(priv, 0x0600,0x0001);
  594. + msleep(50);
  595. + tc358768_write(priv, 0x0602,0x4029);
  596. + tc358768_write(priv, 0x0604,0x0003);
  597. + tc358768_write(priv, 0x0610,0x11C2);
  598. + tc358768_write(priv, 0x0612,0x0041);
  599. + tc358768_write(priv, 0x0600,0x0001);
  600. + msleep(50);
  601. + tc358768_write(priv, 0x0602,0x4029);
  602. + tc358768_write(priv, 0x0604,0x0004);
  603. + tc358768_write(priv, 0x0610,0x22C3);
  604. + tc358768_write(priv, 0x0612,0x0431);
  605. + tc358768_write(priv, 0x0600,0x0001);
  606. + msleep(50);
  607. + tc358768_write(priv, 0x0602,0x4029);
  608. + tc358768_write(priv, 0x0604,0x0006);
  609. + tc358768_write(priv, 0x0610,0x05C7);
  610. + tc358768_write(priv, 0x0612,0x6B23);
  611. + tc358768_write(priv, 0x0614,0x0049);
  612. + tc358768_write(priv, 0x0600,0x0001);
  613. + msleep(50);
  614. + tc358768_write(priv, 0x0602,0x1023);
  615. + tc358768_write(priv, 0x0604,0x0000);
  616. + tc358768_write(priv, 0x0610,0x00C5);
  617. + tc358768_write(priv, 0x0600,0x0001);
  618. + msleep(50);
  619. + tc358768_write(priv, 0x0602,0x4029);
  620. + tc358768_write(priv, 0x0604,0x0004);
  621. + tc358768_write(priv, 0x0610,0x37D0);
  622. + tc358768_write(priv, 0x0612,0xFFFF);
  623. + tc358768_write(priv, 0x0600,0x0001);
  624. + msleep(50);
  625. + tc358768_write(priv, 0x0602,0x4029);
  626. + tc358768_write(priv, 0x0604,0x0005);
  627. + tc358768_write(priv, 0x0610,0x63D2);
  628. + tc358768_write(priv, 0x0612,0x080B);
  629. + tc358768_write(priv, 0x0614,0x0088);
  630. + tc358768_write(priv, 0x0600,0x0001);
  631. + msleep(50);
  632. + tc358768_write(priv, 0x0008,0x0001);
  633. + tc358768_write(priv, 0x0050,0x0029);
  634. + tc358768_write(priv, 0x0022,0x000C);
  635. + tc358768_write(priv, 0x00E0,0x8000);
  636. + tc358768_write(priv, 0x00E8,0x01D3);
  637. + tc358768_write(priv, 0x00E8,0x0000);
  638. + tc358768_write(priv, 0x00E8,0x0101);
  639. + tc358768_write(priv, 0x00E8,0x2537);
  640. + tc358768_write(priv, 0x00E8,0x3138);
  641. + tc358768_write(priv, 0x00E8,0x0706);
  642. + tc358768_write(priv, 0x00E0,0xE000);
  643. + msleep(100);
  644. + tc358768_write(priv, 0x00E0,0x2000);
  645. + tc358768_write(priv, 0x00E0,0x0000);
  646. + msleep(10);
  647. + tc358768_write(priv, 0x0008,0x0001);
  648. + tc358768_write(priv, 0x0050,0x0029);
  649. + tc358768_write(priv, 0x0022,0x0027);
  650. + tc358768_write(priv, 0x00E0,0x8000);
  651. + tc358768_write(priv, 0x00E8,0x7CC8);
  652. + tc358768_write(priv, 0x00E8,0x5D6A);
  653. + tc358768_write(priv, 0x00E8,0x5353);
  654. + tc358768_write(priv, 0x00E8,0x4B45);
  655. + tc358768_write(priv, 0x00E8,0x4D35);
  656. + tc358768_write(priv, 0x00E8,0x494A);
  657. + tc358768_write(priv, 0x00E8,0x5366);
  658. + tc358768_write(priv, 0x00E8,0x4A57);
  659. + tc358768_write(priv, 0x00E8,0x3B48);
  660. + tc358768_write(priv, 0x00E8,0x062A);
  661. + tc358768_write(priv, 0x00E8,0x6A7C);
  662. + tc358768_write(priv, 0x00E8,0x535D);
  663. + tc358768_write(priv, 0x00E8,0x4553);
  664. + tc358768_write(priv, 0x00E8,0x354B);
  665. + tc358768_write(priv, 0x00E8,0x4A4D);
  666. + tc358768_write(priv, 0x00E8,0x6649);
  667. + tc358768_write(priv, 0x00E8,0x5753);
  668. + tc358768_write(priv, 0x00E8,0x484A);
  669. + tc358768_write(priv, 0x00E8,0x2A3B);
  670. + tc358768_write(priv, 0x00E8,0x0006);
  671. + tc358768_write(priv, 0x00E8,0x0000);
  672. + tc358768_write(priv, 0x00E0,0xE000);
  673. + msleep(100);
  674. + tc358768_write(priv, 0x00E0,0x2000);
  675. + tc358768_write(priv, 0x00E0,0x0000);
  676. + msleep(10);
  677. + tc358768_write(priv, 0x0008,0x0001);
  678. + tc358768_write(priv, 0x0050,0x0029);
  679. + tc358768_write(priv, 0x0022,0x0009);
  680. + tc358768_write(priv, 0x00E0,0x8000);
  681. + tc358768_write(priv, 0x00E8,0x00C6);
  682. + tc358768_write(priv, 0x00E8,0xFF00);
  683. + tc358768_write(priv, 0x00E8,0x0000);
  684. + tc358768_write(priv, 0x00E8,0x00FF);
  685. + tc358768_write(priv, 0x00E8,0x0000);
  686. + tc358768_write(priv, 0x00E0,0xE000);
  687. + msleep(100);
  688. + tc358768_write(priv, 0x00E0,0x2000);
  689. + tc358768_write(priv, 0x00E0,0x0000);
  690. + msleep(10);
  691. + tc358768_write(priv, 0x0602,0x4029);
  692. + tc358768_write(priv, 0x0604,0x0003);
  693. + tc358768_write(priv, 0x0610,0x08F4);
  694. + tc358768_write(priv, 0x0612,0x0077);
  695. + tc358768_write(priv, 0x0600,0x0001);
  696. + msleep(50);
  697. + tc358768_write(priv, 0x0602,0x1023);
  698. + tc358768_write(priv, 0x0604,0x0000);
  699. + tc358768_write(priv, 0x0610,0x1436);
  700. + tc358768_write(priv, 0x0600,0x0001);
  701. + msleep(50);
  702. + tc358768_write(priv, 0x0602,0x1023);
  703. + tc358768_write(priv, 0x0604,0x0000);
  704. + tc358768_write(priv, 0x0610,0x0035);
  705. + tc358768_write(priv, 0x0600,0x0001);
  706. + msleep(50);
  707. + tc358768_write(priv, 0x0602,0x1023);
  708. + tc358768_write(priv, 0x0604,0x0000);
  709. + tc358768_write(priv, 0x0610,0x0011);
  710. + tc358768_write(priv, 0x0600,0x0001);
  711. + msleep(50);
  712. + tc358768_write(priv, 0x0602,0x1023);
  713. + tc358768_write(priv, 0x0604,0x0000);
  714. + tc358768_write(priv, 0x0610,0x0029);
  715. + tc358768_write(priv, 0x0600,0x0001);
  716. + msleep(50);
  717. + tc358768_write(priv, 0x0602,0x4029);
  718. + tc358768_write(priv, 0x0604,0x0003);
  719. + tc358768_write(priv, 0x0610,0x5AF1);
  720. + tc358768_write(priv, 0x0612,0x005A);
  721. + tc358768_write(priv, 0x0600,0x0001);
  722. + msleep(50);
  723. + tc358768_write(priv, 0x0602,0x4029);
  724. + tc358768_write(priv, 0x0604,0x0003);
  725. + tc358768_write(priv, 0x0610,0xA5F0);
  726. + tc358768_write(priv, 0x0612,0x00A5);
  727. + tc358768_write(priv, 0x0600,0x0001);
  728. + msleep(50);
  729. + tc358768_write(priv, 0x0500,0x0086);//DSI lane setting, DSI mode=HS
  730. + tc358768_write(priv, 0x0502,0xA300);//bit set
  731. + tc358768_write(priv, 0x0500,0x8000);//Switch to DSI mode
  732. + tc358768_write(priv, 0x0502,0xC300);//
  733. + tc358768_write(priv, 0x0008,0x0037);//DSI-TX Format setting
  734. + tc358768_write(priv, 0x0050,0x003E);//DSI-TX Pixel stream packet Data Type setting
  735. + tc358768_write(priv, 0x0032,0x0000);//HSYNC Polarity
  736. + tc358768_write(priv, 0x0004,0x0044);//Configuration Control Register
  737. +
  738. +}
  739. +
  740. +static void LCD_panel_init(struct tc358768_priv *priv)
  741. +{
  742. + LCD_power_on(priv);
  743. + msleep(100);
  744. + tc358778_panel_init_mipi(priv);
  745. + msleep(10);
  746. +}
  747. +
  748. +static int cwd686_i2c_probe(struct i2c_client *client,
  749. + const struct i2c_device_id *id)
  750. +{
  751. + struct tc358768_priv *priv;
  752. + struct device *dev = &client->dev;
  753. + struct device_node *np = dev->of_node;
  754. + int ret = 0;
  755. +
  756. + if (!np)
  757. + return -ENODEV;
  758. +
  759. + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  760. + if (!priv)
  761. + return -ENOMEM;
  762. +
  763. + dev_set_drvdata(dev, priv);
  764. + priv->dev = dev;
  765. + priv->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
  766. +
  767. + if (IS_ERR(priv->reset_gpio))
  768. + return PTR_ERR(priv->reset_gpio);
  769. +
  770. + priv->power_gpio = devm_gpiod_get_optional(dev, "power", GPIOD_OUT_HIGH);
  771. +
  772. + if (IS_ERR(priv->power_gpio))
  773. + return PTR_ERR(priv->power_gpio);
  774. +
  775. + priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config);
  776. + if (IS_ERR(priv->regmap)) {
  777. + dev_err(dev, "Failed to init regmap\n");
  778. + return PTR_ERR(priv->regmap);
  779. + }
  780. +
  781. + i2c_set_clientdata(client, priv);
  782. +
  783. + LCD_panel_init(priv);
  784. +
  785. + return ret;
  786. +}
  787. +#endif
  788. +
  789. +static const struct of_device_id cwd686_of_match[] = {
  790. + { .compatible = "cw,cwd686" },
  791. + { }
  792. +};
  793. +MODULE_DEVICE_TABLE(of, cwd686_of_match);
  794. +
  795. +static struct i2c_driver cwd686_driver = {
  796. + .driver = {
  797. + .name = "panel-cwd686",
  798. + .of_match_table = cwd686_of_match,
  799. + },
  800. + .probe = cwd686_i2c_probe,
  801. +};
  802. +module_i2c_driver(cwd686_driver);
  803. +
  804. +MODULE_DESCRIPTION("DRM Driver for cwd686 MIPI DSI panel");
  805. +MODULE_LICENSE("GPL v2");
  806. diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
  807. index 585ebe779..b494cede5 100644
  808. --- a/drivers/gpu/drm/panel/panel-simple.c
  809. +++ b/drivers/gpu/drm/panel/panel-simple.c
  810. @@ -4003,6 +4003,29 @@ static const struct panel_desc arm_rtsm = {
  811. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  812. };
  813. +
  814. +static const struct drm_display_mode clockwork_cpi3_lcd_mode = {
  815. + .clock = 50000,
  816. + .hdisplay = 480,
  817. + .hsync_start = 480 + 80,
  818. + .hsync_end = 480 + 80 + 20,
  819. + .htotal = 480 + 80 + 20 + 40,
  820. + .vdisplay = 1280,
  821. + .vsync_start = 1280 + 50,
  822. + .vsync_end = 1280 + 50+ 10,
  823. + .vtotal = 1280 + 50 + 10 + 20,
  824. + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  825. +};
  826. +
  827. +static const struct panel_desc clockwork_cpi3_lcd = {
  828. + .modes = &clockwork_cpi3_lcd_mode,
  829. + .num_modes = 1,
  830. + .bpc = 6,
  831. + .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  832. + .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
  833. + .connector_type = DRM_MODE_CONNECTOR_DPI,
  834. +};
  835. +
  836. static const struct of_device_id platform_of_match[] = {
  837. {
  838. .compatible = "ampire,am-1280800n3tzqw-t00h",
  839. @@ -4419,6 +4442,9 @@ static const struct of_device_id platform_of_match[] = {
  840. }, {
  841. .compatible = "winstar,wf35ltiacd",
  842. .data = &winstar_wf35ltiacd,
  843. + }, {
  844. + .compatible = "clockwork,cpi3-lcd",
  845. + .data = &clockwork_cpi3_lcd,
  846. }, {
  847. /* Must be the last entry */
  848. .compatible = "panel-dpi",