diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 6153972e0..c91f4b7ed 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -500,4 +500,17 @@ config DRM_PANEL_XINPENG_XPP055C272
 	  Say Y here if you want to enable support for the Xinpeng
 	  XPP055C272 controller for 720x1280 LCD panels with MIPI/RGB/SPI
 	  system interfaces.
+
+config DRM_PANEL_CWD686
+	tristate "CWD686 panel"
+	depends on OF
+	depends on DRM_MIPI_DSI
+	depends on BACKLIGHT_CLASS_DEVICE
+	help
+	  Say Y here if you want to enable support for CWD686 panel.
+	  The panel has a 480x1280 resolution and uses 24 bit RGB per pixel.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called panel-cwd686.
+
 endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 2ba560bca..865cca7f6 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o
 obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o
 obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o
 obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o
+obj-$(CONFIG_DRM_PANEL_CWD686) += panel-cwd686.o
diff --git a/drivers/gpu/drm/panel/panel-cwd686.c b/drivers/gpu/drm/panel/panel-cwd686.c
new file mode 100644
index 000000000..f3005490f
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-cwd686.c
@@ -0,0 +1,768 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <drm/drm_modes.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+#include <linux/backlight.h>
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
+#include <linux/delay.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+
+struct cwd686 {
+	struct device *dev;
+	struct drm_panel panel;
+	struct regulator *supply;
+	struct gpio_desc *enable_gpio;
+	struct gpio_desc *reset_gpio;
+	struct backlight_device *backlight;
+	bool prepared;
+	bool enabled;
+};
+
+static const struct drm_display_mode default_mode = {
+	.clock = 54465,
+	.hdisplay = 480,
+	.hsync_start = 480 + 150,
+	.hsync_end = 480 + 150 + 24,
+	.htotal = 480 + 150 + 24 + 40,
+	.vdisplay = 1280,
+	.vsync_start = 1280 + 12,
+	.vsync_end = 1280 + 12+ 6,
+	.vtotal = 1280 + 12 + 6 + 10,
+};
+
+static inline struct cwd686 *panel_to_cwd686(struct drm_panel *panel)
+{
+	return container_of(panel, struct cwd686, panel);
+}
+
+#define dcs_write_seq(seq...)                              \
+({                                                              \
+	static const u8 d[] = { seq };                          \
+	mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d));	 \
+})
+
+static void cwd686_init_sequence(struct cwd686 *ctx)
+{
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+
+	dcs_write_seq(0xF0,0x5A,0x5A);
+	dcs_write_seq(0xF1,0xA5,0xA5);
+	dcs_write_seq(0xB6,0x0D,0x0D);
+	dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
+	dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
+	dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x90,0x01,0x90,0x01);
+	dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x30,0x01,0x6B,0x01);
+	dcs_write_seq(0xB2,0x73);
+	dcs_write_seq(0xBD,0x4E,0x0E,0x50,0x50,0x26,0x1D,0x00,0x14,0x42,0x03);
+	dcs_write_seq(0xB7,0x01,0x01,0x09,0x11,0x0D,0x55,0x19,0x19,0x21,0x1D,0x00,0x00,0x00,0x00,0x02,0xFF,0x3C);
+	dcs_write_seq(0xB8,0x23,0x01,0x30,0x34,0x63);
+	dcs_write_seq(0xB9,0xA0,0x22,0x00,0x44);
+	dcs_write_seq(0xBA,0x12,0x63);
+	dcs_write_seq(0xC1,0x0C,0x16,0x04,0x0C,0x10,0x04);
+	dcs_write_seq(0xC2,0x11,0x41);
+	dcs_write_seq(0xC3,0x22,0x31,0x04);
+	dcs_write_seq(0xC7,0x05,0x23,0x6B,0x49,0x00);
+	dcs_write_seq(0xC5,0x00);
+	dcs_write_seq(0xD0,0x37,0xFF,0xFF);
+	dcs_write_seq(0xD2,0x63,0x0B,0x08,0x88);
+	dcs_write_seq(0xD3,0x01,0x00,0x00,0x01,0x01,0x37,0x25,0x38,0x31,0x06,0x07);
+	dcs_write_seq(0xC8,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06);//GAMMA2.2
+	dcs_write_seq(0xC6,0x00,0x00,0xFF,0x00,0x00,0xFF,0x00,0x00);
+	dcs_write_seq(0xF4,0x08,0x77);
+	dcs_write_seq(0x36,0x14);
+	dcs_write_seq(0x35,0x00);
+	dcs_write_seq(0xF1,0x5A,0x5A);
+	dcs_write_seq(0xF0,0xA5,0xA5);
+
+}
+
+static int cwd686_disable(struct drm_panel *panel)
+{
+	struct cwd686 *ctx = panel_to_cwd686(panel);
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	int ret;
+
+	if (!ctx->enabled)
+		return 0;
+
+	backlight_disable(ctx->backlight);
+
+	ctx->enabled = false;
+
+	return 0;
+}
+
+static int cwd686_unprepare(struct drm_panel *panel)
+{
+	struct cwd686 *ctx = panel_to_cwd686(panel);
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	int ret;
+
+#if 0
+	if (!ctx->prepared)
+		return 0;
+
+	ret = mipi_dsi_dcs_set_display_off(dsi);
+	if (ret) {
+		dev_err(ctx->dev, "failed to turn display off (%d)\n", ret);
+		return ret;
+	}
+	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
+	if (ret) {
+		dev_err(ctx->dev, "failed to enter sleep mode (%d)\n", ret);
+		return ret;
+	}
+
+	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+
+	ctx->prepared = false;
+#endif
+
+	return 0;
+}
+
+static int cwd686_prepare(struct drm_panel *panel)
+{
+	struct cwd686 *ctx = panel_to_cwd686(panel);
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	int ret;
+
+	if (ctx->prepared)
+		return 0;
+
+	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+	msleep(10);
+	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+	msleep(120);
+
+	/* Enabe tearing mode: send TE (tearing effect) at VBLANK */
+	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+	if (ret) {
+		dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", ret);
+		return ret;
+	}
+	/* Exit sleep mode and power on */
+
+	cwd686_init_sequence(ctx);
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret) {
+		dev_err(ctx->dev, "failed to exit sleep mode (%d)\n", ret);
+		return ret;
+	}
+	msleep(120);
+
+	ret = mipi_dsi_dcs_set_display_on(dsi);
+	if (ret) {
+		dev_err(ctx->dev, "failed to turn display on (%d)\n", ret);
+		return ret;
+	}
+	msleep(20);
+
+	ctx->prepared = true;
+
+	return 0;
+}
+
+static int cwd686_enable(struct drm_panel *panel)
+{
+	struct cwd686 *ctx = panel_to_cwd686(panel);
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	int ret;
+
+	if (ctx->enabled)
+		return 0;
+
+	backlight_enable(ctx->backlight);
+
+	ctx->enabled = true;
+
+	return 0;
+}
+
+static int cwd686_get_modes(struct drm_panel *panel, struct drm_connector *connector)
+{
+	struct drm_display_mode *mode;
+
+	mode = drm_mode_duplicate(connector->dev, &default_mode);
+	if (!mode) {
+		dev_err(panel->dev, "bad mode or failed to add mode\n");
+		return -EINVAL;
+	}
+	drm_mode_set_name(mode);
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+
+	connector->display_info.width_mm = mode->width_mm;
+	connector->display_info.height_mm = mode->height_mm;
+
+	drm_mode_probed_add(connector, mode);
+
+	return 1; /* Number of modes */
+}
+
+static const struct drm_panel_funcs cwd686_drm_funcs = {
+	.disable = cwd686_disable,
+	.unprepare = cwd686_unprepare,
+	.prepare = cwd686_prepare,
+	.enable = cwd686_enable,
+	.get_modes = cwd686_get_modes,
+};
+
+static int cwd686_probe(struct mipi_dsi_device *dsi)
+{
+	struct device *dev = &dsi->dev;
+	struct cwd686 *ctx;
+	int ret;
+
+	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+
+	mipi_dsi_set_drvdata(dsi, ctx);
+	ctx->dev = dev;
+
+	dsi->lanes = 4;
+	dsi->format = MIPI_DSI_FMT_RGB888;
+	dsi->mode_flags = MIPI_DSI_MODE_VIDEO |MIPI_DSI_MODE_VIDEO_BURST  | MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+
+	ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+	if (IS_ERR(ctx->reset_gpio)) {
+		ret = PTR_ERR(ctx->reset_gpio);
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "failed to request GPIO (%d)\n", ret);
+		return ret;
+	}
+
+	ctx->backlight = devm_of_find_backlight(dev);
+	if (IS_ERR(ctx->backlight))
+		return PTR_ERR(ctx->backlight);
+
+	drm_panel_init(&ctx->panel, dev, &cwd686_drm_funcs, DRM_MODE_CONNECTOR_DSI);
+
+	drm_panel_add(&ctx->panel);
+
+	ret = mipi_dsi_attach(dsi);
+	if (ret < 0) {
+		dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
+		drm_panel_remove(&ctx->panel);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int cwd686_remove(struct mipi_dsi_device *dsi)
+{
+	struct cwd686 *ctx = mipi_dsi_get_drvdata(dsi);
+
+	mipi_dsi_detach(dsi);
+	drm_panel_remove(&ctx->panel);
+
+	return 0;
+}
+
+#if 1
+#include <linux/i2c.h>
+#include <linux/regmap.h>
+
+struct tc358768_priv {
+	struct device *dev;
+	struct regmap *regmap;
+	struct gpio_desc *reset_gpio;
+	struct gpio_desc *power_gpio;
+};
+
+#define panel_mini_vdd3v3en(val) gpiod_set_value_cansleep(priv->power_gpio, val)
+#define panel_reset(val) gpiod_set_value_cansleep(priv->reset_gpio, val)
+#define panel_lcd_reset(val) {}
+#define panel_lcd_power(val) {}
+
+static const struct regmap_config tc358768_regmap_config = {
+	.reg_bits = 16,
+	.val_bits = 16,
+	.max_register = 0x062C,
+	.cache_type = REGCACHE_NONE,
+//	.writeable_reg = tc358768_writeable_reg,
+//	.readable_reg = tc358768_readable_reg,
+	.reg_format_endian = REGMAP_ENDIAN_BIG,
+	.val_format_endian = REGMAP_ENDIAN_BIG,
+};
+
+static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val)
+{
+	/* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
+	int tmpval = val;
+	size_t count = 1;
+
+	regmap_bulk_write(priv->regmap, reg, &tmpval, count);
+}
+
+static void LCD_power_on(struct tc358768_priv *priv)
+{
+
+	panel_reset(0);
+	panel_lcd_power(1);
+	msleep(5);
+	panel_lcd_reset(0);
+	msleep(5);
+	panel_lcd_reset(1);
+	msleep(5);
+	panel_lcd_reset(0);
+	msleep(5);
+	panel_lcd_reset(1);
+//	sunxi_lcd_power_enable(sel, 0);//config 775 VDD_MIPI_12 power
+	msleep(50);
+	panel_mini_vdd3v3en(1);
+	msleep(50);
+	panel_reset(1);
+	msleep(50);
+	panel_reset(0);
+	msleep(50);	
+	panel_reset(1);
+	msleep(50);
+
+}
+
+static void LCD_power_off(struct tc358768_priv *priv)
+{
+	msleep(5);
+	panel_reset(0);	
+	msleep(5);
+	panel_lcd_reset(0);
+	msleep(20);
+//	sunxi_lcd_power_disable(sel, 0);//config lcd_power pin to close lcd power 
+	panel_mini_vdd3v3en(0);
+	panel_lcd_power(0);
+
+}
+
+static void tc358778_panel_init_mipi(struct tc358768_priv *priv)
+{
+	__u16  value=0;
+	tc358768_write(priv, 0x0002,0x0001);//SYSctl, S/W Reset
+	msleep(10);
+	tc358768_write(priv, 0x0002,0x0000);//SYSctl, S/W Reset release
+	tc358768_write(priv, 0x0016,0x106D);//PLL Control Register 0 (PLL_PRD,PLL_FBD)
+	tc358768_write(priv, 0x0018,0x0603);//PLL_FRS,PLL_LBWS, PLL oscillation enable
+	msleep(100);
+	tc358768_write(priv, 0x0018,0x0613);//PLL_FRS,PLL_LBWS, PLL clock out enable
+	tc358768_write(priv, 0x0006,0x0014);//FIFO Control Register
+	tc358768_write(priv, 0x0140,0x0000);//D-PHY Clock lane enable
+	tc358768_write(priv, 0x0142,0x0000);//
+	tc358768_write(priv, 0x0144,0x0000);//D-PHY Data lane0 enable
+	tc358768_write(priv, 0x0146,0x0000);//
+	tc358768_write(priv, 0x0148,0x0000);//D-PHY Data lane1 enable
+	tc358768_write(priv, 0x014A,0x0000);//
+	tc358768_write(priv, 0x014C,0x0000);//D-PHY Data lane2 enable
+	tc358768_write(priv, 0x014E,0x0000);//
+	tc358768_write(priv, 0x0150,0x0000);//D-PHY Data lane3 enable
+	tc358768_write(priv, 0x0152,0x0000);//
+	tc358768_write(priv, 0x0100,0x0002);//D-PHY Clock lane control
+	tc358768_write(priv, 0x0102,0x0000);//
+	tc358768_write(priv, 0x0104,0x0002);//D-PHY Data lane0 control
+	tc358768_write(priv, 0x0106,0x0000);//
+	tc358768_write(priv, 0x0108,0x0002);//D-PHY Data lane1 control
+	tc358768_write(priv, 0x010A,0x0000);//
+	tc358768_write(priv, 0x010C,0x0002);//D-PHY Data lane2 control
+	tc358768_write(priv, 0x010E,0x0000);//
+	tc358768_write(priv, 0x0110,0x0002);//D-PHY Data lane3 control
+	tc358768_write(priv, 0x0112,0x0000);//
+	tc358768_write(priv, 0x0210,0x1770);//LINEINITCNT
+	tc358768_write(priv, 0x0212,0x0000);//
+	tc358768_write(priv, 0x0214,0x0002);//LPTXTIMECNT
+	tc358768_write(priv, 0x0216,0x0000);//
+	tc358768_write(priv, 0x0218,0x2301);//TCLK_HEADERCNT
+	tc358768_write(priv, 0x021A,0x0000);//
+	tc358768_write(priv, 0x0220,0x0803);//THS_HEADERCNT
+	tc358768_write(priv, 0x0222,0x0000);//
+	tc358768_write(priv, 0x0224,0x4E20);//TWAKEUPCNT
+	tc358768_write(priv, 0x0226,0x0000);//
+	tc358768_write(priv, 0x022C,0x0000);//THS_TRAILCNT
+	tc358768_write(priv, 0x022E,0x0000);//
+	tc358768_write(priv, 0x0230,0x0005);//HSTXVREGCNT
+	tc358768_write(priv, 0x0232,0x0000);//
+	tc358768_write(priv, 0x0234,0x001F);//HSTXVREGEN enable
+	tc358768_write(priv, 0x0236,0x0000);//
+	tc358768_write(priv, 0x0238,0x0001);//DSI clock Enable/Disable during LP
+	tc358768_write(priv, 0x023A,0x0000);//
+	tc358768_write(priv, 0x023C,0x0002);//BTACNTRL1
+	tc358768_write(priv, 0x023E,0x0002);//
+	tc358768_write(priv, 0x0204,0x0001);//STARTCNTRL
+	tc358768_write(priv, 0x0206,0x0000);//
+	tc358768_write(priv, 0x0620,0x0001);//Sync Pulse/Sync Event mode setting
+	tc358768_write(priv, 0x0622,0x001E);//V Control Register1
+	tc358768_write(priv, 0x0624,0x0014);//V Control Register2
+	tc358768_write(priv, 0x0626,0x0500);//V Control Register3
+	tc358768_write(priv, 0x0628,0x00CF);//H Control Register1
+	tc358768_write(priv, 0x062A,0x00BA);//H Control Register2
+	tc358768_write(priv, 0x062C,0x05A0);//H Control Register3
+	tc358768_write(priv, 0x0518,0x0001);//DSI Start
+	tc358768_write(priv, 0x051A,0x0000);//
+	tc358768_write(priv, 0x0602,0x4029);
+	tc358768_write(priv, 0x0604,0x0003);
+	tc358768_write(priv, 0x0610,0x5AF0);
+	tc358768_write(priv, 0x0612,0x005A);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x4029);
+	tc358768_write(priv, 0x0604,0x0003);
+	tc358768_write(priv, 0x0610,0xA5F1);
+	tc358768_write(priv, 0x0612,0x00A5);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x4029);
+	tc358768_write(priv, 0x0604,0x0003);
+	tc358768_write(priv, 0x0610,0x0DB6);
+	tc358768_write(priv, 0x0612,0x000D);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0008,0x0001);
+	tc358768_write(priv, 0x0050,0x0029);
+	tc358768_write(priv, 0x0022,0x0015);
+	tc358768_write(priv, 0x00E0,0x8000);
+	tc358768_write(priv, 0x00E8,0x0AB4);
+	tc358768_write(priv, 0x00E8,0x1208);
+	tc358768_write(priv, 0x00E8,0x0E10);
+	tc358768_write(priv, 0x00E8,0x000C);
+	tc358768_write(priv, 0x00E8,0x0000);
+	tc358768_write(priv, 0x00E8,0x0003);
+	tc358768_write(priv, 0x00E8,0x0303);
+	tc358768_write(priv, 0x00E8,0x0303);
+	tc358768_write(priv, 0x00E8,0x0303);
+	tc358768_write(priv, 0x00E8,0x0403);
+	tc358768_write(priv, 0x00E8,0x0006);
+	tc358768_write(priv, 0x00E0,0xE000);
+	msleep(100);
+	tc358768_write(priv, 0x00E0,0x2000);
+	tc358768_write(priv, 0x00E0,0x0000);
+	msleep(10);
+	tc358768_write(priv, 0x0008,0x0001);
+	tc358768_write(priv, 0x0050,0x0029);
+	tc358768_write(priv, 0x0022,0x0015);
+	tc358768_write(priv, 0x00E0,0x8000);
+	tc358768_write(priv, 0x00E8,0x0BB3);
+	tc358768_write(priv, 0x00E8,0x1309);
+	tc358768_write(priv, 0x00E8,0x0F11);
+	tc358768_write(priv, 0x00E8,0x000D);
+	tc358768_write(priv, 0x00E8,0x0000);
+	tc358768_write(priv, 0x00E8,0x0003);
+	tc358768_write(priv, 0x00E8,0x0303);
+	tc358768_write(priv, 0x00E8,0x0303);
+	tc358768_write(priv, 0x00E8,0x0303);
+	tc358768_write(priv, 0x00E8,0x0503);
+	tc358768_write(priv, 0x00E8,0x0007);
+	tc358768_write(priv, 0x00E0,0xE000);
+	msleep(100);
+	tc358768_write(priv, 0x00E0,0x2000);
+	tc358768_write(priv, 0x00E0,0x0000);
+	msleep(10);
+	tc358768_write(priv, 0x0008,0x0001);
+	tc358768_write(priv, 0x0050,0x0029);
+	tc358768_write(priv, 0x0022,0x000D);
+	tc358768_write(priv, 0x00E0,0x8000);
+	tc358768_write(priv, 0x00E8,0x54B0);
+	tc358768_write(priv, 0x00E8,0x2332);
+	tc358768_write(priv, 0x00E8,0x4445);
+	tc358768_write(priv, 0x00E8,0x4444);
+	tc358768_write(priv, 0x00E8,0x9044);
+	tc358768_write(priv, 0x00E8,0x9001);
+	tc358768_write(priv, 0x00E8,0x0001);
+	tc358768_write(priv, 0x00E0,0xE000);
+	msleep(100);
+	tc358768_write(priv, 0x00E0,0x2000);
+	tc358768_write(priv, 0x00E0,0x0000);
+	msleep(10);
+	tc358768_write(priv, 0x0008,0x0001);
+	tc358768_write(priv, 0x0050,0x0029);
+	tc358768_write(priv, 0x0022,0x000D);
+	tc358768_write(priv, 0x00E0,0x8000);
+	tc358768_write(priv, 0x00E8,0x32B1);
+	tc358768_write(priv, 0x00E8,0x0284);
+	tc358768_write(priv, 0x00E8,0x0383);
+	tc358768_write(priv, 0x00E8,0x6B01);
+	tc358768_write(priv, 0x00E8,0x0001);
+	tc358768_write(priv, 0x00E0,0xE000);
+	msleep(100);
+	tc358768_write(priv, 0x00E0,0x2000);
+	tc358768_write(priv, 0x00E0,0x0000);
+	msleep(10);
+	tc358768_write(priv, 0x0602,0x1023);
+	tc358768_write(priv, 0x0604,0x0000);
+	tc358768_write(priv, 0x0610,0x73B2);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0008,0x0001);
+	tc358768_write(priv, 0x0050,0x0029);
+	tc358768_write(priv, 0x0022,0x000B);
+	tc358768_write(priv, 0x00E0,0x8000);
+	tc358768_write(priv, 0x00E8,0x4EBD);
+	tc358768_write(priv, 0x00E8,0x500E);
+	tc358768_write(priv, 0x00E8,0x2650);
+	tc358768_write(priv, 0x00E8,0x001D);
+	tc358768_write(priv, 0x00E8,0x4214);
+	tc358768_write(priv, 0x00E8,0x0003);
+	tc358768_write(priv, 0x00E0,0xE000);
+	msleep(100);
+	tc358768_write(priv, 0x00E0,0x2000);
+	tc358768_write(priv, 0x00E0,0x0000);
+	msleep(10);
+	tc358768_write(priv, 0x0008,0x0001);
+	tc358768_write(priv, 0x0050,0x0029);
+	tc358768_write(priv, 0x0022,0x0012);
+	tc358768_write(priv, 0x00E0,0x8000);
+	tc358768_write(priv, 0x00E8,0x01B7);
+	tc358768_write(priv, 0x00E8,0x0901);
+	tc358768_write(priv, 0x00E8,0x0D11);
+	tc358768_write(priv, 0x00E8,0x1955);
+	tc358768_write(priv, 0x00E8,0x2119);
+	tc358768_write(priv, 0x00E8,0x001D);
+	tc358768_write(priv, 0x00E8,0x0000);
+	tc358768_write(priv, 0x00E8,0x0200);
+	tc358768_write(priv, 0x00E8,0x3CFF);
+	tc358768_write(priv, 0x00E0,0xE000);
+	msleep(100);
+	tc358768_write(priv, 0x00E0,0x2000);
+	tc358768_write(priv, 0x00E0,0x0000);
+	msleep(10);
+	tc358768_write(priv, 0x0602,0x4029);
+	tc358768_write(priv, 0x0604,0x0006);
+	tc358768_write(priv, 0x0610,0x23B8);
+	tc358768_write(priv, 0x0612,0x3001);
+	tc358768_write(priv, 0x0614,0x6334);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x4029);
+	tc358768_write(priv, 0x0604,0x0005);
+	tc358768_write(priv, 0x0610,0x23B9);
+	tc358768_write(priv, 0x0612,0x0022);
+	tc358768_write(priv, 0x0614,0x0044);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x4029);
+	tc358768_write(priv, 0x0604,0x0003);
+	tc358768_write(priv, 0x0610,0x12BA);
+	tc358768_write(priv, 0x0612,0x0063);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x4029);
+	tc358768_write(priv, 0x0604,0x0007);
+	tc358768_write(priv, 0x0610,0x0CC1);
+	tc358768_write(priv, 0x0612,0x0416);
+	tc358768_write(priv, 0x0614,0x100C);
+	tc358768_write(priv, 0x0616,0x0004);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x4029);
+	tc358768_write(priv, 0x0604,0x0003);
+	tc358768_write(priv, 0x0610,0x11C2);
+	tc358768_write(priv, 0x0612,0x0041);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x4029);
+	tc358768_write(priv, 0x0604,0x0004);
+	tc358768_write(priv, 0x0610,0x22C3);
+	tc358768_write(priv, 0x0612,0x0431);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x4029);
+	tc358768_write(priv, 0x0604,0x0006);
+	tc358768_write(priv, 0x0610,0x05C7);
+	tc358768_write(priv, 0x0612,0x6B23);
+	tc358768_write(priv, 0x0614,0x0049);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x1023);
+	tc358768_write(priv, 0x0604,0x0000);
+	tc358768_write(priv, 0x0610,0x00C5);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x4029);
+	tc358768_write(priv, 0x0604,0x0004);
+	tc358768_write(priv, 0x0610,0x37D0);
+	tc358768_write(priv, 0x0612,0xFFFF);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x4029);
+	tc358768_write(priv, 0x0604,0x0005);
+	tc358768_write(priv, 0x0610,0x63D2);
+	tc358768_write(priv, 0x0612,0x080B);
+	tc358768_write(priv, 0x0614,0x0088);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0008,0x0001);
+	tc358768_write(priv, 0x0050,0x0029);
+	tc358768_write(priv, 0x0022,0x000C);
+	tc358768_write(priv, 0x00E0,0x8000);
+	tc358768_write(priv, 0x00E8,0x01D3);
+	tc358768_write(priv, 0x00E8,0x0000);
+	tc358768_write(priv, 0x00E8,0x0101);
+	tc358768_write(priv, 0x00E8,0x2537);
+	tc358768_write(priv, 0x00E8,0x3138);
+	tc358768_write(priv, 0x00E8,0x0706);
+	tc358768_write(priv, 0x00E0,0xE000);
+	msleep(100);
+	tc358768_write(priv, 0x00E0,0x2000);
+	tc358768_write(priv, 0x00E0,0x0000);
+	msleep(10);
+	tc358768_write(priv, 0x0008,0x0001);
+	tc358768_write(priv, 0x0050,0x0029);
+	tc358768_write(priv, 0x0022,0x0027);
+	tc358768_write(priv, 0x00E0,0x8000);
+	tc358768_write(priv, 0x00E8,0x7CC8);
+	tc358768_write(priv, 0x00E8,0x5D6A);
+	tc358768_write(priv, 0x00E8,0x5353);
+	tc358768_write(priv, 0x00E8,0x4B45);
+	tc358768_write(priv, 0x00E8,0x4D35);
+	tc358768_write(priv, 0x00E8,0x494A);
+	tc358768_write(priv, 0x00E8,0x5366);
+	tc358768_write(priv, 0x00E8,0x4A57);
+	tc358768_write(priv, 0x00E8,0x3B48);
+	tc358768_write(priv, 0x00E8,0x062A);
+	tc358768_write(priv, 0x00E8,0x6A7C);
+	tc358768_write(priv, 0x00E8,0x535D);
+	tc358768_write(priv, 0x00E8,0x4553);
+	tc358768_write(priv, 0x00E8,0x354B);
+	tc358768_write(priv, 0x00E8,0x4A4D);
+	tc358768_write(priv, 0x00E8,0x6649);
+	tc358768_write(priv, 0x00E8,0x5753);
+	tc358768_write(priv, 0x00E8,0x484A);
+	tc358768_write(priv, 0x00E8,0x2A3B);
+	tc358768_write(priv, 0x00E8,0x0006);
+	tc358768_write(priv, 0x00E8,0x0000);
+	tc358768_write(priv, 0x00E0,0xE000);
+	msleep(100);
+	tc358768_write(priv, 0x00E0,0x2000);
+	tc358768_write(priv, 0x00E0,0x0000);
+	msleep(10);
+	tc358768_write(priv, 0x0008,0x0001);
+	tc358768_write(priv, 0x0050,0x0029);
+	tc358768_write(priv, 0x0022,0x0009);
+	tc358768_write(priv, 0x00E0,0x8000);
+	tc358768_write(priv, 0x00E8,0x00C6);
+	tc358768_write(priv, 0x00E8,0xFF00);
+	tc358768_write(priv, 0x00E8,0x0000);
+	tc358768_write(priv, 0x00E8,0x00FF);
+	tc358768_write(priv, 0x00E8,0x0000);
+	tc358768_write(priv, 0x00E0,0xE000);
+	msleep(100);
+	tc358768_write(priv, 0x00E0,0x2000);
+	tc358768_write(priv, 0x00E0,0x0000);
+	msleep(10);
+	tc358768_write(priv, 0x0602,0x4029);
+	tc358768_write(priv, 0x0604,0x0003);
+	tc358768_write(priv, 0x0610,0x08F4);
+	tc358768_write(priv, 0x0612,0x0077);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x1023);
+	tc358768_write(priv, 0x0604,0x0000);
+	tc358768_write(priv, 0x0610,0x1436);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x1023);
+	tc358768_write(priv, 0x0604,0x0000);
+	tc358768_write(priv, 0x0610,0x0035);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x1023);
+	tc358768_write(priv, 0x0604,0x0000);
+	tc358768_write(priv, 0x0610,0x0011);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x1023);
+	tc358768_write(priv, 0x0604,0x0000);
+	tc358768_write(priv, 0x0610,0x0029);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x4029);
+	tc358768_write(priv, 0x0604,0x0003);
+	tc358768_write(priv, 0x0610,0x5AF1);
+	tc358768_write(priv, 0x0612,0x005A);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0602,0x4029);
+	tc358768_write(priv, 0x0604,0x0003);
+	tc358768_write(priv, 0x0610,0xA5F0);
+	tc358768_write(priv, 0x0612,0x00A5);
+	tc358768_write(priv, 0x0600,0x0001);
+	msleep(50);
+	tc358768_write(priv, 0x0500,0x0086);//DSI lane setting, DSI mode=HS
+	tc358768_write(priv, 0x0502,0xA300);//bit set
+	tc358768_write(priv, 0x0500,0x8000);//Switch to DSI mode
+	tc358768_write(priv, 0x0502,0xC300);//
+	tc358768_write(priv, 0x0008,0x0037);//DSI-TX Format setting
+	tc358768_write(priv, 0x0050,0x003E);//DSI-TX Pixel stream packet Data Type setting
+	tc358768_write(priv, 0x0032,0x0000);//HSYNC Polarity
+	tc358768_write(priv, 0x0004,0x0044);//Configuration Control Register
+
+}
+
+static void LCD_panel_init(struct tc358768_priv *priv)
+{
+	LCD_power_on(priv);
+	msleep(100);  
+	tc358778_panel_init_mipi(priv);     
+	msleep(10);  
+}
+
+static int cwd686_i2c_probe(struct i2c_client *client,
+			      const struct i2c_device_id *id)
+{
+	struct tc358768_priv *priv;
+	struct device *dev = &client->dev;
+	struct device_node *np = dev->of_node;
+	int ret = 0;
+
+	if (!np)
+		return -ENODEV;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, priv);
+	priv->dev = dev;
+	priv->reset_gpio  = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+
+	if (IS_ERR(priv->reset_gpio))
+		return PTR_ERR(priv->reset_gpio);
+
+	priv->power_gpio  = devm_gpiod_get_optional(dev, "power", GPIOD_OUT_HIGH);
+
+	if (IS_ERR(priv->power_gpio))
+		return PTR_ERR(priv->power_gpio);
+
+	priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config);
+	if (IS_ERR(priv->regmap)) {
+		dev_err(dev, "Failed to init regmap\n");
+		return PTR_ERR(priv->regmap);
+	}
+
+	i2c_set_clientdata(client, priv);
+
+	LCD_panel_init(priv);
+
+	return ret;
+}
+#endif
+
+static const struct of_device_id cwd686_of_match[] = {
+	{ .compatible = "cw,cwd686" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, cwd686_of_match);
+
+static struct i2c_driver cwd686_driver = {
+	.driver = {
+		.name = "panel-cwd686",
+		.of_match_table = cwd686_of_match,
+	},
+	.probe = cwd686_i2c_probe,
+};
+module_i2c_driver(cwd686_driver);
+
+MODULE_DESCRIPTION("DRM Driver for cwd686 MIPI DSI panel");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 585ebe779..b494cede5 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -4003,6 +4003,29 @@ static const struct panel_desc arm_rtsm = {
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 };
 
+
+static const struct drm_display_mode clockwork_cpi3_lcd_mode = {
+	.clock = 50000,
+	.hdisplay = 480,
+	.hsync_start = 480 + 80,
+	.hsync_end = 480 + 80 + 20,
+	.htotal = 480 + 80 + 20 + 40,
+	.vdisplay = 1280,
+	.vsync_start = 1280 + 50,
+	.vsync_end = 1280 + 50+ 10,
+	.vtotal = 1280 + 50 + 10 + 20,
+	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+};
+
+static const struct panel_desc clockwork_cpi3_lcd = {
+	.modes = &clockwork_cpi3_lcd_mode,
+	.num_modes = 1,
+	.bpc = 6,
+	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
+	.connector_type = DRM_MODE_CONNECTOR_DPI,
+};
+
 static const struct of_device_id platform_of_match[] = {
 	{
 		.compatible = "ampire,am-1280800n3tzqw-t00h",
@@ -4419,6 +4442,9 @@ static const struct of_device_id platform_of_match[] = {
 	}, {
 		.compatible = "winstar,wf35ltiacd",
 		.data = &winstar_wf35ltiacd,
+	}, {
+		.compatible = "clockwork,cpi3-lcd",
+		.data = &clockwork_cpi3_lcd,
 	}, {
 		/* Must be the last entry */
 		.compatible = "panel-dpi",
