Browse Source

Split the address bus in top, and add stub for EEPROM, RTC and GPIO modules.

Godzil 9 years ago
parent
commit
68bec31f04
6 changed files with 561 additions and 63 deletions
  1. 93 0
      EEPROM.vhd
  2. 93 0
      GPIO.vhd
  3. 92 0
      RTC.vhd
  4. 128 2
      WonderMadeleine.qsf
  5. BIN
      WonderMadeleine.qws
  6. 155 61
      WonderMadeleine.vhd

+ 93 - 0
EEPROM.vhd

@@ -0,0 +1,93 @@
+-------------------------------------------------------------------------------
+--                    The WonderProject: WonderMadeleine                     --
+--                      (c) 2014  986-Studio / Godzil                        --
+--  http://www.986-studio.com  <godzil_nospambot at 986 dash studio dot com> --
+--                                                                           --
+-- EEPROM.vhd : EPROM module implementation                                  --
+--                                                                           --
+-- What this project is about:                                               --
+--                                                                           --
+-- This is a VHDL implementation of the Bandai 2001 / 2003 chip found in all --
+-- official WonderSwan Cartridge. It will ultimately provide a fully         --
+-- functional clone of the Bandai chip.                                      --
+--                                                                           --
+-- Licensed under the the Creative Common BY-NC-ND :                         --
+-- You are free to:                                                          --
+--   Share — copy and redistribute the material in any medium or format      --
+--                                                                           --
+--   The licensor cannot revoke these freedoms as long as you follow the     --
+--   license terms.                                                          --
+--                                                                           --
+-- Under the following terms:                                                --
+--                                                                           --
+--   Attribution   — You must give appropriate credit, provide a link to     --
+--                   the license, and indicate if changes were made. You     --
+--                   may do so in any reasonable manner, but not in any way  --
+--                   that suggests the licensor endorses you or your use.    --
+--   NonCommercial — You may not use the material for commercial purposes.   --
+--   NoDerivatives — If you remix, transform, or build upon the material,    --
+--                   you may not distribute the modified material.           --
+--                                                                           --
+--   No additional restrictions — You may not apply legal terms or           --
+--                                technological measures that legally        --
+--                                restrict others from doing anything the    --
+--                                license permits.                           --
+--                                                                           --
+-- Notices:                                                                  --
+--                                                                           --
+--   You do not have to comply with the license for elements of the material --
+--   in the public domain or where your use is permitted by an applicable    --
+--   exception or limitation.                                                --
+--                                                                           --
+--   No warranties are given. The license may not give you all of the        --
+--   permissions necessary for your intended use. For example, other rights  --
+--   such as publicity, privacy, or moral rights may limit how you use the   --
+--   material.                                                               --
+--                                                                           --
+--                                                                           --
+-- What does that mean:                                                      --
+--   You can use this code to program your own CPLD                          --
+--   You can build your own cartridge that use this CPLD (and you can even   --
+--      sell them!)                                                          --
+--   But you can't program CPLD and sell them directly                       --
+--   You are welcome to propose patch for supporting another CPLD or correct --
+--      bugs                                                                 --
+--   You can't integrate this code with another CPLD of FPGA project         --
+--                                                                           --
+-- If you have any doubt, please contact me I will be happy to help you      --
+--                                                                           --
+-- What is currently working: (as of 13 november 2014)                       --
+-- [X] - ROM Banking                                                         --
+-- [X] - SRAM Banking                                                        --
+-- [X] - WonderSwan boot unlock                                              --
+-- [ ] - EEPROM                                                              --
+-- [ ] - RTC                                                                 --
+-- [ ] - GPIO                                                                --
+-- [ ] - All other unknown parts                                             --
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity EepromRegs is
+    port(
+		sel:     in    std_logic;
+		nRD:     in    std_logic;
+		nWR:     in    std_logic;
+		regNum:  in    std_logic_vector(2 downto 0);
+		data:    inout std_logic_vector(7 downto 0);
+		clock:   in    std_logic;
+		-- EEPROM PINs
+		CS:      out   std_logic;
+		CLK:     out   std_logic;
+		DI:      in    std_logic;
+		DO:      out   std_logic
+	 );
+end EepromRegs;
+
+architecture Behavioral of EepromRegs is
+begin
+
+end architecture;

+ 93 - 0
GPIO.vhd

@@ -0,0 +1,93 @@
+-------------------------------------------------------------------------------
+--                    The WonderProject: WonderMadeleine                     --
+--                      (c) 2014  986-Studio / Godzil                        --
+--  http://www.986-studio.com  <godzil_nospambot at 986 dash studio dot com> --
+--                                                                           --
+-- GPIO.vhd : GPIO module implementation                                     --
+--                                                                           --
+-- What this project is about:                                               --
+--                                                                           --
+-- This is a VHDL implementation of the Bandai 2001 / 2003 chip found in all --
+-- official WonderSwan Cartridge. It will ultimately provide a fully         --
+-- functional clone of the Bandai chip.                                      --
+--                                                                           --
+-- Licensed under the the Creative Common BY-NC-ND :                         --
+-- You are free to:                                                          --
+--   Share — copy and redistribute the material in any medium or format      --
+--                                                                           --
+--   The licensor cannot revoke these freedoms as long as you follow the     --
+--   license terms.                                                          --
+--                                                                           --
+-- Under the following terms:                                                --
+--                                                                           --
+--   Attribution   — You must give appropriate credit, provide a link to     --
+--                   the license, and indicate if changes were made. You     --
+--                   may do so in any reasonable manner, but not in any way  --
+--                   that suggests the licensor endorses you or your use.    --
+--   NonCommercial — You may not use the material for commercial purposes.   --
+--   NoDerivatives — If you remix, transform, or build upon the material,    --
+--                   you may not distribute the modified material.           --
+--                                                                           --
+--   No additional restrictions — You may not apply legal terms or           --
+--                                technological measures that legally        --
+--                                restrict others from doing anything the    --
+--                                license permits.                           --
+--                                                                           --
+-- Notices:                                                                  --
+--                                                                           --
+--   You do not have to comply with the license for elements of the material --
+--   in the public domain or where your use is permitted by an applicable    --
+--   exception or limitation.                                                --
+--                                                                           --
+--   No warranties are given. The license may not give you all of the        --
+--   permissions necessary for your intended use. For example, other rights  --
+--   such as publicity, privacy, or moral rights may limit how you use the   --
+--   material.                                                               --
+--                                                                           --
+--                                                                           --
+-- What does that mean:                                                      --
+--   You can use this code to program your own CPLD                          --
+--   You can build your own cartridge that use this CPLD (and you can even   --
+--      sell them!)                                                          --
+--   But you can't program CPLD and sell them directly                       --
+--   You are welcome to propose patch for supporting another CPLD or correct --
+--      bugs                                                                 --
+--   You can't integrate this code with another CPLD of FPGA project         --
+--                                                                           --
+-- If you have any doubt, please contact me I will be happy to help you      --
+--                                                                           --
+-- What is currently working: (as of 13 november 2014)                       --
+-- [X] - ROM Banking                                                         --
+-- [X] - SRAM Banking                                                        --
+-- [X] - WonderSwan boot unlock                                              --
+-- [ ] - EEPROM                                                              --
+-- [ ] - RTC                                                                 --
+-- [ ] - GPIO                                                                --
+-- [ ] - All other unknown parts                                             --
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity GpioRegs is
+    port(
+        sel:     in    std_logic;
+		  nRD:     in    std_logic;
+		  nWR:     in    std_logic;
+        regNum:  in    std_logic;
+        data:    inout std_logic_vector(7 downto 0);
+        clock:   in    std_logic;
+        -- GPIO PINs
+        GPIO:    inout   std_logic_vector(1 downto 0)
+     );
+end GpioRegs;
+
+architecture Behavioral of GpioRegs is
+begin
+    main: process(sel, regNum, data)
+    begin
+
+    end process;
+end architecture;

+ 92 - 0
RTC.vhd

@@ -0,0 +1,92 @@
+-------------------------------------------------------------------------------
+--                    The WonderProject: WonderMadeleine                     --
+--                      (c) 2014  986-Studio / Godzil                        --
+--  http://www.986-studio.com  <godzil_nospambot at 986 dash studio dot com> --
+--                                                                           --
+-- RTC.vhd : RTC module implementation                                       --
+--                                                                           --
+-- What this project is about:                                               --
+--                                                                           --
+-- This is a VHDL implementation of the Bandai 2001 / 2003 chip found in all --
+-- official WonderSwan Cartridge. It will ultimately provide a fully         --
+-- functional clone of the Bandai chip.                                      --
+--                                                                           --
+-- Licensed under the the Creative Common BY-NC-ND :                         --
+-- You are free to:                                                          --
+--   Share — copy and redistribute the material in any medium or format      --
+--                                                                           --
+--   The licensor cannot revoke these freedoms as long as you follow the     --
+--   license terms.                                                          --
+--                                                                           --
+-- Under the following terms:                                                --
+--                                                                           --
+--   Attribution   — You must give appropriate credit, provide a link to     --
+--                   the license, and indicate if changes were made. You     --
+--                   may do so in any reasonable manner, but not in any way  --
+--                   that suggests the licensor endorses you or your use.    --
+--   NonCommercial — You may not use the material for commercial purposes.   --
+--   NoDerivatives — If you remix, transform, or build upon the material,    --
+--                   you may not distribute the modified material.           --
+--                                                                           --
+--   No additional restrictions — You may not apply legal terms or           --
+--                                technological measures that legally        --
+--                                restrict others from doing anything the    --
+--                                license permits.                           --
+--                                                                           --
+-- Notices:                                                                  --
+--                                                                           --
+--   You do not have to comply with the license for elements of the material --
+--   in the public domain or where your use is permitted by an applicable    --
+--   exception or limitation.                                                --
+--                                                                           --
+--   No warranties are given. The license may not give you all of the        --
+--   permissions necessary for your intended use. For example, other rights  --
+--   such as publicity, privacy, or moral rights may limit how you use the   --
+--   material.                                                               --
+--                                                                           --
+--                                                                           --
+-- What does that mean:                                                      --
+--   You can use this code to program your own CPLD                          --
+--   You can build your own cartridge that use this CPLD (and you can even   --
+--      sell them!)                                                          --
+--   But you can't program CPLD and sell them directly                       --
+--   You are welcome to propose patch for supporting another CPLD or correct --
+--      bugs                                                                 --
+--   You can't integrate this code with another CPLD of FPGA project         --
+--                                                                           --
+-- If you have any doubt, please contact me I will be happy to help you      --
+--                                                                           --
+-- What is currently working: (as of 13 november 2014)                       --
+-- [X] - ROM Banking                                                         --
+-- [X] - SRAM Banking                                                        --
+-- [X] - WonderSwan boot unlock                                              --
+-- [ ] - EEPROM                                                              --
+-- [ ] - RTC                                                                 --
+-- [ ] - GPIO                                                                --
+-- [ ] - All other unknown parts                                             --
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity RtcRegs is
+	 port(
+		sel:     in    std_logic;
+		nRD:     in    std_logic;
+		nWR:     in    std_logic;
+		regNum:  in    std_logic;
+		data:    inout std_logic_vector(7 downto 0);
+		clock:   in    std_logic;
+		-- RTC PINs
+		SDA:     inout std_logic;
+		CLK:     out   std_logic;
+		CS:      out   std_logic
+	 );
+end RtcRegs;
+
+architecture Behavioral of RtcRegs is
+begin
+
+end architecture;

+ 128 - 2
WonderMadeleine.qsf

@@ -37,7 +37,7 @@
 
 
 set_global_assignment -name FAMILY "MAX II"
-set_global_assignment -name DEVICE AUTO
+set_global_assignment -name DEVICE EPM240T100C3
 set_global_assignment -name TOP_LEVEL_ENTITY WonderMadeleine
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:43:30  OCTOBER 28, 2014"
@@ -46,4 +46,130 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name VHDL_FILE WonderMadeleine.vhd
+set_global_assignment -name VHDL_FILE WonderMadeleine.vhdset_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
+set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_12 -to SYS_CLK
+set_location_assignment PIN_69 -to RTC_DATA
+set_location_assignment PIN_7 -to nMBC
+set_location_assignment PIN_6 -to nWR
+set_location_assignment PIN_5 -to nRD
+set_location_assignment PIN_4 -to nIO
+set_location_assignment PIN_3 -to nSEL
+set_location_assignment PIN_2 -to nRESET
+set_location_assignment PIN_8 -to nINT
+set_location_assignment PIN_90 -to D_BUS[0]
+set_location_assignment PIN_89 -to D_BUS[1]
+set_location_assignment PIN_88 -to D_BUS[2]
+set_location_assignment PIN_87 -to D_BUS[3]
+set_location_assignment PIN_86 -to D_BUS[4]
+set_location_assignment PIN_85 -to D_BUS[5]
+set_location_assignment PIN_84 -to D_BUS[6]
+set_location_assignment PIN_83 -to D_BUS[7]
+set_location_assignment PIN_82 -to nROM_CS
+set_location_assignment PIN_81 -to nSRAM_CS
+set_location_assignment PIN_78 -to EXT_A[0]
+set_location_assignment PIN_77 -to EXT_A[1]
+set_location_assignment PIN_76 -to EXT_A[2]
+set_location_assignment PIN_75 -to EXT_A[3]
+set_location_assignment PIN_74 -to EXT_A[4]
+set_location_assignment PIN_73 -to EXT_A[5]
+set_location_assignment PIN_72 -to EXT_A[6]
+set_location_assignment PIN_71 -to EXT_A[7]
+set_location_assignment PIN_70 -to RTC_CS
+set_location_assignment PIN_68 -to RTC_CLK
+set_location_assignment PIN_67 -to GPIO[0]
+set_location_assignment PIN_66 -to GPIO[1]
+set_location_assignment PIN_58 -to EEP_CK
+set_location_assignment PIN_57 -to EEP_CS
+set_location_assignment PIN_56 -to EEP_DI
+set_location_assignment PIN_55 -to EEP_DO
+set_location_assignment PIN_15 -to user_reserve_1
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_1
+set_location_assignment PIN_16 -to user_reserve_2
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_2
+set_location_assignment PIN_17 -to user_reserve_3
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_3
+set_location_assignment PIN_18 -to user_reserve_4
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_4
+set_location_assignment PIN_19 -to user_reserve_5
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_5
+set_location_assignment PIN_20 -to user_reserve_6
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_6
+set_location_assignment PIN_21 -to user_reserve_7
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_7
+set_location_assignment PIN_26 -to user_reserve_8
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_8
+set_location_assignment PIN_27 -to user_reserve_9
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_9
+set_location_assignment PIN_29 -to user_reserve_10
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_10
+set_location_assignment PIN_28 -to user_reserve_11
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_11
+set_location_assignment PIN_30 -to user_reserve_12
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_12
+set_location_assignment PIN_33 -to user_reserve_13
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_13
+set_location_assignment PIN_34 -to user_reserve_14
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_14
+set_location_assignment PIN_35 -to user_reserve_15
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_15
+set_location_assignment PIN_36 -to user_reserve_16
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_16
+set_location_assignment PIN_37 -to user_reserve_17
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_17
+set_location_assignment PIN_38 -to user_reserve_18
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_18
+set_location_assignment PIN_39 -to user_reserve_19
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_19
+set_location_assignment PIN_40 -to user_reserve_20
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_20
+set_location_assignment PIN_41 -to user_reserve_21
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_21
+set_location_assignment PIN_42 -to user_reserve_22
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_22
+set_location_assignment PIN_47 -to user_reserve_23
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_23
+set_location_assignment PIN_48 -to user_reserve_24
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_24
+set_location_assignment PIN_49 -to user_reserve_25
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_25
+set_location_assignment PIN_50 -to user_reserve_26
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_26
+set_location_assignment PIN_51 -to user_reserve_27
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_27
+set_location_assignment PIN_52 -to user_reserve_28
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_28
+set_location_assignment PIN_53 -to user_reserve_29
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_29
+set_location_assignment PIN_54 -to user_reserve_30
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_30
+set_location_assignment PIN_62 -to user_reserve_31
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_31
+set_location_assignment PIN_64 -to user_reserve_32
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_32
+set_location_assignment PIN_14 -to user_reserve_33
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_33
+set_location_assignment PIN_43 -to user_reserve_34
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_34
+set_location_assignment PIN_44 -to user_reserve_35
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_35
+set_location_assignment PIN_1 -to user_reserve_36
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_36
+set_location_assignment PIN_61 -to user_reserve_37
+set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to user_reserve_37
+set_location_assignment PIN_100 -to A_BUS_H[16]
+set_location_assignment PIN_99 -to A_BUS_H[17]
+set_location_assignment PIN_98 -to A_BUS_H[18]
+set_location_assignment PIN_97 -to A_BUS_H[19]
+set_location_assignment PIN_96 -to A_BUS_L[3]
+set_location_assignment PIN_95 -to A_BUS_L[2]
+set_location_assignment PIN_92 -to A_BUS_L[1]
+set_location_assignment PIN_91 -to A_BUS_L[0]
+set_global_assignment -name VHDL_FILE EEPROM.vhd
+set_global_assignment -name VHDL_FILE RTC.vhd
+set_global_assignment -name VHDL_FILE GPIO.vhd

BIN
WonderMadeleine.qws


+ 155 - 61
WonderMadeleine.vhd

@@ -3,7 +3,9 @@
 --                      (c) 2014  986-Studio / Godzil                        --
 --  http://www.986-studio.com  <godzil_nospambot at 986 dash studio dot com> --
 --                                                                           --
--- What this file is about:                                                  --
+-- WonderMadeleine.vhd : TOP implementation                                  --
+--                                                                           --
+-- What this project is about:                                               --
 --                                                                           --
 -- This is a VHDL implementation of the Bandai 2001 / 2003 chip found in all --
 -- official WonderSwan Cartridge. It will ultimately provide a fully         --
@@ -72,8 +74,9 @@ use IEEE.NUMERIC_STD.ALL;
 
 entity WonderMadeleine is
     port(
-        D_BUS:   inout std_logic_vector( 7 downto 0);      -- 16 bit Data bus
-        A_BUS:   in    std_logic_vector(19 downto 0);      -- 20 bit Address bus
+        D_BUS:   inout std_logic_vector( 7 downto  0);      -- 16 bit Data bus
+        A_BUS_H: in    std_logic_vector(19 downto 16);      -- High part of 20 bit Address bus
+        A_BUS_L: in    std_logic_vector( 3 downto  0);      -- Low part of 20 bit Address bus
 
         nRD:     in    std_logic;                          -- /RD Signal
         nWR:     in    std_logic;                          -- /WR Signal
@@ -88,36 +91,92 @@ entity WonderMadeleine is
         nSEL:    in    std_logic;                          -- /SEL cart sel.
 
         EXT_A:   out   std_logic_vector( 7 downto 0);      -- 8 bit A bus extension from IO page
-        nSRAM_CS:out   std_logic;                                    -- SRAM ChipSelect
-        nROM_CS: out   std_logic;                                    -- ROM ChipSelect
-
-		  EEP_CS:  out   std_logic;
-		  EEP_SI:  in    std_logic;
-		  EEP_MO:  out   std_logic;
-		  EEP_CK:  out   std_logic;
-		  
-		  RTC_CLD: out   std_logic;
-		  RTC_DATA:inout std_logic;
-		  
+        nSRAM_CS:out   std_logic;                          -- SRAM ChipSelect
+        nROM_CS: out   std_logic;                          -- ROM ChipSelect
+
+        EEP_CS:  out   std_logic;
+        EEP_DI:  in    std_logic;
+        EEP_DO:  out   std_logic;
+        EEP_CK:  out   std_logic;
+
+        RTC_CLK: out   std_logic;
+        RTC_CS:  out   std_logic;
+        RTC_DATA:inout std_logic;
+
         GPIO:    inout std_logic_vector(1 downto 0)
     );
 end WonderMadeleine;
 
 architecture Behavioral of WonderMadeleine is
+    component GpioRegs is
+        port(
+            sel:     in    std_logic;
+				nRD:     in    std_logic;
+				nWR:     in    std_logic;
+            regNum:  in    std_logic;
+            data:    inout std_logic_vector(7 downto 0);
+            clock:   in    std_logic;
+            -- GPIO PINs
+            GPIO:    inout   std_logic_vector(1 downto 0)
+        );
+    end component;
+
+    component EepromRegs
+        port(
+            sel:     in    std_logic;
+				nRD:     in    std_logic;
+				nWR:     in    std_logic;
+            regNum:  in    std_logic_vector(2 downto 0);
+            data:    inout std_logic_vector(7 downto 0);
+            clock:   in    std_logic;
+            -- EEPROM PINs
+            CS:      out   std_logic;
+            CLK:     out   std_logic;
+            DI:      in    std_logic;
+            DO:      out   std_logic
+        );
+    end component;
+
+    component RtcRegs
+        port(
+            sel:     in    std_logic;
+				nRD:     in    std_logic;
+				nWR:     in    std_logic;
+            regNum:  in    std_logic;
+            data:    inout std_logic_vector(7 downto 0);
+            clock:   in    std_logic;
+            -- RTC PINs
+            SDA:     inout std_logic;
+            CLK:     out   std_logic;
+            CS:      out    std_logic
+        );
+    end component;
+
     signal rMBC:        std_logic;
     signal readD:       std_logic_vector(7 downto 0);
     signal writeD:      std_logic_vector(7 downto 0);
 
-	 signal nRWTop:      std_logic;
-	 
+    signal nRWTop:      std_logic;
+
     signal regC0:       std_logic_vector(7 downto 0);
     signal regC1:       std_logic_vector(7 downto 0);
     signal regC2:       std_logic_vector(7 downto 0);
     signal regC3:       std_logic_vector(7 downto 0);
+
+    signal eepromRegSel:   std_logic;
+    signal rtcRegSel:      std_logic;
+    signal gpioRegSel:     std_logic;
+    signal ioRegNum:       std_logic_vector(7 downto 0);
 begin
+
+    -- Instantiates all needed components
+    gpioInst:   GpioRegs   port map(gpioRegSel,   nRd, nWR, ioRegNum(0), D_BUS, SYS_CLK, GPIO);
+    eepromInst: EepromRegs port map(eepromRegSel, nRd, nWR, ioRegNum(2 downto 0), D_BUS, SYS_CLK, EEP_CS, EEP_CK, EEP_DI, EEP_DO);
+    rtcInst:    RtcRegs    port map(rtcRegSel,    nRd, nWR, ioRegNum(0), D_BUS, SYS_CLK, RTC_DATA, RTC_CLK, RTC_CS);
+
     nINT <= 'Z';
     nMBC <= rMBC;
-	 nRWTop <= nRD and nWR;
+    nRWTop <= nRD and nWR;
     d_latches: process (nSEL, nIO, nRD, nWR, D_BUS, writeD, readD)
     begin
         if (nSEL='0' and nIO = '0' and nRD = '0' and nWR = '1') then
@@ -126,76 +185,109 @@ begin
             else
                 D_BUS <= "ZZZZZZZZ";
             end if;
-	         readD <= D_BUS;
-	  	  elsif (nSEL='0' and nIO = '0' and nRD = '1' and nWR = '0') then
+            readD <= D_BUS;
+        elsif (nSEL='0' and nIO = '0' and nRD = '1' and nWR = '0') then
             D_BUS <= "ZZZZZZZZ";
             readD <= D_BUS;
         else
             D_BUS <= "ZZZZZZZZ";
-				readD <= "11111111";
+            readD <= "11111111";
         end if;
     end process;
 
-    main: process(nSEL, nIO, nRD, nWR, nRWTop, A_BUS, nRESET, readD, regC0, regC1, regC2, regC3)
-    variable regNum:     std_logic_vector(7 downto 0);
-	 variable validRange: std_logic;
+    main: process(nSEL, nIO, nRD, nWR, nRWTop, A_BUS_H, A_BUS_L, nRESET, readD, regC0, regC1, regC2, regC3)
+    variable validRange: std_logic;
     begin
-        regNum(7 downto 6) := "00";
-        regNum(5 downto 4) := A_BUS(17 downto 16);
-        regNum(3 downto 0) := A_BUS( 3 downto  0);
-		  
+        ioRegNum(7 downto 4) <= A_BUS_H(19 downto 16);
+        ioRegNum(3 downto 0) <= A_BUS_L( 3 downto  0);
+
         if (nRESET = '0') then
-            nSRAM_CS <= '1';
-            nROM_CS  <= '1';
-            regC0 <= X"FF";
-            regC1 <= X"FF";
-            regC2 <= X"FF";
-            regC3 <= X"FF";
-        elsif (nSEL = '0' and validRange = '1') then
+            nSRAM_CS     <= '1';
+            nROM_CS      <= '1';
+            regC0        <= X"FF";
+            regC1        <= X"FF";
+            regC2        <= X"FF";
+            regC3        <= X"FF";
+            eepromRegSel <= '0';
+            rtcRegSel    <= '0';
+            gpioRegSel   <= '0';
+			elsif (nSEL = '0' and validRange = '1') then
             if(nIO = '0') then
                 nSRAM_CS <= '1'; nROM_CS <= '1';
                 if (falling_edge(nRWTop) and nRD = '0' and nWR = '1') then
-                    case regNum is
-                        when X"00"  => writeD <= regC0;
-                        when X"01"  => writeD <= regC1;
-                        when X"02"  => writeD <= regC2;
-                        when X"03"  => writeD <= regC3;
-                        when others => writeD <= X"FF";
+                    case ioRegNum is
+                        when X"C0"  => writeD <= regC0; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
+                        when X"C1"  => writeD <= regC1; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
+                        when X"C2"  => writeD <= regC2; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
+                        when X"C3"  => writeD <= regC3; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
+								when X"C4"  => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
+								when X"C5"  => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
+								when X"C6"  => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
+								when X"C7"  => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
+								when X"C8"  => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
+								when X"CA"  => eepromRegSel <= '0'; rtcRegSel <= '1'; gpioRegSel <= '0';
+								when X"CB"  => eepromRegSel <= '0'; rtcRegSel <= '1'; gpioRegSel <= '0';
+                        when X"CC"  => eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '1';
+								when X"CD"  => eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '1';
+                        when others => writeD <= X"FF"; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
                     end case;
                 elsif (falling_edge(nRWTop) and nRD = '1' and nWR = '0') then
-                    case regNum is
-                        when X"00"  => regC0 <= readD;
-                        when X"01"  => regC1 <= readD;
-                        when X"02"  => regC2 <= readD;
-                        when X"03"  => regC3 <= readD;
+                    case ioRegNum is
+                        when X"C0"  => regC0 <= readD; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
+                        when X"C1"  => regC1 <= readD; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
+                        when X"C2"  => regC2 <= readD; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
+                        when X"C3"  => regC3 <= readD; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
+								when X"C4"  => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
+								when X"C5"  => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
+								when X"C6"  => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
+								when X"C7"  => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
+								when X"C8"  => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
+								when X"CA"  => eepromRegSel <= '0'; rtcRegSel <= '1'; gpioRegSel <= '0';
+								when X"CB"  => eepromRegSel <= '0'; rtcRegSel <= '1'; gpioRegSel <= '0';
+                        when X"CC"  => eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '1';
+								when X"CD"  => eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '1';
                         when others => null;
                     end case;
                 end if;
             elsif (nRD = '0' or nWR = '0') then
                 -- Not IO
-                case A_BUS(19 downto 16) is
+                case A_BUS_H is
                     when X"0"   => nSRAM_CS <= '1'; nROM_CS <= '1';
                     when X"1"   => nSRAM_CS <= '0'; nROM_CS <= '1';
                     when others => nSRAM_CS <= '1'; nROM_CS <= '0';
                 end case;
+                -- Be sure the reg are not sel during non IO
+                eepromRegSel <= '0';
+                rtcRegSel    <= '0';
+                gpioRegSel   <= '0';
             else
+                -- Be sure the reg are not sel during non IO
+                eepromRegSel <= '0';
+                rtcRegSel    <= '0';
+                gpioRegSel   <= '0';
+                -- Not accessing SRAM or ROM mapping
                 nSRAM_CS <= '1'; nROM_CS <= '1';
             end if;
-        else -- Not Sel
+        else -- Cart is not sel
             nSRAM_CS <= '1'; nROM_CS <= '1';
+
+            -- Be sure the reg are not sel during non IO
+            eepromRegSel <= '0';
+            rtcRegSel    <= '0';
+            gpioRegSel   <= '0';
         end if;
 
-        case A_BUS(19 downto 16) is
+        case A_BUS_H(19 downto 16) is
             when X"0"   => validRange := '0'; EXT_A <= X"00";
-            when X"1"   => validRange := '1'; EXT_A <= regC1; --mbcReg(1); --C1;
-            when X"2"   => validRange := '1'; EXT_A <= regC2; --mbcReg(2); --C2;
-            when X"3"   => validRange := '1'; EXT_A <= regC3; --mbcReg(3); --C3;
-            when others => validRange := '1'; EXT_A(7 downto 4) <= regC0(3 downto 0); --mbcReg(0)(3 downto 0); --C0
-                           EXT_A(3 downto 0) <= A_BUS(19 downto 16);
+            when X"1"   => validRange := '1'; EXT_A <= regC1;
+            when X"2"   => validRange := '1'; EXT_A <= regC2;
+            when X"3"   => validRange := '1'; EXT_A <= regC3;
+            when others => validRange := '1'; EXT_A(7 downto 4) <= regC0(3 downto 0);
+                           EXT_A(3 downto 0) <= A_BUS_H;
         end case;
     end process;
 
-    mbc_lock: process (SYS_CLK, nRESET, A_BUS)
+    mbc_lock: process (SYS_CLK, nRESET, A_BUS_H, A_BUS_L)
         type STATE_TYPE is (sWait, sWaitForA5, sA1, SA2, SA3, sA4,
                             sB1, sB2, sB3, sB4, sB5, sB6, sC, sD,
                             sE, sF1, sF2, sF3, sG, sH, sI, sJ1, sJ2,
@@ -205,8 +297,8 @@ begin
         if (nRESET = '0') then
             state := sWaitForA5;
         elsif (rising_edge(SYS_CLK) and state = sWaitForA5
-                                    and A_BUS(19 downto 16) = X"A"
-                                    and A_BUS( 5 downto  0) = X"5" ) then
+                                    and A_BUS_H = X"A"
+                                    and A_BUS_L = X"5" ) then
             state := sA1;
         elsif (rising_edge(SYS_CLK)) then
             case state is
@@ -243,7 +335,8 @@ end architecture;
 -- Test script...
 -- restart
 -- force -freeze sim:/wondermadeleine/SYS_CLK 1 0, 0 {50 ps} -r 100
--- force -freeze sim:/wondermadeleine/A_BUS 11000000000000000011 0
+-- force -freeze sim:/wondermadeleine/A_BUS_H 1100 0
+-- force -freeze sim:/wondermadeleine/A_BUS_L 0011 0
 -- force -freeze sim:/wondermadeleine/D_BUS 10101010 0 -cancel 200
 -- force -freeze sim:/wondermadeleine/regC0 01011011 0
 -- force -freeze sim:/wondermadeleine/regC1 10111101 0
@@ -269,7 +362,8 @@ end architecture;
 -- force -freeze sim:/wondermadeleine/nIO 1 330
 -- force -freeze sim:/wondermadeleine/nSEL 1 350
 
--- force -freeze sim:/wondermadeleine/A_BUS 00110000000000000000 400
+-- force -freeze sim:/wondermadeleine/A_BUS_H 0011 400
+-- force -freeze sim:/wondermadeleine/A_BUS_L 0000 400
 -- force -freeze sim:/wondermadeleine/nRD 0 410
 -- force -freeze sim:/wondermadeleine/nRD 1 420
 -- force -freeze sim:/wondermadeleine/nSEL 0 430
@@ -277,7 +371,7 @@ end architecture;
 -- force -freeze sim:/wondermadeleine/nRD 1 450
 -- force -freeze sim:/wondermadeleine/nSEL 1 460
 
--- force -freeze sim:/wondermadeleine/A_BUS 10100000000000000000 500
+-- force -freeze sim:/wondermadeleine/A_BUS_H 1010 500
 -- force -freeze sim:/wondermadeleine/nWR 0 510
 -- force -freeze sim:/wondermadeleine/nWR 1 520
 -- force -freeze sim:/wondermadeleine/nSEL 0 530
@@ -285,7 +379,7 @@ end architecture;
 -- force -freeze sim:/wondermadeleine/nWR 1 550
 -- force -freeze sim:/wondermadeleine/nSEL 1 560
 
--- force -freeze sim:/wondermadeleine/A_BUS 00000000000000000000 600
+-- force -freeze sim:/wondermadeleine/A_BUS_H 0000 600
 -- force -freeze sim:/wondermadeleine/nWR 0 610
 -- force -freeze sim:/wondermadeleine/nWR 1 620
 -- force -freeze sim:/wondermadeleine/nSEL 0 630
@@ -293,7 +387,7 @@ end architecture;
 -- force -freeze sim:/wondermadeleine/nWR 1 650
 -- force -freeze sim:/wondermadeleine/nSEL 1 660
 
--- force -freeze sim:/wondermadeleine/A_BUS 00010000000000000000 700
+-- force -freeze sim:/wondermadeleine/A_BUS_H 0001 700
 -- force -freeze sim:/wondermadeleine/nRD 0 710
 -- force -freeze sim:/wondermadeleine/nRD 1 720
 -- force -freeze sim:/wondermadeleine/nSEL 0 730