FspApiEntryT.nasm 19 KB

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  1. ;; @file
  2. ; Provide FSP API entry points.
  3. ;
  4. ; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>
  5. ; SPDX-License-Identifier: BSD-2-Clause-Patent
  6. ;;
  7. SECTION .text
  8. %include "SaveRestoreSseNasm.inc"
  9. %include "MicrocodeLoadNasm.inc"
  10. ;
  11. ; Following are fixed PCDs
  12. ;
  13. extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase))
  14. extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
  15. extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
  16. ;
  17. ; Following functions will be provided in PlatformSecLib
  18. ;
  19. extern ASM_PFX(AsmGetFspBaseAddress)
  20. extern ASM_PFX(AsmGetFspInfoHeaderNoStack)
  21. ;extern ASM_PFX(LoadMicrocode) ; @todo: needs a weak implementation
  22. extern ASM_PFX(SecPlatformInit) ; @todo: needs a weak implementation
  23. extern ASM_PFX(SecCarInit)
  24. ;
  25. ; Define the data length that we saved on the stack top
  26. ;
  27. DATA_LEN_OF_PER0 EQU 18h
  28. DATA_LEN_OF_MCUD EQU 18h
  29. DATA_LEN_AT_STACK_TOP EQU (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)
  30. ;
  31. ; @todo: These structures are moved from MicrocodeLoadNasm.inc to avoid
  32. ; build error. This needs to be fixed later on.
  33. ;
  34. struc MicrocodeHdr
  35. .MicrocodeHdrVersion: resd 1
  36. .MicrocodeHdrRevision: resd 1
  37. .MicrocodeHdrDate: resd 1
  38. .MicrocodeHdrProcessor: resd 1
  39. .MicrocodeHdrChecksum: resd 1
  40. .MicrocodeHdrLoader: resd 1
  41. .MicrocodeHdrFlags: resd 1
  42. .MicrocodeHdrDataSize: resd 1
  43. .MicrocodeHdrTotalSize: resd 1
  44. .MicrocodeHdrRsvd: resd 3
  45. .size:
  46. endstruc
  47. struc ExtSigHdr
  48. .ExtSigHdrCount: resd 1
  49. .ExtSigHdrChecksum: resd 1
  50. .ExtSigHdrRsvd: resd 3
  51. .size:
  52. endstruc
  53. struc ExtSig
  54. .ExtSigProcessor: resd 1
  55. .ExtSigFlags: resd 1
  56. .ExtSigChecksum: resd 1
  57. .size:
  58. endstruc
  59. struc LoadMicrocodeParams
  60. ; FSP_UPD_HEADER {
  61. .FspUpdHeader: resd 8
  62. ; }
  63. ; FSPT_CORE_UPD {
  64. .MicrocodeCodeAddr: resd 1
  65. .MicrocodeCodeSize: resd 1
  66. .CodeRegionBase: resd 1
  67. .CodeRegionSize: resd 1
  68. ; }
  69. .size:
  70. endstruc
  71. struc LoadMicrocodeParamsFsp22
  72. ; FSP_UPD_HEADER {
  73. .FspUpdHeaderSignature: resd 2
  74. .FspUpdHeaderRevision: resb 1
  75. .FspUpdHeaderReserved: resb 23
  76. ; }
  77. ; FSPT_ARCH_UPD {
  78. .FsptArchRevision: resb 1
  79. .FsptArchReserved: resb 3
  80. .FsptArchUpd: resd 7
  81. ; }
  82. ; FSPT_CORE_UPD {
  83. .MicrocodeCodeAddr: resd 1
  84. .MicrocodeCodeSize: resd 1
  85. .CodeRegionBase: resd 1
  86. .CodeRegionSize: resd 1
  87. ; }
  88. .size:
  89. endstruc
  90. struc LoadMicrocodeParamsFsp24
  91. ; FSP_UPD_HEADER {
  92. .FspUpdHeaderSignature: resd 2
  93. .FspUpdHeaderRevision: resb 1
  94. .FspUpdHeaderReserved: resb 23
  95. ; }
  96. ; FSPT_ARCH2_UPD {
  97. .FsptArchRevision: resb 1
  98. .FsptArchReserved: resb 3
  99. .FsptArchLength: resd 1
  100. .FspDebugHandler resq 1
  101. .FsptArchUpd: resd 4
  102. ; }
  103. ; FSPT_CORE_UPD {
  104. .MicrocodeCodeAddr: resq 1
  105. .MicrocodeCodeSize: resq 1
  106. .CodeRegionBase: resq 1
  107. .CodeRegionSize: resq 1
  108. ; }
  109. .size:
  110. endstruc
  111. ;
  112. ; Define SSE macros
  113. ;
  114. ;
  115. ;args 1: ReturnAddress 2:MmxRegister
  116. ;
  117. %macro LOAD_MMX_EXT 2
  118. mov esi, %1
  119. movd %2, esi ; save ReturnAddress into MMX
  120. %endmacro
  121. ;
  122. ;args 1: RoutineLabel 2:MmxRegister
  123. ;
  124. %macro CALL_MMX_EXT 2
  125. mov esi, %%ReturnAddress
  126. movd %2, esi ; save ReturnAddress into MMX
  127. jmp %1
  128. %%ReturnAddress:
  129. %endmacro
  130. ;
  131. ;arg 1:MmxRegister
  132. ;
  133. %macro RET_ESI_EXT 1
  134. movd esi, %1 ; move ReturnAddress from MMX to ESI
  135. jmp esi
  136. %endmacro
  137. ;
  138. ;arg 1:RoutineLabel
  139. ;
  140. %macro CALL_MMX 1
  141. CALL_MMX_EXT %1, mm7
  142. %endmacro
  143. %macro RET_ESI 0
  144. RET_ESI_EXT mm7
  145. %endmacro
  146. %macro CALL_EDI 1
  147. mov edi, %%ReturnAddress
  148. jmp %1
  149. %%ReturnAddress:
  150. %endmacro
  151. %macro CALL_EBP 1
  152. mov ebp, %%ReturnAddress
  153. jmp %1
  154. %%ReturnAddress:
  155. %endmacro
  156. %macro RET_EBP 0
  157. jmp ebp ; restore EIP from EBP
  158. %endmacro
  159. ;
  160. ; Load UPD region pointer in ECX
  161. ;
  162. global ASM_PFX(LoadUpdPointerToECX)
  163. ASM_PFX(LoadUpdPointerToECX):
  164. ;
  165. ; esp + 4 is input UPD parameter
  166. ; If esp + 4 is NULL the default UPD should be used
  167. ; ecx will be the UPD region that should be used
  168. ;
  169. mov ecx, dword [esp + 4]
  170. cmp ecx, 0
  171. jnz ParamValid
  172. ;
  173. ; Fall back to default UPD region
  174. ;
  175. CALL_EDI ASM_PFX(AsmGetFspInfoHeaderNoStack)
  176. mov ecx, DWORD [eax + 01Ch] ; Read FsptImageBaseAddress
  177. add ecx, DWORD [eax + 024h] ; Get Cfg Region base address = FsptImageBaseAddress + CfgRegionOffset
  178. ParamValid:
  179. RET_EBP
  180. ;
  181. ; @todo: The strong/weak implementation does not work.
  182. ; This needs to be reviewed later.
  183. ;
  184. ;------------------------------------------------------------------------------
  185. ;
  186. ;;global ASM_PFX(SecPlatformInitDefault)
  187. ;ASM_PFX(SecPlatformInitDefault):
  188. ; ; Inputs:
  189. ; ; mm7 -> Return address
  190. ; ; Outputs:
  191. ; ; eax -> 0 - Successful, Non-zero - Failed.
  192. ; ; Register Usage:
  193. ; ; eax is cleared and ebp is used for return address.
  194. ; ; All others reserved.
  195. ;
  196. ; ; Save return address to EBP
  197. ; movd ebp, mm7
  198. ;
  199. ; xor eax, eax
  200. ;Exit1:
  201. ; jmp ebp
  202. ;------------------------------------------------------------------------------
  203. global ASM_PFX(LoadMicrocodeDefault)
  204. ASM_PFX(LoadMicrocodeDefault):
  205. ; Inputs:
  206. ; ecx -> UPD region contains LoadMicrocodeParams pointer
  207. ; Register Usage:
  208. ; All are destroyed
  209. ; Assumptions:
  210. ; No memory available, stack is hard-coded and used for return address
  211. ; Executed by SBSP and NBSP
  212. ; Beginning of microcode update region starts on paragraph boundary
  213. ;
  214. ; Save return address to EBP
  215. ;
  216. movd ebp, mm7
  217. mov esp, ecx ; ECX has been assigned to UPD region
  218. cmp esp, 0
  219. jz ParamError
  220. ; skip loading Microcode if the MicrocodeCodeSize is zero
  221. ; and report error if size is less than 2k
  222. ; first check UPD header revision
  223. cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
  224. jb Fsp20UpdHeader
  225. cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
  226. je Fsp24UpdHeader
  227. jmp Fsp22UpdHeader
  228. Fsp20UpdHeader:
  229. ; UPD structure is compliant with FSP spec 2.0/2.1
  230. mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]
  231. cmp eax, 0
  232. jz Exit2
  233. cmp eax, 0800h
  234. jl ParamError
  235. mov esi, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]
  236. cmp esi, 0
  237. jnz CheckMainHeader
  238. jmp ParamError
  239. Fsp22UpdHeader:
  240. ; UPD structure is compliant with FSP spec 2.2
  241. mov eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]
  242. cmp eax, 0
  243. jz Exit2
  244. cmp eax, 0800h
  245. jl ParamError
  246. mov esi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]
  247. cmp esi, 0
  248. jnz CheckMainHeader
  249. jmp ParamError
  250. Fsp24UpdHeader:
  251. ; UPD structure is compliant with FSP spec 2.4
  252. mov eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
  253. cmp eax, 0
  254. jz Exit2
  255. cmp eax, 0800h
  256. jl ParamError
  257. mov esi, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
  258. cmp esi, 0
  259. jnz CheckMainHeader
  260. ParamError:
  261. mov eax, 080000002h
  262. jmp Exit2
  263. CheckMainHeader:
  264. ; Get processor signature and platform ID from the installed processor
  265. ; and save into registers for later use
  266. ; ebx = processor signature
  267. ; edx = platform ID
  268. mov eax, 1
  269. cpuid
  270. mov ebx, eax
  271. mov ecx, MSR_IA32_PLATFORM_ID
  272. rdmsr
  273. mov ecx, edx
  274. shr ecx, 50-32 ; shift (50d-32d=18d=0x12) bits
  275. and ecx, 7h ; platform id at bit[52..50]
  276. mov edx, 1
  277. shl edx, cl
  278. ; Current register usage
  279. ; esp -> stack with parameters
  280. ; esi -> microcode update to check
  281. ; ebx = processor signature
  282. ; edx = platform ID
  283. ; Check for valid microcode header
  284. ; Minimal test checking for header version and loader version as 1
  285. mov eax, dword 1
  286. cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], eax
  287. jne AdvanceFixedSize
  288. cmp dword [esi + MicrocodeHdr.MicrocodeHdrLoader], eax
  289. jne AdvanceFixedSize
  290. ; Check if signature and plaform ID match
  291. cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]
  292. jne LoadMicrocodeDefault1
  293. test edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]
  294. jnz LoadCheck ; Jif signature and platform ID match
  295. LoadMicrocodeDefault1:
  296. ; Check if extended header exists
  297. ; First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid
  298. xor eax, eax
  299. cmp dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax
  300. je NextMicrocode
  301. cmp dword [esi + MicrocodeHdr.MicrocodeHdrDataSize], eax
  302. je NextMicrocode
  303. ; Then verify total size - sizeof header > data size
  304. mov ecx, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize]
  305. sub ecx, MicrocodeHdr.size
  306. cmp ecx, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize]
  307. jng NextMicrocode ; Jif extended header does not exist
  308. ; Set edi -> extended header
  309. mov edi, esi
  310. add edi, MicrocodeHdr.size
  311. add edi, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize]
  312. ; Get count of extended structures
  313. mov ecx, dword [edi + ExtSigHdr.ExtSigHdrCount]
  314. ; Move pointer to first signature structure
  315. add edi, ExtSigHdr.size
  316. CheckExtSig:
  317. ; Check if extended signature and platform ID match
  318. cmp dword [edi + ExtSig.ExtSigProcessor], ebx
  319. jne LoadMicrocodeDefault2
  320. test dword [edi + ExtSig.ExtSigFlags], edx
  321. jnz LoadCheck ; Jif signature and platform ID match
  322. LoadMicrocodeDefault2:
  323. ; Check if any more extended signatures exist
  324. add edi, ExtSig.size
  325. loop CheckExtSig
  326. NextMicrocode:
  327. ; Advance just after end of this microcode
  328. xor eax, eax
  329. cmp dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax
  330. je LoadMicrocodeDefault3
  331. add esi, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize]
  332. jmp CheckAddress
  333. LoadMicrocodeDefault3:
  334. add esi, dword 2048
  335. jmp CheckAddress
  336. AdvanceFixedSize:
  337. ; Advance by 4X dwords
  338. add esi, dword 1024
  339. CheckAddress:
  340. ; Check UPD header revision
  341. cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
  342. jb Fsp20UpdHeader1
  343. cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
  344. je Fsp24UpdHeader1;
  345. jmp Fsp22UpdHeader1
  346. Fsp20UpdHeader1:
  347. ; UPD structure is compliant with FSP spec 2.0/2.1
  348. ; Is automatic size detection ?
  349. mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]
  350. cmp eax, 0ffffffffh
  351. jz LoadMicrocodeDefault4
  352. ; Address >= microcode region address + microcode region size?
  353. add eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]
  354. cmp esi, eax
  355. jae Done ;Jif address is outside of microcode region
  356. jmp CheckMainHeader
  357. Fsp22UpdHeader1:
  358. ; UPD structure is compliant with FSP spec 2.2
  359. ; Is automatic size detection ?
  360. mov eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]
  361. cmp eax, 0ffffffffh
  362. jz LoadMicrocodeDefault4
  363. ; Address >= microcode region address + microcode region size?
  364. add eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]
  365. cmp esi, eax
  366. jae Done ;Jif address is outside of microcode region
  367. jmp CheckMainHeader
  368. Fsp24UpdHeader1:
  369. ; UPD structure is compliant with FSP spec 2.4
  370. ; Is automatic size detection ?
  371. mov eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
  372. cmp eax, 0ffffffffh
  373. jz LoadMicrocodeDefault4
  374. ; Address >= microcode region address + microcode region size?
  375. add eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
  376. cmp esi, eax
  377. jae Done ;Jif address is outside of microcode region
  378. jmp CheckMainHeader
  379. LoadMicrocodeDefault4:
  380. ; Is valid Microcode start point ?
  381. cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh
  382. jz Done
  383. LoadCheck:
  384. ; Get the revision of the current microcode update loaded
  385. mov ecx, MSR_IA32_BIOS_SIGN_ID
  386. xor eax, eax ; Clear EAX
  387. xor edx, edx ; Clear EDX
  388. wrmsr ; Load 0 to MSR at 8Bh
  389. mov eax, 1
  390. cpuid
  391. mov ecx, MSR_IA32_BIOS_SIGN_ID
  392. rdmsr ; Get current microcode signature
  393. ; Verify this microcode update is not already loaded
  394. cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx
  395. je Continue
  396. LoadMicrocode:
  397. ; EAX contains the linear address of the start of the Update Data
  398. ; EDX contains zero
  399. ; ECX contains 79h (IA32_BIOS_UPDT_TRIG)
  400. ; Start microcode load with wrmsr
  401. mov eax, esi
  402. add eax, MicrocodeHdr.size
  403. xor edx, edx
  404. mov ecx, MSR_IA32_BIOS_UPDT_TRIG
  405. wrmsr
  406. mov eax, 1
  407. cpuid
  408. Continue:
  409. jmp NextMicrocode
  410. Done:
  411. mov eax, 1
  412. cpuid
  413. mov ecx, MSR_IA32_BIOS_SIGN_ID
  414. rdmsr ; Get current microcode signature
  415. xor eax, eax
  416. cmp edx, 0
  417. jnz Exit2
  418. mov eax, 08000000Eh
  419. Exit2:
  420. jmp ebp
  421. ;
  422. ; EstablishStackFsp: EDI should be preserved cross this function
  423. ;
  424. global ASM_PFX(EstablishStackFsp)
  425. ASM_PFX(EstablishStackFsp):
  426. ;
  427. ; Save parameter pointer in edx
  428. ;
  429. mov edx, ecx ; ECX has been assigned to UPD region
  430. ;
  431. ; Enable FSP STACK
  432. ;
  433. mov esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
  434. add esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]
  435. push DATA_LEN_OF_MCUD ; Size of the data region
  436. push 4455434Dh ; Signature of the data region 'MCUD'
  437. ; check UPD structure revision (edx + 8)
  438. cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
  439. jb Fsp20UpdHeader2
  440. cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
  441. je Fsp24UpdHeader2
  442. jmp Fsp22UpdHeader2
  443. Fsp20UpdHeader2:
  444. ; UPD structure is compliant with FSP spec 2.0/2.1
  445. push dword [edx + LoadMicrocodeParams.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 12
  446. push dword [edx + LoadMicrocodeParams.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8
  447. push dword [edx + LoadMicrocodeParams.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4
  448. push dword [edx + LoadMicrocodeParams.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0
  449. jmp ContinueAfterUpdPush
  450. Fsp22UpdHeader2:
  451. ; UPD structure is compliant with FSP spec 2.2
  452. push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 12
  453. push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8
  454. push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4
  455. push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0
  456. jmp ContinueAfterUpdPush
  457. Fsp24UpdHeader2:
  458. ; UPD structure is compliant with FSP spec 2.4
  459. push dword [edx + LoadMicrocodeParamsFsp24.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 24
  460. push dword [edx + LoadMicrocodeParamsFsp24.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 16
  461. push dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 8
  462. push dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0
  463. ContinueAfterUpdPush:
  464. ;
  465. ; Save API entry/exit timestamp into stack
  466. ;
  467. push DATA_LEN_OF_PER0 ; Size of the data region
  468. push 30524550h ; Signature of the data region 'PER0'
  469. rdtsc
  470. push edx
  471. push eax
  472. LOAD_EDX
  473. push edx
  474. LOAD_EAX
  475. push eax
  476. ;
  477. ; Terminator for the data on stack
  478. ;
  479. push 0
  480. ;
  481. ; Set ECX/EDX to the BootLoader temporary memory range
  482. ;
  483. mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
  484. mov edx, ecx
  485. add edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]
  486. sub edx, [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))]
  487. cmp ecx, edx ;If PcdFspReservedBufferSize >= PcdTemporaryRamSize, then error.
  488. jb EstablishStackFspSuccess
  489. mov eax, 80000003h ;EFI_UNSUPPORTED
  490. jmp EstablishStackFspExit
  491. EstablishStackFspSuccess:
  492. xor eax, eax
  493. EstablishStackFspExit:
  494. RET_ESI
  495. ;----------------------------------------------------------------------------
  496. ; TempRamInit API
  497. ;
  498. ; This FSP API will load the microcode update, enable code caching for the
  499. ; region specified by the boot loader and also setup a temporary stack to be
  500. ; used till main memory is initialized.
  501. ;
  502. ;----------------------------------------------------------------------------
  503. global ASM_PFX(TempRamInitApi)
  504. ASM_PFX(TempRamInitApi):
  505. ;
  506. ; Ensure SSE is enabled
  507. ;
  508. ENABLE_SSE
  509. ;
  510. ; Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6
  511. ;
  512. SAVE_REGS
  513. ;
  514. ; Save timestamp into XMM6
  515. ;
  516. rdtsc
  517. SAVE_EAX
  518. SAVE_EDX
  519. CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
  520. SAVE_ECX ; save UPD param to slot 3 in xmm6
  521. ;
  522. ; Sec Platform Init
  523. ;
  524. CALL_MMX ASM_PFX(SecPlatformInit)
  525. cmp eax, 0
  526. jnz TempRamInitExit
  527. ; Load microcode
  528. LOAD_ESP
  529. LOAD_ECX
  530. CALL_MMX ASM_PFX(LoadMicrocodeDefault)
  531. SAVE_UCODE_STATUS ; Save microcode return status in slot 1 in xmm5.
  532. ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.
  533. ; Call Sec CAR Init
  534. LOAD_ESP
  535. LOAD_ECX
  536. CALL_MMX ASM_PFX(SecCarInit)
  537. cmp eax, 0
  538. jnz TempRamInitExit
  539. LOAD_ESP
  540. LOAD_ECX
  541. mov edi, ecx ; Save UPD param to EDI for later code use
  542. CALL_MMX ASM_PFX(EstablishStackFsp)
  543. cmp eax, 0
  544. jnz TempRamInitExit
  545. LOAD_UCODE_STATUS ; Restore microcode status if no CAR init error from slot 1 in xmm5.
  546. TempRamInitExit:
  547. mov bl, al ; save al data in bl
  548. mov al, 07Fh ; API exit postcode 7f
  549. out 080h, al
  550. mov al, bl ; restore al data from bl
  551. ;
  552. ; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6
  553. ;
  554. LOAD_REGS
  555. ret
  556. ;----------------------------------------------------------------------------
  557. ; Module Entrypoint API
  558. ;----------------------------------------------------------------------------
  559. global ASM_PFX(_ModuleEntryPoint)
  560. ASM_PFX(_ModuleEntryPoint):
  561. jmp $