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@@ -108,14 +108,16 @@ typedef enum {
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#define ARM_CORE_MASK ARM_CORE_AFF0
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#define ARM_CLUSTER_MASK ARM_CORE_AFF1
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-#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
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-#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
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-#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
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-#define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0)
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-#define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8)
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-#define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16)
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-#define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32)
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+#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
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+#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
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+#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
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+#define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0)
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+#define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8)
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+#define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16)
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+#define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32)
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+#define GET_MPIDR_AFFINITY_BITS(MpId) ((MpId) & 0xFF00FFFFFF)
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#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
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+#define MPIDR_MT_BIT BIT24
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/** Reads the CCSIDR register for the specified cache.
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