platform.c 15 KB

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  1. // Platform-dependent functions
  2. #include "platform.h"
  3. #include "c_stdio.h"
  4. #include "c_string.h"
  5. #include "c_stdlib.h"
  6. #include "gpio.h"
  7. #include "user_interface.h"
  8. #include "driver/uart.h"
  9. // Platform specific includes
  10. static void pwms_init();
  11. int platform_init()
  12. {
  13. // Setup PWMs
  14. pwms_init();
  15. cmn_platform_init();
  16. // All done
  17. return PLATFORM_OK;
  18. }
  19. // ****************************************************************************
  20. // KEY_LED functions
  21. uint8_t platform_key_led( uint8_t level){
  22. uint8_t temp;
  23. gpio16_output_set(1); // set to high first, for reading key low level
  24. gpio16_input_conf();
  25. temp = gpio16_input_get();
  26. gpio16_output_conf();
  27. gpio16_output_set(level);
  28. return temp;
  29. }
  30. // ****************************************************************************
  31. // GPIO functions
  32. #ifdef GPIO_INTERRUPT_ENABLE
  33. extern void lua_gpio_unref(unsigned pin);
  34. #endif
  35. int platform_gpio_mode( unsigned pin, unsigned mode, unsigned pull )
  36. {
  37. // NODE_DBG("Function platform_gpio_mode() is called. pin_mux:%d, func:%d\n",pin_mux[pin],pin_func[pin]);
  38. if (pin >= NUM_GPIO)
  39. return -1;
  40. if(pin == 0){
  41. if(mode==PLATFORM_GPIO_INPUT)
  42. gpio16_input_conf();
  43. else
  44. gpio16_output_conf();
  45. return 1;
  46. }
  47. platform_pwm_close(pin); // closed from pwm module, if it is used in pwm
  48. switch(pull){
  49. case PLATFORM_GPIO_PULLUP:
  50. PIN_PULLUP_EN(pin_mux[pin]);
  51. break;
  52. case PLATFORM_GPIO_FLOAT:
  53. PIN_PULLUP_DIS(pin_mux[pin]);
  54. break;
  55. default:
  56. PIN_PULLUP_DIS(pin_mux[pin]);
  57. break;
  58. }
  59. switch(mode){
  60. case PLATFORM_GPIO_INPUT:
  61. #ifdef GPIO_INTERRUPT_ENABLE
  62. lua_gpio_unref(pin); // unref the lua ref call back.
  63. #endif
  64. GPIO_DIS_OUTPUT(pin_num[pin]);
  65. case PLATFORM_GPIO_OUTPUT:
  66. ETS_GPIO_INTR_DISABLE();
  67. #ifdef GPIO_INTERRUPT_ENABLE
  68. pin_int_type[pin] = GPIO_PIN_INTR_DISABLE;
  69. #endif
  70. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  71. //disable interrupt
  72. gpio_pin_intr_state_set(GPIO_ID_PIN(pin_num[pin]), GPIO_PIN_INTR_DISABLE);
  73. //clear interrupt status
  74. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pin_num[pin]));
  75. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])), GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) & (~ GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE))); //disable open drain;
  76. ETS_GPIO_INTR_ENABLE();
  77. break;
  78. #ifdef GPIO_INTERRUPT_ENABLE
  79. case PLATFORM_GPIO_INT:
  80. ETS_GPIO_INTR_DISABLE();
  81. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  82. GPIO_DIS_OUTPUT(pin_num[pin]);
  83. gpio_register_set(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])), GPIO_PIN_INT_TYPE_SET(GPIO_PIN_INTR_DISABLE)
  84. | GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_DISABLE)
  85. | GPIO_PIN_SOURCE_SET(GPIO_AS_PIN_SOURCE));
  86. ETS_GPIO_INTR_ENABLE();
  87. break;
  88. #endif
  89. default:
  90. break;
  91. }
  92. return 1;
  93. }
  94. int platform_gpio_write( unsigned pin, unsigned level )
  95. {
  96. // NODE_DBG("Function platform_gpio_write() is called. pin:%d, level:%d\n",GPIO_ID_PIN(pin_num[pin]),level);
  97. if (pin >= NUM_GPIO)
  98. return -1;
  99. if(pin == 0){
  100. gpio16_output_conf();
  101. gpio16_output_set(level);
  102. return 1;
  103. }
  104. GPIO_OUTPUT_SET(GPIO_ID_PIN(pin_num[pin]), level);
  105. }
  106. int platform_gpio_read( unsigned pin )
  107. {
  108. // NODE_DBG("Function platform_gpio_read() is called. pin:%d\n",GPIO_ID_PIN(pin_num[pin]));
  109. if (pin >= NUM_GPIO)
  110. return -1;
  111. if(pin == 0){
  112. // gpio16_input_conf();
  113. return 0x1 & gpio16_input_get();
  114. }
  115. // GPIO_DIS_OUTPUT(pin_num[pin]);
  116. return 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(pin_num[pin]));
  117. }
  118. #ifdef GPIO_INTERRUPT_ENABLE
  119. static void platform_gpio_intr_dispatcher( void *arg) {
  120. platform_gpio_intr_handler_fn_t cb = arg;
  121. uint8 i, level;
  122. uint32 gpio_status = GPIO_REG_READ(GPIO_STATUS_ADDRESS);
  123. for (i = 0; i < GPIO_PIN_NUM; i++) {
  124. if (pin_int_type[i] && (gpio_status & BIT(pin_num[i])) ) {
  125. //disable interrupt
  126. gpio_pin_intr_state_set(GPIO_ID_PIN(pin_num[i]), GPIO_PIN_INTR_DISABLE);
  127. //clear interrupt status
  128. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, gpio_status & BIT(pin_num[i]));
  129. level = 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(pin_num[i]));
  130. if(cb){
  131. cb(i, level);
  132. }
  133. gpio_pin_intr_state_set(GPIO_ID_PIN(pin_num[i]), pin_int_type[i]);
  134. }
  135. }
  136. }
  137. void platform_gpio_init( platform_gpio_intr_handler_fn_t cb )
  138. {
  139. ETS_GPIO_INTR_ATTACH(platform_gpio_intr_dispatcher, cb);
  140. }
  141. int platform_gpio_intr_init( unsigned pin, GPIO_INT_TYPE type )
  142. {
  143. if (pin >= NUM_GPIO)
  144. return -1;
  145. ETS_GPIO_INTR_DISABLE();
  146. //clear interrupt status
  147. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pin_num[pin]));
  148. pin_int_type[pin] = type;
  149. //enable interrupt
  150. gpio_pin_intr_state_set(GPIO_ID_PIN(pin_num[pin]), type);
  151. ETS_GPIO_INTR_ENABLE();
  152. }
  153. #endif
  154. // ****************************************************************************
  155. // UART
  156. // TODO: Support timeouts.
  157. // UartDev is defined and initialized in rom code.
  158. extern UartDevice UartDev;
  159. uint32_t platform_uart_setup( unsigned id, uint32_t baud, int databits, int parity, int stopbits )
  160. {
  161. switch( baud )
  162. {
  163. case BIT_RATE_300:
  164. case BIT_RATE_600:
  165. case BIT_RATE_1200:
  166. case BIT_RATE_2400:
  167. case BIT_RATE_4800:
  168. case BIT_RATE_9600:
  169. case BIT_RATE_19200:
  170. case BIT_RATE_38400:
  171. case BIT_RATE_57600:
  172. case BIT_RATE_74880:
  173. case BIT_RATE_115200:
  174. case BIT_RATE_230400:
  175. case BIT_RATE_460800:
  176. case BIT_RATE_921600:
  177. case BIT_RATE_1843200:
  178. case BIT_RATE_3686400:
  179. UartDev.baut_rate = baud;
  180. break;
  181. default:
  182. UartDev.baut_rate = BIT_RATE_9600;
  183. break;
  184. }
  185. switch( databits )
  186. {
  187. case 5:
  188. UartDev.data_bits = FIVE_BITS;
  189. break;
  190. case 6:
  191. UartDev.data_bits = SIX_BITS;
  192. break;
  193. case 7:
  194. UartDev.data_bits = SEVEN_BITS;
  195. break;
  196. case 8:
  197. UartDev.data_bits = EIGHT_BITS;
  198. break;
  199. default:
  200. UartDev.data_bits = EIGHT_BITS;
  201. break;
  202. }
  203. switch (stopbits)
  204. {
  205. case PLATFORM_UART_STOPBITS_1_5:
  206. UartDev.stop_bits = ONE_HALF_STOP_BIT;
  207. break;
  208. case PLATFORM_UART_STOPBITS_2:
  209. UartDev.stop_bits = TWO_STOP_BIT;
  210. break;
  211. default:
  212. UartDev.stop_bits = ONE_STOP_BIT;
  213. break;
  214. }
  215. switch (parity)
  216. {
  217. case PLATFORM_UART_PARITY_EVEN:
  218. UartDev.parity = EVEN_BITS;
  219. UartDev.exist_parity = STICK_PARITY_EN;
  220. break;
  221. case PLATFORM_UART_PARITY_ODD:
  222. UartDev.parity = ODD_BITS;
  223. UartDev.exist_parity = STICK_PARITY_EN;
  224. break;
  225. default:
  226. UartDev.parity = NONE_BITS;
  227. UartDev.exist_parity = STICK_PARITY_DIS;
  228. break;
  229. }
  230. uart_setup(id);
  231. return baud;
  232. }
  233. // if set=1, then alternate serial output pins are used. (15=rx, 13=tx)
  234. void platform_uart_alt( int set )
  235. {
  236. uart0_alt( set );
  237. return;
  238. }
  239. // Send: version with and without mux
  240. void platform_uart_send( unsigned id, u8 data )
  241. {
  242. uart_tx_one_char(id, data);
  243. }
  244. // ****************************************************************************
  245. // PWMs
  246. static uint16_t pwms_duty[NUM_PWM] = {0};
  247. static void pwms_init()
  248. {
  249. int i;
  250. for(i=0;i<NUM_PWM;i++){
  251. pwms_duty[i] = DUTY(0);
  252. }
  253. pwm_init(500, NULL);
  254. // NODE_DBG("Function pwms_init() is called.\n");
  255. }
  256. // Return the PWM clock
  257. // NOTE: Can't find a function to query for the period set for the timer,
  258. // therefore using the struct.
  259. // This may require adjustment if driver libraries are updated.
  260. uint32_t platform_pwm_get_clock( unsigned pin )
  261. {
  262. // NODE_DBG("Function platform_pwm_get_clock() is called.\n");
  263. if( pin >= NUM_PWM)
  264. return 0;
  265. if(!pwm_exist(pin))
  266. return 0;
  267. return (uint32_t)pwm_get_freq(pin);
  268. }
  269. // Set the PWM clock
  270. uint32_t platform_pwm_set_clock( unsigned pin, uint32_t clock )
  271. {
  272. // NODE_DBG("Function platform_pwm_set_clock() is called.\n");
  273. if( pin >= NUM_PWM)
  274. return 0;
  275. if(!pwm_exist(pin))
  276. return 0;
  277. pwm_set_freq((uint16_t)clock, pin);
  278. pwm_start();
  279. return (uint32_t)pwm_get_freq( pin );
  280. }
  281. uint32_t platform_pwm_get_duty( unsigned pin )
  282. {
  283. // NODE_DBG("Function platform_pwm_get_duty() is called.\n");
  284. if( pin < NUM_PWM){
  285. if(!pwm_exist(pin))
  286. return 0;
  287. // return NORMAL_DUTY(pwm_get_duty(pin));
  288. return pwms_duty[pin];
  289. }
  290. return 0;
  291. }
  292. // Set the PWM duty
  293. uint32_t platform_pwm_set_duty( unsigned pin, uint32_t duty )
  294. {
  295. // NODE_DBG("Function platform_pwm_set_duty() is called.\n");
  296. if ( pin < NUM_PWM)
  297. {
  298. if(!pwm_exist(pin))
  299. return 0;
  300. pwm_set_duty(DUTY(duty), pin);
  301. } else {
  302. return 0;
  303. }
  304. pwm_start();
  305. pwms_duty[pin] = NORMAL_DUTY(pwm_get_duty(pin));
  306. return pwms_duty[pin];
  307. }
  308. uint32_t platform_pwm_setup( unsigned pin, uint32_t frequency, unsigned duty )
  309. {
  310. uint32_t clock;
  311. if ( pin < NUM_PWM)
  312. {
  313. platform_gpio_mode(pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT); // disable gpio interrupt first
  314. if(!pwm_add(pin))
  315. return 0;
  316. // pwm_set_duty(DUTY(duty), pin);
  317. pwm_set_duty(0, pin);
  318. pwms_duty[pin] = duty;
  319. pwm_set_freq((uint16_t)frequency, pin);
  320. } else {
  321. return 0;
  322. }
  323. clock = platform_pwm_get_clock( pin );
  324. pwm_start();
  325. return clock;
  326. }
  327. void platform_pwm_close( unsigned pin )
  328. {
  329. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  330. if ( pin < NUM_PWM)
  331. {
  332. pwm_delete(pin);
  333. pwm_start();
  334. }
  335. }
  336. void platform_pwm_start( unsigned pin )
  337. {
  338. // NODE_DBG("Function platform_pwm_start() is called.\n");
  339. if ( pin < NUM_PWM)
  340. {
  341. if(!pwm_exist(pin))
  342. return;
  343. pwm_set_duty(DUTY(pwms_duty[pin]), pin);
  344. pwm_start();
  345. }
  346. }
  347. void platform_pwm_stop( unsigned pin )
  348. {
  349. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  350. if ( pin < NUM_PWM)
  351. {
  352. if(!pwm_exist(pin))
  353. return;
  354. pwm_set_duty(0, pin);
  355. pwm_start();
  356. }
  357. }
  358. // *****************************************************************************
  359. // I2C platform interface
  360. uint32_t platform_i2c_setup( unsigned id, uint8_t sda, uint8_t scl, uint32_t speed ){
  361. if (sda >= NUM_GPIO || scl >= NUM_GPIO)
  362. return 0;
  363. // platform_pwm_close(sda);
  364. // platform_pwm_close(scl);
  365. // disable gpio interrupt first
  366. platform_gpio_mode(sda, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // inside this func call platform_pwm_close
  367. platform_gpio_mode(scl, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // disable gpio interrupt first
  368. i2c_master_gpio_init(sda, scl);
  369. return PLATFORM_I2C_SPEED_SLOW;
  370. }
  371. void platform_i2c_send_start( unsigned id ){
  372. i2c_master_start();
  373. }
  374. void platform_i2c_send_stop( unsigned id ){
  375. i2c_master_stop();
  376. }
  377. int platform_i2c_send_address( unsigned id, uint16_t address, int direction ){
  378. // Convert enum codes to R/w bit value.
  379. // If TX == 0 and RX == 1, this test will be removed by the compiler
  380. if ( ! ( PLATFORM_I2C_DIRECTION_TRANSMITTER == 0 &&
  381. PLATFORM_I2C_DIRECTION_RECEIVER == 1 ) ) {
  382. direction = ( direction == PLATFORM_I2C_DIRECTION_TRANSMITTER ) ? 0 : 1;
  383. }
  384. i2c_master_writeByte( (uint8_t) ((address << 1) | direction ));
  385. // Low-level returns nack (0=acked); we return ack (1=acked).
  386. return ! i2c_master_getAck();
  387. }
  388. int platform_i2c_send_byte( unsigned id, uint8_t data ){
  389. i2c_master_writeByte(data);
  390. // Low-level returns nack (0=acked); we return ack (1=acked).
  391. return ! i2c_master_getAck();
  392. }
  393. int platform_i2c_recv_byte( unsigned id, int ack ){
  394. uint8_t r = i2c_master_readByte();
  395. i2c_master_setAck( !ack );
  396. return r;
  397. }
  398. // *****************************************************************************
  399. // SPI platform interface
  400. uint32_t platform_spi_setup( uint8_t id, int mode, unsigned cpol, unsigned cpha, uint32_t clock_div)
  401. {
  402. spi_master_init( id, cpol, cpha, clock_div );
  403. return 1;
  404. }
  405. int platform_spi_send( uint8_t id, uint8_t bitlen, spi_data_type data )
  406. {
  407. if (bitlen > 32)
  408. return PLATFORM_ERR;
  409. spi_mast_transaction( id, 0, 0, bitlen, data, 0, 0, 0 );
  410. return PLATFORM_OK;
  411. }
  412. spi_data_type platform_spi_send_recv( uint8_t id, uint8_t bitlen, spi_data_type data )
  413. {
  414. if (bitlen > 32)
  415. return 0;
  416. spi_mast_set_mosi( id, 0, bitlen, data );
  417. spi_mast_transaction( id, 0, 0, 0, 0, bitlen, 0, -1 );
  418. return spi_mast_get_miso( id, 0, bitlen );
  419. }
  420. int platform_spi_set_mosi( uint8_t id, uint8_t offset, uint8_t bitlen, spi_data_type data )
  421. {
  422. if (offset + bitlen > 512)
  423. return PLATFORM_ERR;
  424. spi_mast_set_mosi( id, offset, bitlen, data );
  425. return PLATFORM_OK;
  426. }
  427. spi_data_type platform_spi_get_miso( uint8_t id, uint8_t offset, uint8_t bitlen )
  428. {
  429. if (offset + bitlen > 512)
  430. return 0;
  431. return spi_mast_get_miso( id, offset, bitlen );
  432. }
  433. int platform_spi_transaction( uint8_t id, uint8_t cmd_bitlen, spi_data_type cmd_data,
  434. uint8_t addr_bitlen, spi_data_type addr_data,
  435. uint16_t mosi_bitlen, uint8_t dummy_bitlen, int16_t miso_bitlen )
  436. {
  437. if ((cmd_bitlen > 16) ||
  438. (addr_bitlen > 32) ||
  439. (mosi_bitlen > 512) ||
  440. (dummy_bitlen > 256) ||
  441. (miso_bitlen > 512))
  442. return PLATFORM_ERR;
  443. spi_mast_transaction( id, cmd_bitlen, cmd_data, addr_bitlen, addr_data, mosi_bitlen, dummy_bitlen, miso_bitlen );
  444. return PLATFORM_OK;
  445. }
  446. // ****************************************************************************
  447. // Flash access functions
  448. /*
  449. * Assumptions:
  450. * > toaddr is INTERNAL_FLASH_WRITE_UNIT_SIZE aligned
  451. * > size is a multiple of INTERNAL_FLASH_WRITE_UNIT_SIZE
  452. */
  453. uint32_t platform_s_flash_write( const void *from, uint32_t toaddr, uint32_t size )
  454. {
  455. SpiFlashOpResult r;
  456. const uint32_t blkmask = INTERNAL_FLASH_WRITE_UNIT_SIZE - 1;
  457. uint32_t *apbuf = NULL;
  458. uint32_t fromaddr = (uint32_t)from;
  459. if( (fromaddr & blkmask ) || (fromaddr >= INTERNAL_FLASH_MAPPED_ADDRESS)) {
  460. apbuf = (uint32_t *)c_malloc(size);
  461. if(!apbuf)
  462. return 0;
  463. c_memcpy(apbuf, from, size);
  464. }
  465. system_soft_wdt_feed ();
  466. r = flash_write(toaddr, apbuf?(uint32 *)apbuf:(uint32 *)from, size);
  467. if(apbuf)
  468. c_free(apbuf);
  469. if(SPI_FLASH_RESULT_OK == r)
  470. return size;
  471. else{
  472. NODE_ERR( "ERROR in flash_write: r=%d at %08X\n", ( int )r, ( unsigned )toaddr);
  473. return 0;
  474. }
  475. }
  476. /*
  477. * Assumptions:
  478. * > fromaddr is INTERNAL_FLASH_READ_UNIT_SIZE aligned
  479. * > size is a multiple of INTERNAL_FLASH_READ_UNIT_SIZE
  480. */
  481. uint32_t platform_s_flash_read( void *to, uint32_t fromaddr, uint32_t size )
  482. {
  483. if (size==0)
  484. return 0;
  485. SpiFlashOpResult r;
  486. system_soft_wdt_feed ();
  487. const uint32_t blkmask = (INTERNAL_FLASH_READ_UNIT_SIZE - 1);
  488. if( ((uint32_t)to) & blkmask )
  489. {
  490. uint32_t size2=size-INTERNAL_FLASH_READ_UNIT_SIZE;
  491. uint32* to2=(uint32*)((((uint32_t)to)&(~blkmask))+INTERNAL_FLASH_READ_UNIT_SIZE);
  492. r = flash_read(fromaddr, to2, size2);
  493. if(SPI_FLASH_RESULT_OK == r)
  494. {
  495. os_memmove(to,to2,size2);
  496. char back[ INTERNAL_FLASH_READ_UNIT_SIZE ] __attribute__ ((aligned(INTERNAL_FLASH_READ_UNIT_SIZE)));
  497. r=flash_read(fromaddr+size2,(uint32*)back,INTERNAL_FLASH_READ_UNIT_SIZE);
  498. os_memcpy((uint8_t*)to+size2,back,INTERNAL_FLASH_READ_UNIT_SIZE);
  499. }
  500. }
  501. else
  502. r = flash_read(fromaddr, (uint32 *)to, size);
  503. if(SPI_FLASH_RESULT_OK == r)
  504. return size;
  505. else{
  506. NODE_ERR( "ERROR in flash_read: r=%d at %08X\n", ( int )r, ( unsigned )fromaddr);
  507. return 0;
  508. }
  509. }
  510. int platform_flash_erase_sector( uint32_t sector_id )
  511. {
  512. system_soft_wdt_feed ();
  513. return flash_erase( sector_id ) == SPI_FLASH_RESULT_OK ? PLATFORM_OK : PLATFORM_ERR;
  514. }
  515. uint32_t platform_flash_mapped2phys (uint32_t mapped_addr)
  516. {
  517. uint32_t cache_ctrl = READ_PERI_REG(CACHE_FLASH_CTRL_REG);
  518. if (!(cache_ctrl & CACHE_FLASH_ACTIVE))
  519. return -1;
  520. bool b0 = (cache_ctrl & CACHE_FLASH_MAPPED0) ? 1 : 0;
  521. bool b1 = (cache_ctrl & CACHE_FLASH_MAPPED1) ? 1 : 0;
  522. uint32_t meg = (b1 << 1) | b0;
  523. return mapped_addr - INTERNAL_FLASH_MAPPED_ADDRESS + meg * 0x100000;
  524. }