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+/*
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+ * Copyright 2015 Dius Computing Pty Ltd. All rights reserved.
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions
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+ * are met:
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+ *
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+ * - Redistributions of source code must retain the above copyright
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+ * notice, this list of conditions and the following disclaimer.
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+ * - Redistributions in binary form must reproduce the above copyright
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+ * notice, this list of conditions and the following disclaimer in the
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+ * documentation and/or other materials provided with the
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+ * distribution.
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+ * - Neither the name of the copyright holders nor the names of
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+ * its contributors may be used to endorse or promote products derived
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+ * from this software without specific prior written permission.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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+ * OF THE POSSIBILITY OF SUCH DAMAGE.
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+ *
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+ * @author Bernd Meyer <bmeyer@dius.com.au>
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+ * @author Johny Mattsson <jmattsson@dius.com.au>
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+ */
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+
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+#ifndef _RTCTIME_INTERNAL_H_
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+#define _RTCTIME_INTERNAL_H_
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+
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+/*
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+ * The ESP8266 has four distinct power states:
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+ *
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+ * 1) Active --- CPU and modem are powered and running
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+ * 2) Modem Sleep --- CPU is active, but the RF section is powered down
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+ * 3) Light Sleep --- CPU is halted, RF section is powered down. CPU gets reactivated by interrupt
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+ * 4) Deep Sleep --- CPU and RF section are powered down, restart requires a full reset
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+ *
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+ * There are also three (relevant) sources of time information
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+ *
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+ * A) CPU Cycle Counter --- this is incremented at the CPU frequency in modes (1) and (2), but is
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+ * halted in state (3), and gets reset in state (4). Highly precise 32 bit counter
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+ * which overflows roughly every minute. Starts counting as soon as the CPU becomes
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+ * active after a reset. Can cause an interrupt when it hits a particular value;
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+ * This interrupt (and the register that determines the comparison value) are not
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+ * used by the system software, and are available for user code to use.
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+ *
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+ * B) Free Running Counter 2 --- This is a peripheral which gets configured to run at 1/256th of the
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+ * CPU frequency. It is also active in states (1) and (2), and is halted in state (3).
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+ * However, the ESP system code will adjust its value across periods of Light Sleep
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+ * that it initiates, so *in effect*, this counter kind-of remains active in (3).
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+ * While in states (1) and (2), it is as precise as the CPU Cycle. While in state (3),
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+ * however, it is only as precise as the system's knowledge of how long the sleep
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+ * period was. This knowledge is limited (it is based on (C), see below).
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+ * The Free Running Counter 2 is a 32 bit counter which overflows roughly every
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+ * 4 hours, and typically has a resolution of 3.2us. It starts counting as soon as
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+ * it gets configured, which is considerably *after* the time of reset, and in fact
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+ * is not done by the ESP boot loader, but rather by the loaded-from-SPI-flash system
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+ * code. This means it is not yet running when the boot loader calls the configured
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+ * entry point, and the time between reset and the counter starting to run depends on
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+ * the size of code/data to be copied into RAM from the flash.
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+ * The FRC2 is also used by the system software for its internal time keeping, i.e. for
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+ * dealing with any registered ETS_Timers (and derived-from-them timer functionality).
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+ *
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+ * C) "Real Time Clock" --- This peripheral runs from an internal low power RC oscillator, at a frequency
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+ * somewhere in the 120-200kHz range. It keeps running in all power states, and is in
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+ * fact the time source responsible for generating an interrupt (state (3)) or reset
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+ * (state (4)) to end Light and Deep Sleep periods. However, it *does* get reset to
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+ * zero after a reset, even one it caused itself.
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+ * The major issue with the RTC is that it is not using a crystal (support for an
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+ * external 32.768kHz crystal was planned at one point, but was removed from the
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+ * final ESP8266 design), and thus the frequency of the oscillator is dependent on
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+ * a number of parameters, including the chip temperature. The ESP's system software
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+ * contains code to "calibrate" exactly how long one cycle of the oscillator is, and
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+ * uses that calibration to work out how many cycles to sleep for modes (3) and (4).
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+ * However, once the chip has entered a low power state, it quickly cools down, which
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+ * results in the oscillator running faster than during calibration, leading to early
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+ * wakeups. This effect is small (even in relative terms) for short sleep periods (because
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+ * the temperature does not change much over a few hundred milliseconds), but can get
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+ * quite large for extended sleeps.
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+ *
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+ * For added fun, a typical ESP8266 module starts up running the CPU (and thus the cycle counter) at 52MHz,
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+ * but usually this will be switched to 80MHz on application startup, and can later be switched to 160MHz
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+ * under user control. Meanwhile, the FRC2 is usually kept running at 80MHz/256, regardless of the CPU
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+ * clock.
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+ *
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+ *
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+ *
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+ * The code in this file implements a best-effort time keeping solution for the ESP. It keeps track of time
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+ * by switching between various time sources. All state is kept in RAM associated with the RTC, which is
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+ * maintained across Deep Sleep periods.
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+ *
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+ * Internally, time is managed in units of cycles of a (hypothetical) 2080MHz clock, e.g. in units
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+ * of 0.4807692307ns. The reason for this choice is that this covers both the FRC2 and the cycle
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+ * counter periods, while running at 52MHz, 80MHz or 160MHz.
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+ *
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+ * At any given time, the time status indicates whether the FRC2 or the Cycle Counter is the current time
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+ * source, how many unit cycles each LSB of the chosen time source "is worth", and what the unix time in
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+ * unit cycles was when the time source was at 0.
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+ * Given that either time source overflows its 32 bit counter in a relatively short time, the code also
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+ * maintains a "last read 32 bit value" for the selected time source, and on each subsequent read will
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+ * check for overflow and, if necessary, adjust the unix-time-at-time-source-being-zero appropriately.
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+ * In order to avoid missing overflows, a timer gets installed which requests time every 40 seconds.
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+ *
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+ * To avoid race conditions, *none* of the code here must be called from an interrupt context unless
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+ * the user can absolutely guarantee that there will never be a clock source rollover (which can be the
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+ * case for sensor applications that only stay awake for a few seconds). And even then, do so at your
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+ * own risk.
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+ *
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+ *
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+ * Deep sleep is handled by moving the time offset forward *before* the sleep to the scheduled wakeup
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+ * time. Due to the nature of the RTC, the actual wakeup time may be a little bit different, but
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+ * it's the best that can be done. The code attempts to come up with a better calibration value if
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+ * authoritative time is available both before and after a sleep; This works reasonably well, but of
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+ * course is still merely a guess, which may well be somewhat wrong.
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+ *
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+ */
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+#include <osapi.h>
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+#include <ets_sys.h>
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+#include "rom.h"
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+#include "rtcaccess.h"
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+
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+// Layout of the RTC storage space:
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+//
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+// 0: Magic, and time source. Meaningful values are
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+// * RTC_TIME_MAGIC_SLEEP: Indicates that the device went to sleep under RTCTIME control.
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+// This is the magic expected on deep sleep wakeup; Any other status means we lost track
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+// of time, and whatever time offset is stored in state is invalid and must be cleared.
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+// * RTC_TIME_MAGIC_CCOUNT: Time offset is relative to the Cycle Counter.
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+// * RTC_TIME_MAGIC_FRC2: Time offset is relative to the Free Running Counter.
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+// Any values other than these indicate that RTCTIME is not in use and no state is available, nor should
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+// RTCTIME make any changes to any of the RTC memory space.
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+//
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+// 1/2: UNIX time in Unit Cycles when time source had value 0 (64 bit, lower 32 bit in 1, upper in 2).
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+// If 0, then time is unknown.
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+// 3: Last used value of time source (32 bit unsigned). If current time source is less, then a rollover happened
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+// 4: Length of a time source cycle in Unit Cycles.
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+// 5: cached result of sleep clock calibration. Has the format of system_rtc_clock_cali_proc(),
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+// or 0 if not available (see 6/7 below)
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+// 6: Number of microseconds we tried to sleep, or 0 if we didn't sleep since last calibration, ffffffff if invalid
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+// 7: Number of RTC cycles we decided to sleep, or 0 if we didn't sleep since last calibration, ffffffff if invalid
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+
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+// 8: Number of microseconds which we add to (1/2) to avoid time going backwards
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+// 9: microsecond value returned in the last gettimeofday() to "user space".
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+//
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+// Entries 6-9 are needed because the RTC cycles/second appears quite temperature dependent,
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+// and thus is heavily influenced by what else the chip is doing. As such, any calibration against
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+// the crystal-provided clock (which necessarily would have to happen while the chip is active and
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+// burning a few milliwatts) will be significantly different from the actual frequency during deep
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+// sleep.
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+// Thus, in order to calibrate for deep sleep conditions, we keep track of total sleep microseconds
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+// and total sleep clock cycles between settimeofday() calls (which presumably are NTP driven), and
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+// adjust the calibration accordingly on each settimeofday(). This will also track frequency changes
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+// due to ambient temperature changes.
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+// 8/9 get used when a settimeofday() would result in turning back time. As that can cause all sorts
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+// of ugly issues, we *do* adjust (1/2), but compensate by making the same adjustment to (8). Then each
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+// time gettimeofday() is called, we inspect (9) and determine how much time has passed since the last
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+// call (yes, this gets it wrong if more than a second has passed, but not in a way that causes issues)
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+// and try to take up to 6% of that time away from (8) until (8) reaches 0. Also, whenever we go to
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+// deep sleep, we add (8) to the sleep time, thus catching up all in one go.
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+// Note that for calculating the next sample-aligned wakeup, we need to use the post-adjustment
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+// timeofday(), but for calculating actual sleep time, we use the pre-adjustment one, thus bringing
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+// things back into line.
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+//
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+
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+#define RTC_TIME_BASE 0 // Where the RTC timekeeping block starts in RTC user memory slots
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+#define RTC_TIME_MAGIC_CCOUNT 0x44695573
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+#define RTC_TIME_MAGIC_FRC2 (RTC_TIME_MAGIC_CCOUNT+1)
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+#define RTC_TIME_MAGIC_SLEEP (RTC_TIME_MAGIC_CCOUNT+2)
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+
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+#define UNITCYCLE_MHZ 2080
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+#define CPU_OVERCLOCK_MHZ 160
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+#define CPU_DEFAULT_MHZ 80
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+#define CPU_BOOTUP_MHZ 52
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+
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+// RTCTIME storage
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+#define RTC_TIME_MAGIC_POS (RTC_TIME_BASE+0)
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+#define RTC_CYCLEOFFSETL_POS (RTC_TIME_BASE+1)
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+#define RTC_CYCLEOFFSETH_POS (RTC_TIME_BASE+2)
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+#define RTC_LASTSOURCEVAL_POS (RTC_TIME_BASE+3)
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+#define RTC_SOURCECYCLEUNITS_POS (RTC_TIME_BASE+4)
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+#define RTC_CALIBRATION_POS (RTC_TIME_BASE+5)
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+#define RTC_SLEEPTOTALUS_POS (RTC_TIME_BASE+6)
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+#define RTC_SLEEPTOTALCYCLES_POS (RTC_TIME_BASE+7)
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+#define RTC_TODOFFSETUS_POS (RTC_TIME_BASE+8)
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+#define RTC_LASTTODUS_POS (RTC_TIME_BASE+9)
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+
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+
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+struct rtc_timeval
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+{
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+ uint32_t tv_sec;
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+ uint32_t tv_usec;
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+};
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+
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+static inline uint64_t rtc_time_get_now_us_adjusted();
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+
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+static inline uint32_t rtc_time_get_magic(void)
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+{
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+ return rtc_mem_read(RTC_TIME_MAGIC_POS);
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+}
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+
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+static inline bool rtc_time_check_sleep_magic(void)
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+{
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+ uint32_t magic=rtc_time_get_magic();
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+ return (magic==RTC_TIME_MAGIC_SLEEP);
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+}
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+
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+static inline bool rtc_time_check_wake_magic(void)
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+{
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+ uint32_t magic=rtc_time_get_magic();
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+ return (magic==RTC_TIME_MAGIC_FRC2 || magic==RTC_TIME_MAGIC_CCOUNT);
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+}
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+
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+static inline bool rtc_time_check_magic(void)
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+{
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+ uint32_t magic=rtc_time_get_magic();
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+ return (magic==RTC_TIME_MAGIC_FRC2 || magic==RTC_TIME_MAGIC_CCOUNT || magic==RTC_TIME_MAGIC_SLEEP);
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+}
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+
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+static inline void rtc_time_set_magic(uint32_t new_magic)
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+{
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+ rtc_mem_write(RTC_TIME_MAGIC_POS,new_magic);
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+}
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+
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+static inline void rtc_time_set_sleep_magic(void)
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+{
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+ rtc_time_set_magic(RTC_TIME_MAGIC_SLEEP);
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+}
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+
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+static inline void rtc_time_set_ccount_magic(void)
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+{
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+ rtc_time_set_magic(RTC_TIME_MAGIC_CCOUNT);
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+}
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+
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+static inline void rtc_time_set_frc2_magic(void)
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+{
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+ rtc_time_set_magic(RTC_TIME_MAGIC_FRC2);
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+}
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+
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+
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+
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+static inline void rtc_time_unset_magic(void)
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+{
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+ rtc_mem_write(RTC_TIME_MAGIC_POS,0);
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+}
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+
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+static inline uint32_t rtc_time_read_raw(void)
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+{
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+ return rtc_reg_read(RTC_COUNTER_ADDR);
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+}
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+
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+static inline uint32_t rtc_time_read_raw_ccount(void)
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+{
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+ return xthal_get_ccount();
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+}
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+
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+static inline uint32_t rtc_time_read_raw_frc2(void)
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+{
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+ return NOW();
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+}
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+
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+// Get us the number of Unit Cycles that have elapsed since the source was 0.
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+// Note: This may in fact adjust the stored cycles-when-source-was-0 entry, so
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+// we need to make sure we call this before reading that entry
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+static inline uint64_t rtc_time_source_offset(void)
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+{
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+ uint32_t magic=rtc_time_get_magic();
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+ uint32_t raw=0;
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+
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+ switch (magic)
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+ {
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+ case RTC_TIME_MAGIC_CCOUNT: raw=rtc_time_read_raw_ccount(); break;
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+ case RTC_TIME_MAGIC_FRC2: raw=rtc_time_read_raw_frc2(); break;
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+ default: return 0; // We are not in a position to offer time
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+ }
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+ uint32_t multiplier=rtc_mem_read(RTC_SOURCECYCLEUNITS_POS);
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+ uint32_t previous=rtc_mem_read(RTC_LASTSOURCEVAL_POS);
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+ if (raw<previous)
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+ { // We had a rollover.
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+ uint64_t to_add=(1ULL<<32)*multiplier;
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+ uint64_t base=rtc_mem_read64(RTC_CYCLEOFFSETL_POS);
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+ if (base)
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+ rtc_mem_write64(RTC_CYCLEOFFSETL_POS,base+to_add);
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+ }
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+ rtc_mem_write(RTC_LASTSOURCEVAL_POS,raw);
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+ return ((uint64_t)raw)*multiplier;
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+}
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+
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+static inline uint64_t rtc_time_unix_unitcycles(void)
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+{
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+ // Note: The order of these two must be maintained, as the first call might change the outcome of the second
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+ uint64_t offset=rtc_time_source_offset();
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+ uint64_t base=rtc_mem_read64(RTC_CYCLEOFFSETL_POS);
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+
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+ if (!base)
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+ return 0; // No known time
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+
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+ return base+offset;
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+}
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+
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+static inline uint64_t rtc_time_unix_us(void)
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+{
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+ return rtc_time_unix_unitcycles()/UNITCYCLE_MHZ;
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+}
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+
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+static inline void rtc_time_register_time_reached(uint32_t s, uint32_t us)
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+{
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+ rtc_mem_write(RTC_LASTTODUS_POS,us);
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+}
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+
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+static inline uint32_t rtc_time_us_since_time_reached(uint32_t s, uint32_t us)
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+{
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+ uint32_t lastus=rtc_mem_read(RTC_LASTTODUS_POS);
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+ if (us<lastus)
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+ us+=1000000;
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+ return us-lastus;
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+}
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+
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+// A small sanity check so sleep times go completely nuts if someone
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+// has provided wrong timestamps to gettimeofday.
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+static inline bool rtc_time_calibration_is_sane(uint32_t cali)
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+{
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+ return (cali>=(4<<12)) && (cali<=(10<<12));
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+}
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+
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+
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+static inline uint32_t rtc_time_get_calibration(void)
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+{
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+ uint32_t cal=rtc_time_check_magic()?rtc_mem_read(RTC_CALIBRATION_POS):0;
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+ if (!cal)
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+ {
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+ // Make a first guess, most likely to be rather bad, but better then nothing.
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+#ifndef BOOTLOADER_CODE // This will pull in way too much of the system for the bootloader to handle.
|
|
|
+ ets_delay_us(200);
|
|
|
+ cal=system_rtc_clock_cali_proc();
|
|
|
+ rtc_mem_write(RTC_CALIBRATION_POS,cal);
|
|
|
+#else
|
|
|
+ cal=6<<12;
|
|
|
+#endif
|
|
|
+ }
|
|
|
+ return cal;
|
|
|
+}
|
|
|
+
|
|
|
+static inline void rtc_time_invalidate_calibration(void)
|
|
|
+{
|
|
|
+ rtc_mem_write(RTC_CALIBRATION_POS,0);
|
|
|
+}
|
|
|
+
|
|
|
+static inline uint64_t rtc_time_us_to_ticks(uint64_t us)
|
|
|
+{
|
|
|
+ uint32_t cal=rtc_time_get_calibration();
|
|
|
+
|
|
|
+ return (us<<12)/cal;
|
|
|
+}
|
|
|
+
|
|
|
+static inline uint64_t rtc_time_get_now_us_raw(void)
|
|
|
+{
|
|
|
+ if (!rtc_time_check_magic())
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ return rtc_time_unix_us();
|
|
|
+}
|
|
|
+
|
|
|
+static inline uint64_t rtc_time_get_now_us_adjusted(void)
|
|
|
+{
|
|
|
+ uint64_t raw=rtc_time_get_now_us_raw();
|
|
|
+ if (!raw)
|
|
|
+ return 0;
|
|
|
+ return raw+rtc_mem_read(RTC_TODOFFSETUS_POS);
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+static inline void rtc_time_add_sleep_tracking(uint32_t us, uint32_t cycles)
|
|
|
+{
|
|
|
+ if (rtc_time_check_magic())
|
|
|
+ {
|
|
|
+ // us is the one that will grow faster...
|
|
|
+ uint32_t us_before=rtc_mem_read(RTC_SLEEPTOTALUS_POS);
|
|
|
+ uint32_t us_after=us_before+us;
|
|
|
+ uint32_t cycles_after=rtc_mem_read(RTC_SLEEPTOTALCYCLES_POS)+cycles;
|
|
|
+
|
|
|
+ if (us_after<us_before) // Give up if it would cause an overflow
|
|
|
+ {
|
|
|
+ us_after=cycles_after=0xffffffff;
|
|
|
+ }
|
|
|
+ rtc_mem_write(RTC_SLEEPTOTALUS_POS, us_after);
|
|
|
+ rtc_mem_write(RTC_SLEEPTOTALCYCLES_POS,cycles_after);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void rtc_time_enter_deep_sleep_us(uint32_t us)
|
|
|
+{
|
|
|
+ if (rtc_time_check_wake_magic())
|
|
|
+ rtc_time_set_sleep_magic();
|
|
|
+
|
|
|
+ rtc_reg_write(0,0);
|
|
|
+ rtc_reg_write(0,rtc_reg_read(0)&0xffffbfff);
|
|
|
+ rtc_reg_write(0,rtc_reg_read(0)|0x30);
|
|
|
+
|
|
|
+ rtc_reg_write(0x44,4);
|
|
|
+ rtc_reg_write(0x0c,0x00010010);
|
|
|
+
|
|
|
+ rtc_reg_write(0x48,(rtc_reg_read(0x48)&0xffff01ff)|0x0000fc00);
|
|
|
+ rtc_reg_write(0x48,(rtc_reg_read(0x48)&0xfffffe00)|0x00000080);
|
|
|
+
|
|
|
+ rtc_reg_write(RTC_TARGET_ADDR,rtc_time_read_raw()+136);
|
|
|
+ rtc_reg_write(0x18,8);
|
|
|
+ rtc_reg_write(0x08,0x00100010);
|
|
|
+
|
|
|
+ ets_delay_us(20);
|
|
|
+
|
|
|
+ rtc_reg_write(0x9c,17);
|
|
|
+ rtc_reg_write(0xa0,3);
|
|
|
+
|
|
|
+ rtc_reg_write(0x0c,0x640c8);
|
|
|
+ rtc_reg_write(0,rtc_reg_read(0)&0xffffffcf);
|
|
|
+
|
|
|
+ uint32_t cycles=rtc_time_us_to_ticks(us);
|
|
|
+ rtc_time_add_sleep_tracking(us,cycles);
|
|
|
+
|
|
|
+ rtc_reg_write(RTC_TARGET_ADDR,rtc_time_read_raw()+cycles);
|
|
|
+ rtc_reg_write(0x9c,17);
|
|
|
+ rtc_reg_write(0xa0,3);
|
|
|
+
|
|
|
+ // Clear bit 0 of DPORT 0x04. Doesn't seem to be necessary
|
|
|
+ // wm(0x3fff0004,bitrm(0x3fff0004),0xfffffffe));
|
|
|
+ rtc_reg_write(0x40,-1);
|
|
|
+ rtc_reg_write(0x44,32);
|
|
|
+ rtc_reg_write(0x10,0);
|
|
|
+
|
|
|
+ rtc_reg_write(0x18,8);
|
|
|
+ rtc_reg_write(0x08,0x00100000); // go to sleep
|
|
|
+}
|
|
|
+
|
|
|
+static inline void rtc_time_deep_sleep_us(uint32_t us)
|
|
|
+{
|
|
|
+ if (rtc_time_check_magic())
|
|
|
+ {
|
|
|
+ uint32_t to_adjust=rtc_mem_read(RTC_TODOFFSETUS_POS);
|
|
|
+ if (to_adjust)
|
|
|
+ {
|
|
|
+ us+=to_adjust;
|
|
|
+ rtc_mem_write(RTC_TODOFFSETUS_POS,0);
|
|
|
+ }
|
|
|
+ uint64_t now=rtc_time_get_now_us_raw(); // Now the same as _adjusted()
|
|
|
+ if (now)
|
|
|
+ { // Need to maintain the clock first. When we wake up, counter will be 0
|
|
|
+ uint64_t wakeup=now+us;
|
|
|
+ uint64_t wakeup_cycles=wakeup*UNITCYCLE_MHZ;
|
|
|
+ rtc_mem_write64(RTC_CYCLEOFFSETL_POS,wakeup_cycles);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ rtc_time_enter_deep_sleep_us(us);
|
|
|
+}
|
|
|
+
|
|
|
+static inline void rtc_time_deep_sleep_until_aligned(uint32_t align, uint32_t min_sleep_us)
|
|
|
+{
|
|
|
+ uint64_t now=rtc_time_get_now_us_adjusted();
|
|
|
+ uint64_t then=now+min_sleep_us;
|
|
|
+
|
|
|
+ if (align)
|
|
|
+ {
|
|
|
+ then+=align-1;
|
|
|
+ then-=(then%align);
|
|
|
+ }
|
|
|
+ rtc_time_deep_sleep_us(then-now);
|
|
|
+}
|
|
|
+
|
|
|
+static inline void rtc_time_reset(bool clear_cali)
|
|
|
+{
|
|
|
+ rtc_mem_write64(RTC_CYCLEOFFSETL_POS,0);
|
|
|
+ rtc_mem_write(RTC_SLEEPTOTALUS_POS,0);
|
|
|
+ rtc_mem_write(RTC_SLEEPTOTALCYCLES_POS,0);
|
|
|
+ rtc_mem_write(RTC_TODOFFSETUS_POS,0);
|
|
|
+ rtc_mem_write(RTC_LASTTODUS_POS,0);
|
|
|
+ rtc_mem_write(RTC_SOURCECYCLEUNITS_POS,0);
|
|
|
+ rtc_mem_write(RTC_LASTSOURCEVAL_POS,0);
|
|
|
+
|
|
|
+ if (clear_cali)
|
|
|
+ rtc_mem_write(RTC_CALIBRATION_POS,0);
|
|
|
+}
|
|
|
+
|
|
|
+static inline bool rtc_time_have_time(void)
|
|
|
+{
|
|
|
+ return (rtc_time_check_magic() && rtc_mem_read64(RTC_CYCLEOFFSETL_POS)!=0);
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+static inline void rtc_time_select_frc2_source()
|
|
|
+{
|
|
|
+ // FRC2 always runs at 1/256th of the default 80MHz clock, even if the actual clock is different
|
|
|
+ uint32_t new_multiplier=(256*UNITCYCLE_MHZ+CPU_DEFAULT_MHZ/2)/CPU_DEFAULT_MHZ;
|
|
|
+
|
|
|
+ uint64_t now;
|
|
|
+ uint32_t before;
|
|
|
+ uint32_t after;
|
|
|
+
|
|
|
+ // Deal with race condition here...
|
|
|
+ do {
|
|
|
+ before=rtc_time_read_raw_frc2();
|
|
|
+ now=rtc_time_unix_unitcycles();
|
|
|
+ after=rtc_time_read_raw_frc2();
|
|
|
+ } while (before>after);
|
|
|
+
|
|
|
+ if (rtc_time_have_time())
|
|
|
+ {
|
|
|
+ uint64_t offset=(uint64_t)after*new_multiplier;
|
|
|
+ rtc_mem_write64(RTC_CYCLEOFFSETL_POS,now-offset);
|
|
|
+ rtc_mem_write(RTC_LASTSOURCEVAL_POS,after);
|
|
|
+ }
|
|
|
+ rtc_mem_write(RTC_SOURCECYCLEUNITS_POS,new_multiplier);
|
|
|
+ rtc_mem_write(RTC_TIME_MAGIC_POS,RTC_TIME_MAGIC_FRC2);
|
|
|
+}
|
|
|
+
|
|
|
+static inline void rtc_time_select_ccount_source(uint32_t mhz, bool first)
|
|
|
+{
|
|
|
+ uint32_t new_multiplier=(UNITCYCLE_MHZ+mhz/2)/mhz;
|
|
|
+
|
|
|
+ // Check that
|
|
|
+ if (new_multiplier*mhz!=UNITCYCLE_MHZ)
|
|
|
+ ets_printf("Trying to use unsuitable frequency: %dMHz\n",mhz);
|
|
|
+
|
|
|
+ if (first)
|
|
|
+ { // The ccounter has been running at this rate since startup, and the offset is set accordingly
|
|
|
+ rtc_mem_write(RTC_LASTSOURCEVAL_POS,0);
|
|
|
+ rtc_mem_write(RTC_SOURCECYCLEUNITS_POS,new_multiplier);
|
|
|
+ rtc_mem_write(RTC_TIME_MAGIC_POS,RTC_TIME_MAGIC_CCOUNT);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ uint64_t now;
|
|
|
+ uint32_t before;
|
|
|
+ uint32_t after;
|
|
|
+
|
|
|
+ // Deal with race condition here...
|
|
|
+ do {
|
|
|
+ before=rtc_time_read_raw_ccount();
|
|
|
+ now=rtc_time_unix_unitcycles();
|
|
|
+ after=rtc_time_read_raw_ccount();
|
|
|
+ } while (before>after);
|
|
|
+
|
|
|
+ if (rtc_time_have_time())
|
|
|
+ {
|
|
|
+ uint64_t offset=(uint64_t)after*new_multiplier;
|
|
|
+ rtc_mem_write64(RTC_CYCLEOFFSETL_POS,now-offset);
|
|
|
+ rtc_mem_write(RTC_LASTSOURCEVAL_POS,after);
|
|
|
+ }
|
|
|
+ rtc_mem_write(RTC_SOURCECYCLEUNITS_POS,new_multiplier);
|
|
|
+ rtc_mem_write(RTC_TIME_MAGIC_POS,RTC_TIME_MAGIC_CCOUNT);
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+static inline void rtc_time_switch_to_ccount_frequency(uint32_t mhz)
|
|
|
+{
|
|
|
+ if (rtc_time_check_magic())
|
|
|
+ rtc_time_select_ccount_source(mhz,false);
|
|
|
+}
|
|
|
+
|
|
|
+static inline void rtc_time_switch_to_system_clock(void)
|
|
|
+{
|
|
|
+ if (rtc_time_check_magic())
|
|
|
+ rtc_time_select_frc2_source();
|
|
|
+}
|
|
|
+
|
|
|
+static inline void rtc_time_tmrfn(void* arg)
|
|
|
+{
|
|
|
+ rtc_time_source_offset();
|
|
|
+}
|
|
|
+
|
|
|
+static inline void rtc_time_install_timer(void)
|
|
|
+{
|
|
|
+ static ETSTimer tmr;
|
|
|
+
|
|
|
+ os_timer_setfn(&tmr,rtc_time_tmrfn,NULL);
|
|
|
+ os_timer_arm(&tmr,10000,1);
|
|
|
+}
|
|
|
+
|
|
|
+#if 0 // Kept around for reference....
|
|
|
+static inline void rtc_time_ccount_wrap_handler(void* dst_v, uint32_t sp)
|
|
|
+{
|
|
|
+ uint32_t off_h=rtc_mem_read(RTC_CYCLEOFFSETH_POS);
|
|
|
+ if (rtc_time_check_magic() && off_h)
|
|
|
+ {
|
|
|
+ rtc_mem_write(RTC_CYCLEOFFSETH_POS,off_h+1);
|
|
|
+ }
|
|
|
+ xthal_set_ccompare(0,0); // This resets the interrupt condition
|
|
|
+}
|
|
|
+
|
|
|
+static inline void rtc_time_install_wrap_handler(void)
|
|
|
+{
|
|
|
+ xthal_set_ccompare(0,0); // Recognise a ccounter wraparound
|
|
|
+ ets_isr_attach(RTC_TIME_CCOMPARE_INT,rtc_time_ccount_wrap_handler,NULL);
|
|
|
+ ets_isr_unmask(1<<RTC_TIME_CCOMPARE_INT);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+// This switches from MAGIC_SLEEP to MAGIC_CCOUNT, with ccount running at bootup frequency (i.e. 52MHz).
|
|
|
+// To be called as early as possible, potententially as the first thing in an overridden entry point.
|
|
|
+static inline void rtc_time_register_bootup(void)
|
|
|
+{
|
|
|
+ uint32_t reset_reason=rtc_get_reset_reason();
|
|
|
+#ifndef BOOTLOADER_CODE
|
|
|
+ static const bool erase_calibration=true;
|
|
|
+#else
|
|
|
+ // In the boot loader, any leftover calibration is going to be better than anything we can
|
|
|
+ // come up with....
|
|
|
+ static const bool erase_calibration=false;
|
|
|
+#endif
|
|
|
+
|
|
|
+ if (rtc_time_check_sleep_magic())
|
|
|
+ {
|
|
|
+ if (reset_reason!=2) // This was *not* a proper wakeup from a deep sleep. All our time keeping is f*cked!
|
|
|
+ rtc_time_reset(erase_calibration); // Possibly keep the calibration, it should still be good
|
|
|
+ rtc_time_select_ccount_source(CPU_BOOTUP_MHZ,true);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (rtc_time_check_magic())
|
|
|
+ {
|
|
|
+ // We did not go to sleep properly. All our time keeping is f*cked!
|
|
|
+ rtc_time_reset(erase_calibration); // Possibly keep the calibration, it should still be good
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+// Call this from the nodemcu entry point, i.e. just before we switch from 52MHz to 80MHz
|
|
|
+static inline void rtc_time_switch_clocks(void)
|
|
|
+{
|
|
|
+ rtc_time_switch_to_ccount_frequency(CPU_DEFAULT_MHZ);
|
|
|
+}
|
|
|
+
|
|
|
+// Call this exactly once, from user_init, i.e. once the operating system is up and running
|
|
|
+static inline void rtc_time_switch_system(void)
|
|
|
+{
|
|
|
+ rtc_time_install_timer();
|
|
|
+ rtc_time_switch_to_system_clock();
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+static inline void rtc_time_prepare(void)
|
|
|
+{
|
|
|
+ rtc_time_reset(true);
|
|
|
+ rtc_time_select_frc2_source();
|
|
|
+}
|
|
|
+
|
|
|
+static inline void rtc_time_gettimeofday(struct rtc_timeval* tv)
|
|
|
+{
|
|
|
+ uint64_t now=rtc_time_get_now_us_adjusted();
|
|
|
+ uint32_t sec=now/1000000;
|
|
|
+ uint32_t usec=now%1000000;
|
|
|
+ uint32_t to_adjust=rtc_mem_read(RTC_TODOFFSETUS_POS);
|
|
|
+ if (to_adjust)
|
|
|
+ {
|
|
|
+ uint32_t us_passed=rtc_time_us_since_time_reached(sec,usec);
|
|
|
+ uint32_t adjust=us_passed>>4;
|
|
|
+ if (adjust)
|
|
|
+ {
|
|
|
+ if (adjust>to_adjust)
|
|
|
+ adjust=to_adjust;
|
|
|
+ to_adjust-=adjust;
|
|
|
+ now-=adjust;
|
|
|
+ now/1000000;
|
|
|
+ now%1000000;
|
|
|
+ rtc_mem_write(RTC_TODOFFSETUS_POS,to_adjust);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ tv->tv_sec=sec;
|
|
|
+ tv->tv_usec=usec;
|
|
|
+ rtc_time_register_time_reached(sec,usec);
|
|
|
+}
|
|
|
+
|
|
|
+static inline void rtc_time_settimeofday(const struct rtc_timeval* tv)
|
|
|
+{
|
|
|
+ if (!rtc_time_check_magic())
|
|
|
+ return;
|
|
|
+
|
|
|
+
|
|
|
+ uint32_t sleep_us=rtc_mem_read(RTC_SLEEPTOTALUS_POS);
|
|
|
+ uint32_t sleep_cycles=rtc_mem_read(RTC_SLEEPTOTALCYCLES_POS);
|
|
|
+ // At this point, the CPU clock will definitely be at the default rate (nodemcu fully booted)
|
|
|
+ uint64_t now_esp_us=rtc_time_get_now_us_adjusted();
|
|
|
+ uint64_t now_ntp_us=((uint64_t)tv->tv_sec)*1000000+tv->tv_usec;
|
|
|
+ int64_t diff_us=now_esp_us-now_ntp_us;
|
|
|
+
|
|
|
+ // Store the *actual* time.
|
|
|
+ uint64_t target_unitcycles=now_ntp_us*UNITCYCLE_MHZ;
|
|
|
+ uint64_t sourcecycles=rtc_time_source_offset();
|
|
|
+ rtc_mem_write64(RTC_CYCLEOFFSETL_POS,target_unitcycles-sourcecycles);
|
|
|
+
|
|
|
+ // calibrate sleep period based on difference between expected time and actual time
|
|
|
+ if (sleep_us>0 && sleep_us<0xffffffff &&
|
|
|
+ sleep_cycles>0 && sleep_cycles<0xffffffff)
|
|
|
+ {
|
|
|
+ uint64_t actual_sleep_us=sleep_us-diff_us;
|
|
|
+ uint32_t cali=(actual_sleep_us<<12)/sleep_cycles;
|
|
|
+ if (rtc_time_calibration_is_sane(cali))
|
|
|
+ rtc_mem_write(RTC_CALIBRATION_POS,cali);
|
|
|
+ }
|
|
|
+
|
|
|
+ rtc_mem_write(RTC_SLEEPTOTALUS_POS,0);
|
|
|
+ rtc_mem_write(RTC_SLEEPTOTALCYCLES_POS,0);
|
|
|
+
|
|
|
+ // Deal with time adjustment if necessary
|
|
|
+ if (diff_us>0) // Time went backwards. Avoid that....
|
|
|
+ {
|
|
|
+ if (diff_us>0xffffffffULL)
|
|
|
+ diff_us=0xffffffffULL;
|
|
|
+ now_ntp_us+=diff_us;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ diff_us=0;
|
|
|
+ rtc_mem_write(RTC_TODOFFSETUS_POS,diff_us);
|
|
|
+
|
|
|
+ uint32_t now_s=now_ntp_us/1000000;
|
|
|
+ uint32_t now_us=now_ntp_us%1000000;
|
|
|
+ rtc_time_register_time_reached(now_s,now_us);
|
|
|
+}
|
|
|
+
|
|
|
+#endif
|