memory_arm.s 8.1 KB

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  1. /*
  2. * PicoDrive
  3. * (C) notaz, 2006-2009
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. */
  8. @@ .include "port_config.s"
  9. .equ SRR_MAPPED, (1 << 0)
  10. .equ SRR_READONLY, (1 << 1)
  11. .equ SRF_EEPROM, (1 << 1)
  12. .equ POPT_6BTN_PAD, (1 << 5)
  13. .equ POPT_EN_32X, (1 << 20)
  14. .text
  15. .align 4
  16. .global PicoRead8_sram
  17. .global PicoRead8_io
  18. .global PicoRead16_sram
  19. .global PicoRead16_io
  20. .global PicoWrite8_io
  21. .global PicoWrite16_io
  22. PicoRead8_sram: @ u32 a, u32 d
  23. ldr r2, =(SRam)
  24. ldr r3, =(Pico+0x22200)
  25. ldr r1, [r2, #8] @ SRam.end
  26. cmp r0, r1
  27. bgt m_read8_nosram
  28. ldr r1, [r2, #4] @ SRam.start
  29. cmp r0, r1
  30. blt m_read8_nosram
  31. ldrb r1, [r3, #0x11] @ Pico.m.sram_reg
  32. tst r1, #SRR_MAPPED
  33. beq m_read8_nosram
  34. ldr r1, [r2, #0x0c]
  35. tst r1, #SRF_EEPROM
  36. bne m_read8_eeprom
  37. ldr r1, [r2, #4] @ SRam.start
  38. ldr r2, [r2] @ SRam.data
  39. sub r0, r0, r1
  40. add r0, r0, r2
  41. ldrb r0, [r0]
  42. bx lr
  43. m_read8_nosram:
  44. ldr r1, [r3, #4] @ romsize
  45. cmp r0, r1
  46. movgt r0, #0
  47. bxgt lr @ bad location
  48. @ XXX: banking unfriendly
  49. ldr r1, [r3]
  50. eor r0, r0, #1
  51. ldrb r0, [r1, r0]
  52. bx lr
  53. m_read8_eeprom:
  54. stmfd sp!,{r0,lr}
  55. bl EEPROM_read
  56. ldmfd sp!,{r1,lr}
  57. tst r1, #1
  58. moveq r0, r0, lsr #8
  59. bx lr
  60. PicoRead8_io: @ u32 a, u32 d
  61. bic r2, r0, #0x001f @ most commonly we get i/o port read,
  62. cmp r2, #0xa10000 @ so check for it first
  63. bne m_read8_not_io
  64. m_read8_misc_io:
  65. ands r0, r0, #0x1e
  66. beq m_read8_misc_hwreg
  67. cmp r0, #4
  68. movlt r0, #0
  69. moveq r0, #1
  70. ble PadRead
  71. ldr r3, =(Pico+0x22000)
  72. mov r0, r0, lsr #1 @ other IO ports (Pico.ioports[a])
  73. ldrb r0, [r3, r0]
  74. bx lr
  75. m_read8_misc_hwreg:
  76. ldr r3, =(Pico+0x22200)
  77. ldrb r0, [r3, #0x0f] @ Pico.m.hardware
  78. bx lr
  79. m_read8_not_io:
  80. and r2, r0, #0xfc00
  81. cmp r2, #0x1000
  82. bne m_read8_not_brq
  83. ldr r3, =(Pico+0x22200)
  84. mov r1, r0
  85. ldr r0, [r3, #8] @ Pico.m.rotate
  86. add r0, r0, #1
  87. strb r0, [r3, #8]
  88. eor r0, r0, r0, lsl #6
  89. tst r1, #1
  90. bxne lr @ odd addr -> open bus
  91. bic r0, r0, #1 @ bit0 defined in this area
  92. and r2, r1, #0xff00
  93. cmp r2, #0x1100
  94. bxne lr @ not busreq
  95. ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run
  96. ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset
  97. orr r0, r0, r1
  98. orr r0, r0, r2
  99. bx lr
  100. m_read8_not_brq:
  101. ldr r2, =PicoOpt
  102. ldr r2, [r2]
  103. tst r2, #POPT_EN_32X
  104. bne PicoRead8_32x
  105. mov r0, #0
  106. bx lr
  107. @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
  108. PicoRead16_sram: @ u32 a, u32 d
  109. ldr r2, =(SRam)
  110. ldr r3, =(Pico+0x22200)
  111. ldr r1, [r2, #8] @ SRam.end
  112. cmp r0, r1
  113. bgt m_read16_nosram
  114. ldr r1, [r2, #4] @ SRam.start
  115. cmp r0, r1
  116. blt m_read16_nosram
  117. ldrb r1, [r3, #0x11] @ Pico.m.sram_reg
  118. tst r1, #SRR_MAPPED
  119. beq m_read16_nosram
  120. ldr r1, [r2, #0x0c]
  121. tst r1, #SRF_EEPROM
  122. bne EEPROM_read
  123. ldr r1, [r2, #4] @ SRam.start
  124. ldr r2, [r2] @ SRam.data
  125. sub r0, r0, r1
  126. add r0, r0, r2
  127. ldrb r1, [r0], #1
  128. ldrb r0, [r0]
  129. orr r0, r0, r1, lsl #8
  130. bx lr
  131. m_read16_nosram:
  132. ldr r1, [r3, #4] @ romsize
  133. cmp r0, r1
  134. movgt r0, #0
  135. bxgt lr @ bad location
  136. @ XXX: banking unfriendly
  137. ldr r1, [r3]
  138. ldrh r0, [r1, r0]
  139. bx lr
  140. PicoRead16_io: @ u32 a, u32 d
  141. bic r2, r0, #0x001f @ most commonly we get i/o port read,
  142. cmp r2, #0xa10000 @ so check for it first
  143. bne m_read16_not_io
  144. stmfd sp!,{lr}
  145. bl m_read8_misc_io @ same as read8
  146. orr r0, r0, r0, lsl #8 @ only has bytes mirrored
  147. ldmfd sp!,{pc}
  148. m_read16_not_io:
  149. and r2, r0, #0xfc00
  150. cmp r2, #0x1000
  151. bne m_read16_not_brq
  152. ldr r3, =(Pico+0x22200)
  153. and r2, r0, #0xff00
  154. ldr r0, [r3, #8] @ Pico.m.rotate
  155. add r0, r0, #1
  156. strb r0, [r3, #8]
  157. eor r0, r0, r0, lsl #5
  158. eor r0, r0, r0, lsl #8
  159. bic r0, r0, #0x100 @ bit8 defined in this area
  160. cmp r2, #0x1100
  161. bxne lr @ not busreq
  162. ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run
  163. ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset
  164. orr r0, r0, r1, lsl #8
  165. orr r0, r0, r2, lsl #8
  166. bx lr
  167. m_read16_not_brq:
  168. ldr r2, =PicoOpt
  169. ldr r2, [r2]
  170. tst r2, #POPT_EN_32X
  171. bne PicoRead16_32x
  172. mov r0, #0
  173. bx lr
  174. @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
  175. PicoWrite8_io: @ u32 a, u32 d
  176. bic r2, r0, #0x1e @ most commonly we get i/o port write,
  177. eor r2, r2, #0xa10000 @ so check for it first
  178. eors r2, r2, #1
  179. bne m_write8_not_io
  180. m_write8_io:
  181. ldr r2, =PicoOpt
  182. and r0, r0, #0x1e
  183. ldr r2, [r2]
  184. ldr r3, =(Pico+0x22000) @ Pico.ioports
  185. tst r2, #POPT_6BTN_PAD
  186. beq m_write8_io_done
  187. cmp r0, #2
  188. cmpne r0, #4
  189. bne m_write8_io_done @ not likely to happen
  190. add r2, r3, #0x200 @ Pico+0x22200
  191. mov r12,#0
  192. cmp r0, #2
  193. streqb r12,[r2,#0x18]
  194. strneb r12,[r2,#0x19] @ Pico.m.padDelay[i] = 0
  195. tst r1, #0x40 @ TH
  196. beq m_write8_io_done
  197. ldrb r12,[r3, r0, lsr #1]
  198. tst r12,#0x40
  199. bne m_write8_io_done
  200. cmp r0, #2
  201. ldreqb r12,[r2,#0x0a]
  202. ldrneb r12,[r2,#0x0b] @ Pico.m.padTHPhase
  203. add r12,r12,#1
  204. streqb r12,[r2,#0x0a]
  205. strneb r12,[r2,#0x0b] @ Pico.m.padTHPhase
  206. m_write8_io_done:
  207. strb r1, [r3, r0, lsr #1]
  208. bx lr
  209. m_write8_not_io:
  210. tst r0, #1
  211. bne m_write8_not_z80ctl @ even addrs only
  212. and r2, r0, #0xff00
  213. cmp r2, #0x1100
  214. moveq r0, r1
  215. beq ctl_write_z80busreq
  216. cmp r2, #0x1200
  217. moveq r0, r1
  218. beq ctl_write_z80reset
  219. m_write8_not_z80ctl:
  220. @ unlikely
  221. eor r2, r0, #0xa10000
  222. eor r2, r2, #0x003000
  223. eors r2, r2, #0x0000f1
  224. bne m_write8_not_sreg
  225. ldr r3, =(Pico+0x22200)
  226. ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg
  227. and r1, r1, #(SRR_MAPPED|SRR_READONLY)
  228. bic r2, r2, #(SRR_MAPPED|SRR_READONLY)
  229. orr r2, r2, r1
  230. strb r2, [r3, #(8+9)]
  231. bx lr
  232. m_write8_not_sreg:
  233. ldr r2, =PicoOpt
  234. ldr r2, [r2]
  235. tst r2, #POPT_EN_32X
  236. bne PicoWrite8_32x
  237. bx lr
  238. @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
  239. PicoWrite16_io: @ u32 a, u32 d
  240. bic r2, r0, #0x1f @ most commonly we get i/o port write,
  241. cmp r2, #0xa10000 @ so check for it first
  242. beq m_write8_io
  243. m_write16_not_io:
  244. and r2, r0, #0xff00
  245. cmp r2, #0x1100
  246. moveq r0, r1, lsr #8
  247. beq ctl_write_z80busreq
  248. cmp r2, #0x1200
  249. moveq r0, r1, lsr #8
  250. beq ctl_write_z80reset
  251. m_write16_not_z80ctl:
  252. @ unlikely
  253. eor r2, r0, #0xa10000
  254. eor r2, r2, #0x003000
  255. eors r2, r2, #0x0000f0
  256. bne m_write16_not_sreg
  257. ldr r3, =(Pico+0x22200)
  258. ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg
  259. and r1, r1, #(SRR_MAPPED|SRR_READONLY)
  260. bic r2, r2, #(SRR_MAPPED|SRR_READONLY)
  261. orr r2, r2, r1
  262. strb r2, [r3, #(8+9)]
  263. bx lr
  264. m_write16_not_sreg:
  265. ldr r2, =PicoOpt
  266. ldr r2, [r2]
  267. tst r2, #POPT_EN_32X
  268. bne PicoWrite16_32x
  269. bx lr
  270. .pool
  271. @ vim:filetype=armasm