stub_arm.S 15 KB

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  1. @*
  2. @* Compiler helper functions and some SVP HLE code
  3. @* (C) notaz, 2008,2009
  4. @*
  5. @* This work is licensed under the terms of MAME license.
  6. @* See COPYING file in the top-level directory.
  7. @*
  8. .global ssp_drc_entry
  9. .global ssp_drc_next
  10. .global ssp_drc_next_patch
  11. .global ssp_drc_end
  12. .global ssp_hle_800
  13. .global ssp_hle_902
  14. .global ssp_hle_07_030
  15. .global ssp_hle_07_036
  16. .global ssp_hle_07_6d6
  17. .global ssp_hle_11_12c
  18. .global ssp_hle_11_384
  19. .global ssp_hle_11_38a
  20. .text
  21. .align 2
  22. @ SSP_GR0, SSP_X, SSP_Y, SSP_A,
  23. @ SSP_ST, SSP_STACK, SSP_PC, SSP_P,
  24. @ SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
  25. @ SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
  26. @ register map:
  27. @ r4: XXYY
  28. @ r5: A
  29. @ r6: STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
  30. @ r7: SSP context
  31. @ r8: r0-r2 (.210)
  32. @ r9: r4-r6 (.654)
  33. @ r10: P
  34. @ r11: cycles
  35. @ r12: tmp
  36. #define SSP_OFFS_GR 0x400
  37. #define SSP_PC 6
  38. #define SSP_P 7
  39. #define SSP_PM0 8
  40. #define SSP_PMC 14
  41. #define SSP_OFFS_PM_WRITE 0x46c // pmac_write[]
  42. #define SSP_OFFS_EMUSTAT 0x484 // emu_status
  43. #define SSP_OFFS_IRAM_ROM 0x48c // ptr_iram_rom
  44. #define SSP_OFFS_DRAM 0x490 // ptr_dram
  45. #define SSP_OFFS_IRAM_DIRTY 0x494
  46. #define SSP_OFFS_IRAM_CTX 0x498 // iram_context
  47. #define SSP_OFFS_BLTAB 0x49c // block_table
  48. #define SSP_OFFS_BLTAB_IRAM 0x4a0
  49. #define SSP_OFFS_TMP0 0x4a4 // for entry PC
  50. #define SSP_OFFS_TMP1 0x4a8
  51. #define SSP_OFFS_TMP2 0x4ac
  52. #define SSP_WAIT_PM0 0x2000
  53. .macro ssp_drc_do_next patch_jump=0
  54. .if \patch_jump
  55. str lr, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
  56. .endif
  57. mov r0, r0, lsl #16
  58. mov r0, r0, lsr #16
  59. str r0, [r7, #SSP_OFFS_TMP0]
  60. cmp r0, #0x400
  61. blt 0f @ ssp_de_iram
  62. ldr r2, [r7, #SSP_OFFS_BLTAB]
  63. ldr r2, [r2, r0, lsl #2]
  64. tst r2, r2
  65. .if \patch_jump
  66. bne ssp_drc_do_patch
  67. .else
  68. bxne r2
  69. .endif
  70. bl ssp_translate_block
  71. mov r2, r0
  72. ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
  73. ldr r1, [r7, #SSP_OFFS_BLTAB]
  74. str r2, [r1, r0, lsl #2]
  75. .if \patch_jump
  76. b ssp_drc_do_patch
  77. .else
  78. bx r2
  79. .endif
  80. 0: @ ssp_de_iram:
  81. ldr r1, [r7, #SSP_OFFS_IRAM_DIRTY]
  82. tst r1, r1
  83. ldreq r1, [r7, #SSP_OFFS_IRAM_CTX]
  84. beq 1f @ ssp_de_iram_ctx
  85. bl ssp_get_iram_context
  86. mov r1, #0
  87. str r1, [r7, #SSP_OFFS_IRAM_DIRTY]
  88. mov r1, r0
  89. str r1, [r7, #SSP_OFFS_IRAM_CTX]
  90. ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
  91. 1: @ ssp_de_iram_ctx:
  92. ldr r2, [r7, #SSP_OFFS_BLTAB_IRAM]
  93. add r2, r2, r1, lsl #12 @ block_tab_iram + iram_context * 0x800/2*4
  94. add r1, r2, r0, lsl #2
  95. ldr r2, [r1]
  96. tst r2, r2
  97. .if \patch_jump
  98. bne ssp_drc_do_patch
  99. .else
  100. bxne r2
  101. .endif
  102. str r1, [r7, #SSP_OFFS_TMP1]
  103. bl ssp_translate_block
  104. mov r2, r0
  105. ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
  106. ldr r1, [r7, #SSP_OFFS_TMP1] @ &block_table_iram[iram_context][rPC]
  107. str r2, [r1]
  108. .if \patch_jump
  109. b ssp_drc_do_patch
  110. .else
  111. bx r2
  112. .endif
  113. .endm @ ssp_drc_do_next
  114. ssp_drc_entry:
  115. stmfd sp!, {r4-r11, lr}
  116. mov r11, r0
  117. ssp_regfile_load:
  118. ldr r7, =ssp
  119. ldr r7, [r7]
  120. add r2, r7, #0x400
  121. add r2, r2, #4
  122. ldmia r2, {r3,r4,r5,r6,r8}
  123. mov r3, r3, lsr #16
  124. mov r3, r3, lsl #16
  125. orr r4, r3, r4, lsr #16 @ XXYY
  126. and r8, r8, #0x0f0000
  127. mov r8, r8, lsl #13 @ sss0 *
  128. and r9, r6, #0x670000
  129. tst r6, #0x80000000
  130. orrne r8, r8, #0x8
  131. tst r6, #0x20000000
  132. orrne r8, r8, #0x4 @ sss0 * NZ..
  133. orr r6, r8, r9, lsr #12 @ sss0 * .uu. .lll NZ..
  134. ldr r8, [r7, #0x440] @ r0-r2
  135. ldr r9, [r7, #0x444] @ r4-r6
  136. ldr r10,[r7, #(0x400+SSP_P*4)] @ P
  137. ldr r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
  138. mov r0, r0, lsr #16
  139. ssp_drc_next:
  140. ssp_drc_do_next 0
  141. ssp_drc_next_patch:
  142. ssp_drc_do_next 1
  143. ssp_drc_do_patch:
  144. ldr r1, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
  145. subs r12,r2, r1
  146. moveq r3, #0xe1000000
  147. orreq r3, r3, #0x00a00000 @ nop
  148. streq r3, [r1, #-4]
  149. beq ssp_drc_dp_end
  150. cmp r12,#4
  151. ldreq r3, [r1]
  152. addeq r3, r3, #1
  153. streq r3, [r1, #-4] @ move the other cond up
  154. moveq r3, #0xe1000000
  155. orreq r3, r3, #0x00a00000
  156. streq r3, [r1] @ fill it's place with nop
  157. beq ssp_drc_dp_end
  158. ldr r3, [r1, #-4]
  159. sub r12,r12,#4
  160. mov r3, r3, lsr #24
  161. bic r3, r3, #1 @ L bit
  162. orr r3, r3, r12,lsl #6
  163. mov r3, r3, ror #8 @ patched branch instruction
  164. str r3, [r1, #-4] @ patch the bl/b to jump directly to another handler
  165. ssp_drc_dp_end:
  166. str r2, [r7, #SSP_OFFS_TMP1]
  167. sub r0, r1, #4
  168. add r1, r1, #4
  169. bl cache_flush_d_inval_i
  170. ldr r2, [r7, #SSP_OFFS_TMP1]
  171. ldr r0, [r7, #SSP_OFFS_TMP0]
  172. bx r2
  173. ssp_drc_end:
  174. mov r0, r0, lsl #16
  175. str r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
  176. ssp_regfile_store:
  177. str r10,[r7, #(0x400+SSP_P*4)] @ P
  178. str r8, [r7, #0x440] @ r0-r2
  179. str r9, [r7, #0x444] @ r4-r6
  180. mov r9, r6, lsr #13
  181. and r9, r9, #(7<<16) @ STACK
  182. mov r3, r6, lsl #28
  183. msr cpsr_flg, r3 @ to to ARM PSR
  184. and r6, r6, #0x670
  185. mov r6, r6, lsl #12
  186. orrmi r6, r6, #0x80000000 @ N
  187. orreq r6, r6, #0x20000000 @ Z
  188. mov r3, r4, lsl #16 @ Y
  189. mov r2, r4, lsr #16
  190. mov r2, r2, lsl #16 @ X
  191. add r8, r7, #0x400
  192. add r8, r8, #4
  193. stmia r8, {r2,r3,r5,r6,r9}
  194. mov r0, r11
  195. ldmfd sp!, {r4-r11, lr}
  196. bx lr
  197. @ ld A, PM0
  198. @ andi 2
  199. @ bra z=1, gloc_0800
  200. ssp_hle_800:
  201. ldr r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
  202. ldr r1, [r7, #SSP_OFFS_EMUSTAT]
  203. tst r0, #0x20000
  204. orreq r1, r1, #SSP_WAIT_PM0
  205. subeq r11,r11, #1024
  206. streq r1, [r7, #SSP_OFFS_EMUSTAT]
  207. mov r0, #0x400
  208. beq ssp_drc_end
  209. orrne r0, r0, #0x004
  210. b ssp_drc_next
  211. .macro hle_flushflags
  212. bic r6, r6, #0xf
  213. mrs r1, cpsr
  214. orr r6, r6, r1, lsr #28
  215. .endm
  216. .macro hle_popstack
  217. sub r6, r6, #0x20000000
  218. add r1, r7, #0x400
  219. add r1, r1, #0x048 @ stack
  220. add r1, r1, r6, lsr #28
  221. ldrh r0, [r1]
  222. .endm
  223. ssp_hle_902:
  224. cmp r11, #0
  225. ble ssp_drc_end
  226. add r1, r7, #0x200
  227. ldrh r0, [r1]
  228. ldr r3, [r7, #SSP_OFFS_IRAM_ROM]
  229. add r2, r3, r0, lsl #1 @ (r7|00)
  230. ldrh r0, [r2], #2
  231. mov r5, r5, lsl #16
  232. mov r5, r5, lsr #16
  233. bic r0, r0, #0xfc00
  234. add r3, r3, r0, lsl #1 @ IRAM dest
  235. ldrh r12,[r2], #2 @ length
  236. bic r3, r3, #3 @ always seen aligned
  237. @ orr r5, r5, #0x08000000
  238. @ orr r5, r5, #0x00880000
  239. @ sub r5, r5, r12, lsl #16
  240. bic r6, r6, #0xf
  241. add r12,r12,#1
  242. mov r0, #1
  243. str r0, [r7, #SSP_OFFS_IRAM_DIRTY]
  244. sub r11,r11,r12,lsl #1
  245. sub r11,r11,r12 @ -= length*3
  246. ssp_hle_902_loop:
  247. ldrh r0, [r2], #2
  248. ldrh r1, [r2], #2
  249. subs r12,r12,#2
  250. orr r0, r0, r1, lsl #16
  251. str r0, [r3], #4
  252. bgt ssp_hle_902_loop
  253. tst r12, #1
  254. ldrneh r0, [r2], #2
  255. strneh r0, [r3], #2
  256. ldr r0, [r7, #SSP_OFFS_IRAM_ROM]
  257. add r1, r7, #0x200
  258. sub r2, r2, r0
  259. mov r2, r2, lsr #1
  260. strh r2, [r1] @ (r7|00)
  261. sub r0, r3, r0
  262. mov r0, r0, lsr #1
  263. orr r0, r0, #0x08000000
  264. orr r0, r0, #0x001c8000
  265. str r0, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
  266. str r0, [r7, #(SSP_OFFS_PM_WRITE+4*4)]
  267. hle_popstack
  268. subs r11,r11,#16 @ timeslice is likely to end
  269. ble ssp_drc_end
  270. b ssp_drc_next
  271. @ this one is car rendering related
  272. .macro hle_11_12c_mla offs_in
  273. ldrsh r5, [r7, #(\offs_in+0)]
  274. ldrsh r0, [r7, #(\offs_in+2)]
  275. ldrsh r1, [r7, #(\offs_in+4)]
  276. mul r5, r2, r5
  277. ldrsh r12,[r7, #(\offs_in+6)]
  278. mla r5, r3, r0, r5
  279. mla r5, r4, r1, r5
  280. add r5, r5, r12,lsl #11
  281. movs r5, r5, lsr #13
  282. add r1, r7, r8, lsr #23
  283. strh r5, [r1]
  284. add r8, r8, #(1<<24)
  285. .endm
  286. ssp_hle_11_12c:
  287. cmp r11, #0
  288. ble ssp_drc_end
  289. mov r0, #0
  290. bl ssp_pm_read
  291. mov r4, r0
  292. mov r0, #0
  293. bl ssp_pm_read
  294. mov r5, r0
  295. mov r0, #0
  296. bl ssp_pm_read
  297. mov r2, r4, lsl #16
  298. mov r2, r2, asr #15 @ (r7|00) << 1
  299. mov r3, r5, lsl #16
  300. mov r3, r3, asr #15 @ (r7|01) << 1
  301. mov r4, r0, lsl #16
  302. mov r4, r4, asr #15 @ (r7|10) << 1
  303. bic r8, r8, #0xff
  304. mov r8, r8, ror #16
  305. hle_11_12c_mla 0x20
  306. hle_11_12c_mla 0x28
  307. hle_11_12c_mla 0x30
  308. mov r8, r8, ror #16
  309. orr r8, r8, #0x1c
  310. @ hle_flushflags
  311. hle_popstack
  312. sub r11,r11,#33
  313. b ssp_drc_next
  314. ssp_hle_11_384:
  315. mov r3, #2
  316. b ssp_hle_11_38x
  317. ssp_hle_11_38a:
  318. mov r3, #3 @ r5
  319. ssp_hle_11_38x:
  320. cmp r11, #0
  321. ble ssp_drc_end
  322. mov r2, #0 @ EFh, EEh
  323. mov r1, #1 @ r4
  324. add r0, r7, #0x1c0 @ r0 (based)
  325. ssp_hle_11_38x_loop:
  326. ldrh r5, [r0], #2
  327. ldr r12,[r7, #0x224]
  328. mov r5, r5, lsl #16
  329. eor r5, r5, r5, asr #31
  330. add r5, r5, r5, lsr #31 @ abs(r5)
  331. cmp r5, r12,lsl #16
  332. orrpl r2, r2, r1,lsl #16 @ EFh |= r4
  333. ldrh r5, [r0, #2]!
  334. ldr r12,[r7, #0x220]
  335. cmp r5, r12,lsr #16
  336. orrpl r2, r2, r1,lsl #16 @ EFh |= r4
  337. ldr r12,[r7, #0x1e8]
  338. add r0, r0, #2
  339. mov r12,r12,lsl #16
  340. cmp r5, r12,lsr #16
  341. orrmi r2, r2, r1
  342. mov r1, r1, lsl #1
  343. subs r3, r3, #1
  344. bpl ssp_hle_11_38x_loop
  345. str r2, [r7, #0x1dc]
  346. sub r0, r0, r7
  347. bic r8, r8, #0xff
  348. orr r8, r8, r0, lsr #1
  349. bic r9, r9, #0xff
  350. orr r9, r9, r1
  351. @ hle_flushflags
  352. hle_popstack
  353. sub r11,r11,#(9+30*4)
  354. b ssp_drc_next
  355. ssp_hle_07_6d6:
  356. cmp r11, #0
  357. ble ssp_drc_end
  358. ldr r1, [r7, #0x20c]
  359. and r0, r8, #0xff @ assuming alignment
  360. add r0, r7, r0, lsl #1
  361. mov r2, r1, lsr #16
  362. mov r1, r1, lsl #16 @ 106h << 16
  363. mov r2, r2, lsl #16 @ 107h << 16
  364. ssp_hle_07_6d6_loop:
  365. ldr r5, [r0], #4
  366. tst r5, r5
  367. bmi ssp_hle_07_6d6_end
  368. mov r5, r5, lsl #16
  369. cmp r5, r1
  370. movmi r1, r5
  371. cmp r5, r2
  372. sub r11,r11,#16
  373. bmi ssp_hle_07_6d6_loop
  374. mov r2, r5
  375. b ssp_hle_07_6d6_loop
  376. ssp_hle_07_6d6_end:
  377. sub r0, r0, r7
  378. mov r0, r0, lsr #1
  379. bic r8, r8, #0xff
  380. orr r8, r8, r0
  381. orr r1, r2, r1, lsr #16
  382. str r1, [r7, #0x20c]
  383. hle_popstack
  384. sub r11,r11,#6
  385. b ssp_drc_next
  386. ssp_hle_07_030:
  387. ldrh r0, [r7]
  388. mov r0, r0, lsl #4
  389. orr r0, r0, r0, lsr #16
  390. strh r0, [r7]
  391. sub r11,r11,#3
  392. ssp_hle_07_036:
  393. ldr r1, [r7, #0x1e0] @ F1h F0h
  394. rsb r5, r1, r1, lsr #16
  395. mov r5, r5, lsl #16 @ AL not needed
  396. cmp r5, #(4<<16)
  397. sub r11,r11,#5
  398. bmi hle_07_036_ending2
  399. ldr r1, [r7, #0x1dc] @ EEh
  400. cmp r5, r1, lsl #16
  401. sub r11,r11,#5
  402. bpl hle_07_036_ret
  403. mov r0, r5, lsr #16
  404. add r1, r7, #0x100
  405. strh r0, [r1, #0xea] @ F5h
  406. ldr r0, [r7, #0x1e0] @ F0h
  407. and r0, r0, #3
  408. strh r0, [r1, #0xf0] @ F8h
  409. add r2, r0, #0xc0 @ r2
  410. add r2, r7, r2, lsl #1
  411. ldrh r2, [r2]
  412. ldr r0, [r7]
  413. mov r1, #4
  414. and r0, r0, r2
  415. bl ssp_pm_write
  416. @ will handle PMC later
  417. ldr r0, [r7, #0x1e8] @ F5h << 16
  418. ldr r1, [r7, #0x1f0] @ F8h
  419. ldr r2, [r7, #0x1d4] @ EAh
  420. sub r0, r0, #(3<<16)
  421. add r0, r0, r1, lsl #16
  422. sub r0, r2, r0, asr #18
  423. and r0, r0, #0x7f
  424. rsbs r0, r0, #0x78 @ length
  425. ble hle_07_036_ending1
  426. sub r11,r11,r0
  427. @ copy part
  428. ldr r1, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
  429. ldr r2, [r7, #SSP_OFFS_DRAM]
  430. mov r1, r1, lsl #16
  431. add r1, r2, r1, lsr #15 @ addr (based)
  432. ldrh r2, [r7, #0] @ pattern
  433. ldrh r3, [r7, #6] @ mode
  434. mov r12, #0x4000
  435. orr r12,r12,#0x0018
  436. subs r12,r3, r12
  437. subnes r12,r12,#0x0400
  438. blne tr_unhandled
  439. orr r2, r2, r2, lsl #16
  440. tst r3, #0x400
  441. bne hle_07_036_ovrwr
  442. hle_07_036_no_ovrwr:
  443. tst r1, #2
  444. strneh r2, [r1], #0x3e @ align
  445. subne r0, r0, #1
  446. subs r0, r0, #4
  447. blt hle_07_036_l2
  448. hle_07_036_l1:
  449. subs r0, r0, #4
  450. str r2, [r1], #0x40
  451. str r2, [r1], #0x40
  452. bge hle_07_036_l1
  453. hle_07_036_l2:
  454. tst r0, #2
  455. strne r2, [r1], #0x40
  456. tst r0, #1
  457. strneh r2, [r1], #2
  458. b hle_07_036_end_copy
  459. hle_07_036_ovrwr:
  460. tst r2, #0x000f
  461. orreq r12,r12,#0x000f
  462. tst r2, #0x00f0
  463. orreq r12,r12,#0x00f0
  464. tst r2, #0x0f00
  465. orreq r12,r12,#0x0f00
  466. tst r2, #0xf000
  467. orreq r12,r12,#0xf000
  468. orrs r12,r12,r12,lsl #16
  469. beq hle_07_036_no_ovrwr
  470. tst r1, #2
  471. beq hle_07_036_ol0
  472. ldrh r3, [r1]
  473. and r3, r3, r12
  474. orr r3, r3, r2
  475. strh r3, [r1], #0x3e @ align
  476. sub r0, r0, #1
  477. hle_07_036_ol0:
  478. subs r0, r0, #2
  479. blt hle_07_036_ol2
  480. hle_07_036_ol1:
  481. subs r0, r0, #2
  482. ldr r3, [r1]
  483. and r3, r3, r12
  484. orr r3, r3, r2
  485. str r3, [r1], #0x40
  486. bge hle_07_036_ol1
  487. hle_07_036_ol2:
  488. tst r0, #1
  489. ldrneh r3, [r1]
  490. andne r3, r3, r12
  491. orrne r3, r3, r2
  492. strneh r3, [r1], #2
  493. hle_07_036_end_copy:
  494. ldr r2, [r7, #SSP_OFFS_DRAM]
  495. add r3, r7, #0x400
  496. sub r0, r1, r2 @ new addr
  497. mov r0, r0, lsr #1
  498. strh r0, [r3, #(0x6c+4*4)] @ SSP_OFFS_PM_WRITE+4*4 (low)
  499. hle_07_036_ending1:
  500. ldr r0, [r7, #0x1e0] @ F1h << 16
  501. add r0, r0, #(1<<16)
  502. and r0, r0, #(3<<16)
  503. add r0, r0, #(0xc4<<16)
  504. bic r8, r8, #0xff0000
  505. orr r8, r8, r0 @ r2
  506. add r0, r7, r0, lsr #15
  507. ldrh r0, [r0]
  508. ldr r2, [r7]
  509. and r0, r0, r2
  510. movs r5, r0, lsl #16
  511. ldr r1, [r7, #4] @ new mode
  512. add r2, r7, #0x400
  513. strh r1, [r2, #(0x6c+4*4+2)] @ SSP_OFFS_PM_WRITE+4*4 (high)
  514. mov r1, #4
  515. bl ssp_pm_write
  516. sub r11,r11,#35
  517. hle_07_036_ret:
  518. hle_popstack
  519. b ssp_drc_next
  520. hle_07_036_ending2:
  521. sub r11,r11,#3
  522. movs r5, r5, lsl #1
  523. bmi hle_07_036_ret
  524. mov r0, #0x87
  525. b ssp_drc_next @ let the dispatcher finish this
  526. @ vim:filetype=armasm