emit_x86.c 17 KB

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  1. /*
  2. * Basic macros to emit x86 instructions and some utils
  3. * Copyright (C) 2008,2009,2010 notaz
  4. *
  5. * This work is licensed under the terms of MAME license.
  6. * See COPYING file in the top-level directory.
  7. *
  8. * note:
  9. * temp registers must be eax-edx due to use of SETcc and r/w 8/16.
  10. * note about silly things like emith_eor_r_r_r:
  11. * these are here because the compiler was designed
  12. * for ARM as it's primary target.
  13. */
  14. #include <stdarg.h>
  15. enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
  16. #define CONTEXT_REG xBP
  17. #define ICOND_JO 0x00
  18. #define ICOND_JNO 0x01
  19. #define ICOND_JB 0x02
  20. #define ICOND_JAE 0x03
  21. #define ICOND_JE 0x04
  22. #define ICOND_JNE 0x05
  23. #define ICOND_JBE 0x06
  24. #define ICOND_JA 0x07
  25. #define ICOND_JS 0x08
  26. #define ICOND_JNS 0x09
  27. #define ICOND_JL 0x0c
  28. #define ICOND_JGE 0x0d
  29. #define ICOND_JLE 0x0e
  30. #define ICOND_JG 0x0f
  31. #define IOP_JMP 0xeb
  32. // unified conditions (we just use rel8 jump instructions for x86)
  33. #define DCOND_EQ ICOND_JE
  34. #define DCOND_NE ICOND_JNE
  35. #define DCOND_MI ICOND_JS // MInus
  36. #define DCOND_PL ICOND_JNS // PLus or zero
  37. #define DCOND_HI ICOND_JA // higher (unsigned)
  38. #define DCOND_HS ICOND_JAE // higher || same (unsigned)
  39. #define DCOND_LO ICOND_JB // lower (unsigned)
  40. #define DCOND_LS ICOND_JBE // lower || same (unsigned)
  41. #define DCOND_GE ICOND_JGE // greater || equal (signed)
  42. #define DCOND_GT ICOND_JG // greater (signed)
  43. #define DCOND_LE ICOND_JLE // less || equal (signed)
  44. #define DCOND_LT ICOND_JL // less (signed)
  45. #define DCOND_VS ICOND_JO // oVerflow Set
  46. #define DCOND_VC ICOND_JNO // oVerflow Clear
  47. #define EMIT_PTR(ptr, val, type) \
  48. *(type *)(ptr) = val
  49. #define EMIT(val, type) { \
  50. EMIT_PTR(tcache_ptr, val, type); \
  51. tcache_ptr += sizeof(type); \
  52. }
  53. #define EMIT_OP(op) { \
  54. COUNT_OP; \
  55. EMIT(op, u8); \
  56. }
  57. #define EMIT_MODRM(mod,r,rm) \
  58. EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)
  59. #define EMIT_SIB(scale,index,base) \
  60. EMIT(((scale)<<6) | ((index)<<3) | (base), u8)
  61. #define EMIT_OP_MODRM(op,mod,r,rm) do { \
  62. EMIT_OP(op); \
  63. EMIT_MODRM(mod, r, rm); \
  64. } while (0)
  65. #define JMP8_POS(ptr) \
  66. ptr = tcache_ptr; \
  67. tcache_ptr += 2
  68. #define JMP8_EMIT(op, ptr) \
  69. EMIT_PTR(ptr, 0x70|(op), u8); \
  70. EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
  71. #define JMP8_EMIT_NC(ptr) \
  72. EMIT_PTR(ptr, IOP_JMP, u8); \
  73. EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
  74. // _r_r
  75. #define emith_move_r_r(dst, src) \
  76. EMIT_OP_MODRM(0x8b, 3, dst, src)
  77. #define emith_add_r_r(d, s) \
  78. EMIT_OP_MODRM(0x01, 3, s, d)
  79. #define emith_sub_r_r(d, s) \
  80. EMIT_OP_MODRM(0x29, 3, s, d)
  81. #define emith_adc_r_r(d, s) \
  82. EMIT_OP_MODRM(0x11, 3, s, d)
  83. #define emith_sbc_r_r(d, s) \
  84. EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */
  85. #define emith_or_r_r(d, s) \
  86. EMIT_OP_MODRM(0x09, 3, s, d)
  87. #define emith_and_r_r(d, s) \
  88. EMIT_OP_MODRM(0x21, 3, s, d)
  89. #define emith_eor_r_r(d, s) \
  90. EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */
  91. #define emith_tst_r_r(d, s) \
  92. EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */
  93. #define emith_cmp_r_r(d, s) \
  94. EMIT_OP_MODRM(0x39, 3, s, d)
  95. // fake teq - test equivalence - get_flags(d ^ s)
  96. #define emith_teq_r_r(d, s) { \
  97. emith_push(d); \
  98. emith_eor_r_r(d, s); \
  99. emith_pop(d); \
  100. }
  101. #define emith_mvn_r_r(d, s) { \
  102. if (d != s) \
  103. emith_move_r_r(d, s); \
  104. EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
  105. }
  106. #define emith_negc_r_r(d, s) { \
  107. int tmp_ = rcache_get_tmp(); \
  108. emith_move_r_imm(tmp_, 0); \
  109. emith_sbc_r_r(tmp_, s); \
  110. emith_move_r_r(d, tmp_); \
  111. rcache_free_tmp(tmp_); \
  112. }
  113. #define emith_neg_r_r(d, s) { \
  114. if (d != s) \
  115. emith_move_r_r(d, s); \
  116. EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
  117. }
  118. // _r_r_r
  119. #define emith_eor_r_r_r(d, s1, s2) { \
  120. if (d == s1) { \
  121. emith_eor_r_r(d, s2); \
  122. } else if (d == s2) { \
  123. emith_eor_r_r(d, s1); \
  124. } else { \
  125. emith_move_r_r(d, s1); \
  126. emith_eor_r_r(d, s2); \
  127. } \
  128. }
  129. // _r_r_shift
  130. #define emith_or_r_r_lsl(d, s, lslimm) { \
  131. int tmp_ = rcache_get_tmp(); \
  132. emith_lsl(tmp_, s, lslimm); \
  133. emith_or_r_r(d, tmp_); \
  134. rcache_free_tmp(tmp_); \
  135. }
  136. // d != s
  137. #define emith_eor_r_r_lsr(d, s, lsrimm) { \
  138. emith_push(s); \
  139. emith_lsr(s, s, lsrimm); \
  140. emith_eor_r_r(d, s); \
  141. emith_pop(s); \
  142. }
  143. // _r_imm
  144. #define emith_move_r_imm(r, imm) { \
  145. EMIT_OP(0xb8 + (r)); \
  146. EMIT(imm, u32); \
  147. }
  148. #define emith_move_r_imm_s8(r, imm) \
  149. emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))
  150. #define emith_arith_r_imm(op, r, imm) do { \
  151. EMIT_OP_MODRM(0x81, 3, op, r); \
  152. EMIT(imm, u32); \
  153. } while (0)
  154. #define emith_add_r_imm(r, imm) \
  155. emith_arith_r_imm(0, r, imm)
  156. #define emith_or_r_imm(r, imm) \
  157. emith_arith_r_imm(1, r, imm)
  158. #define emith_adc_r_imm(r, imm) \
  159. emith_arith_r_imm(2, r, imm)
  160. #define emith_sbc_r_imm(r, imm) \
  161. emith_arith_r_imm(3, r, imm) // sbb
  162. #define emith_and_r_imm(r, imm) \
  163. emith_arith_r_imm(4, r, imm)
  164. #define emith_sub_r_imm(r, imm) \
  165. emith_arith_r_imm(5, r, imm)
  166. #define emith_eor_r_imm(r, imm) \
  167. emith_arith_r_imm(6, r, imm)
  168. #define emith_cmp_r_imm(r, imm) \
  169. emith_arith_r_imm(7, r, imm)
  170. #define emith_tst_r_imm(r, imm) do { \
  171. EMIT_OP_MODRM(0xf7, 3, 0, r); \
  172. EMIT(imm, u32); \
  173. } while (0)
  174. // fake
  175. #define emith_bic_r_imm(r, imm) \
  176. emith_arith_r_imm(4, r, ~(imm))
  177. // fake conditionals (using SJMP instead)
  178. #define emith_move_r_imm_c(cond, r, imm) { \
  179. (void)(cond); \
  180. emith_move_r_imm(r, imm); \
  181. }
  182. #define emith_add_r_imm_c(cond, r, imm) { \
  183. (void)(cond); \
  184. emith_add_r_imm(r, imm); \
  185. }
  186. #define emith_sub_r_imm_c(cond, r, imm) { \
  187. (void)(cond); \
  188. emith_sub_r_imm(r, imm); \
  189. }
  190. #define emith_or_r_imm_c(cond, r, imm) \
  191. emith_or_r_imm(r, imm)
  192. #define emith_eor_r_imm_c(cond, r, imm) \
  193. emith_eor_r_imm(r, imm)
  194. #define emith_bic_r_imm_c(cond, r, imm) \
  195. emith_bic_r_imm(r, imm)
  196. #define emith_ror_c(cond, d, s, cnt) \
  197. emith_ror(d, s, cnt)
  198. #define emith_read_r_r_offs_c(cond, r, rs, offs) \
  199. emith_read_r_r_offs(r, rs, offs)
  200. #define emith_write_r_r_offs_c(cond, r, rs, offs) \
  201. emith_write_r_r_offs(r, rs, offs)
  202. #define emith_read8_r_r_offs_c(cond, r, rs, offs) \
  203. emith_read8_r_r_offs(r, rs, offs)
  204. #define emith_write8_r_r_offs_c(cond, r, rs, offs) \
  205. emith_write8_r_r_offs(r, rs, offs)
  206. #define emith_read16_r_r_offs_c(cond, r, rs, offs) \
  207. emith_read16_r_r_offs(r, rs, offs)
  208. #define emith_write16_r_r_offs_c(cond, r, rs, offs) \
  209. emith_write16_r_r_offs(r, rs, offs)
  210. #define emith_jump_reg_c(cond, r) \
  211. emith_jump_reg(r)
  212. #define emith_jump_ctx_c(cond, offs) \
  213. emith_jump_ctx(offs)
  214. #define emith_ret_c(cond) \
  215. emith_ret()
  216. // _r_r_imm
  217. #define emith_add_r_r_imm(d, s, imm) { \
  218. if (d != s) \
  219. emith_move_r_r(d, s); \
  220. emith_add_r_imm(d, imm); \
  221. }
  222. #define emith_and_r_r_imm(d, s, imm) { \
  223. if (d != s) \
  224. emith_move_r_r(d, s); \
  225. emith_and_r_imm(d, imm); \
  226. }
  227. // shift
  228. #define emith_shift(op, d, s, cnt) { \
  229. if (d != s) \
  230. emith_move_r_r(d, s); \
  231. EMIT_OP_MODRM(0xc1, 3, op, d); \
  232. EMIT(cnt, u8); \
  233. }
  234. #define emith_lsl(d, s, cnt) \
  235. emith_shift(4, d, s, cnt)
  236. #define emith_lsr(d, s, cnt) \
  237. emith_shift(5, d, s, cnt)
  238. #define emith_asr(d, s, cnt) \
  239. emith_shift(7, d, s, cnt)
  240. #define emith_rol(d, s, cnt) \
  241. emith_shift(0, d, s, cnt)
  242. #define emith_ror(d, s, cnt) \
  243. emith_shift(1, d, s, cnt)
  244. #define emith_rolc(r) \
  245. EMIT_OP_MODRM(0xd1, 3, 2, r)
  246. #define emith_rorc(r) \
  247. EMIT_OP_MODRM(0xd1, 3, 3, r)
  248. // misc
  249. #define emith_push(r) \
  250. EMIT_OP(0x50 + (r))
  251. #define emith_push_imm(imm) { \
  252. EMIT_OP(0x68); \
  253. EMIT(imm, u32); \
  254. }
  255. #define emith_pop(r) \
  256. EMIT_OP(0x58 + (r))
  257. #define emith_neg_r(r) \
  258. EMIT_OP_MODRM(0xf7, 3, 3, r)
  259. #define emith_clear_msb(d, s, count) { \
  260. u32 t = (u32)-1; \
  261. t >>= count; \
  262. if (d != s) \
  263. emith_move_r_r(d, s); \
  264. emith_and_r_imm(d, t); \
  265. }
  266. #define emith_clear_msb_c(cond, d, s, count) { \
  267. (void)(cond); \
  268. emith_clear_msb(d, s, count); \
  269. }
  270. #define emith_sext(d, s, bits) { \
  271. emith_lsl(d, s, 32 - (bits)); \
  272. emith_asr(d, d, 32 - (bits)); \
  273. }
  274. #define emith_setc(r) { \
  275. EMIT_OP(0x0f); \
  276. EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
  277. }
  278. // XXX: stupid mess
  279. #define emith_mul_(op, dlo, dhi, s1, s2) { \
  280. int rmr; \
  281. if (dlo != xAX && dhi != xAX) \
  282. emith_push(xAX); \
  283. if (dlo != xDX && dhi != xDX) \
  284. emith_push(xDX); \
  285. if ((s1) == xAX) \
  286. rmr = s2; \
  287. else if ((s2) == xAX) \
  288. rmr = s1; \
  289. else { \
  290. emith_move_r_r(xAX, s1); \
  291. rmr = s2; \
  292. } \
  293. EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
  294. /* XXX: using push/pop for the case of edx->eax; eax->edx */ \
  295. if (dhi != xDX && dhi != -1) \
  296. emith_push(xDX); \
  297. if (dlo != xAX) \
  298. emith_move_r_r(dlo, xAX); \
  299. if (dhi != xDX && dhi != -1) \
  300. emith_pop(dhi); \
  301. if (dlo != xDX && dhi != xDX) \
  302. emith_pop(xDX); \
  303. if (dlo != xAX && dhi != xAX) \
  304. emith_pop(xAX); \
  305. }
  306. #define emith_mul_u64(dlo, dhi, s1, s2) \
  307. emith_mul_(4, dlo, dhi, s1, s2) /* MUL */
  308. #define emith_mul_s64(dlo, dhi, s1, s2) \
  309. emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */
  310. #define emith_mul(d, s1, s2) \
  311. emith_mul_(4, d, -1, s1, s2)
  312. // (dlo,dhi) += signed(s1) * signed(s2)
  313. #define emith_mula_s64(dlo, dhi, s1, s2) { \
  314. emith_push(dhi); \
  315. emith_push(dlo); \
  316. emith_mul_(5, dlo, dhi, s1, s2); \
  317. EMIT_OP_MODRM(0x03, 0, dlo, 4); \
  318. EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
  319. EMIT_OP_MODRM(0x13, 1, dhi, 4); \
  320. EMIT_SIB(0, 4, 4); \
  321. EMIT(4, u8); /* adc dhi, [esp+4] */ \
  322. emith_add_r_imm(xSP, 4*2); \
  323. }
  324. // "flag" instructions are the same
  325. #define emith_subf_r_imm emith_sub_r_imm
  326. #define emith_addf_r_r emith_add_r_r
  327. #define emith_subf_r_r emith_sub_r_r
  328. #define emith_adcf_r_r emith_adc_r_r
  329. #define emith_sbcf_r_r emith_sbc_r_r
  330. #define emith_eorf_r_r emith_eor_r_r
  331. #define emith_negcf_r_r emith_negc_r_r
  332. #define emith_lslf emith_lsl
  333. #define emith_lsrf emith_lsr
  334. #define emith_asrf emith_asr
  335. #define emith_rolf emith_rol
  336. #define emith_rorf emith_ror
  337. #define emith_rolcf emith_rolc
  338. #define emith_rorcf emith_rorc
  339. #define emith_deref_op(op, r, rs, offs) do { \
  340. /* mov r <-> [ebp+#offs] */ \
  341. if ((offs) >= 0x80) { \
  342. EMIT_OP_MODRM(op, 2, r, rs); \
  343. EMIT(offs, u32); \
  344. } else { \
  345. EMIT_OP_MODRM(op, 1, r, rs); \
  346. EMIT(offs, u8); \
  347. } \
  348. } while (0)
  349. #define is_abcdx(r) (xAX <= (r) && (r) <= xDX)
  350. #define emith_read_r_r_offs(r, rs, offs) \
  351. emith_deref_op(0x8b, r, rs, offs)
  352. #define emith_write_r_r_offs(r, rs, offs) \
  353. emith_deref_op(0x89, r, rs, offs)
  354. // note: don't use prefixes on this
  355. #define emith_read8_r_r_offs(r, rs, offs) do { \
  356. int r_ = r; \
  357. if (!is_abcdx(r)) \
  358. r_ = rcache_get_tmp(); \
  359. emith_deref_op(0x8a, r_, rs, offs); \
  360. if ((r) != r_) { \
  361. emith_move_r_r(r, r_); \
  362. rcache_free_tmp(r_); \
  363. } \
  364. } while (0)
  365. #define emith_write8_r_r_offs(r, rs, offs) do {\
  366. int r_ = r; \
  367. if (!is_abcdx(r)) { \
  368. r_ = rcache_get_tmp(); \
  369. emith_move_r_r(r_, r); \
  370. } \
  371. emith_deref_op(0x88, r_, rs, offs); \
  372. if ((r) != r_) \
  373. rcache_free_tmp(r_); \
  374. } while (0)
  375. #define emith_read16_r_r_offs(r, rs, offs) { \
  376. EMIT(0x66, u8); /* operand override */ \
  377. emith_read_r_r_offs(r, rs, offs); \
  378. }
  379. #define emith_write16_r_r_offs(r, rs, offs) { \
  380. EMIT(0x66, u8); \
  381. emith_write_r_r_offs(r, rs, offs); \
  382. }
  383. #define emith_ctx_read(r, offs) \
  384. emith_read_r_r_offs(r, CONTEXT_REG, offs)
  385. #define emith_ctx_write(r, offs) \
  386. emith_write_r_r_offs(r, CONTEXT_REG, offs)
  387. #define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
  388. int r_ = r, offs_ = offs, cnt_ = cnt; \
  389. for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
  390. emith_ctx_read(r_, offs_); \
  391. } while (0)
  392. #define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
  393. int r_ = r, offs_ = offs, cnt_ = cnt; \
  394. for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
  395. emith_ctx_write(r_, offs_); \
  396. } while (0)
  397. // assumes EBX is free
  398. #define emith_ret_to_ctx(offs) { \
  399. emith_pop(xBX); \
  400. emith_ctx_write(xBX, offs); \
  401. }
  402. #define emith_jump(ptr) { \
  403. u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
  404. EMIT_OP(0xe9); \
  405. EMIT(disp, u32); \
  406. }
  407. #define emith_jump_patchable(target) \
  408. emith_jump(target)
  409. #define emith_jump_cond(cond, ptr) { \
  410. u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 6); \
  411. EMIT(0x0f, u8); \
  412. EMIT_OP(0x80 | (cond)); \
  413. EMIT(disp, u32); \
  414. }
  415. #define emith_jump_cond_patchable(cond, target) \
  416. emith_jump_cond(cond, target)
  417. #define emith_jump_patch(ptr, target) do { \
  418. u32 disp_ = (u32)(target) - ((u32)(ptr) + 4); \
  419. u32 offs_ = (*(u8 *)(ptr) == 0x0f) ? 2 : 1; \
  420. EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
  421. } while (0)
  422. #define emith_jump_at(ptr, target) { \
  423. u32 disp_ = (u32)(target) - ((u32)(ptr) + 5); \
  424. EMIT_PTR(ptr, 0xe9, u8); \
  425. EMIT_PTR((u8 *)(ptr) + 1, disp_, u32); \
  426. }
  427. #define emith_call(ptr) { \
  428. u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
  429. EMIT_OP(0xe8); \
  430. EMIT(disp, u32); \
  431. }
  432. #define emith_call_cond(cond, ptr) \
  433. emith_call(ptr)
  434. #define emith_call_reg(r) \
  435. EMIT_OP_MODRM(0xff, 3, 2, r)
  436. #define emith_call_ctx(offs) { \
  437. EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
  438. EMIT(offs, u32); \
  439. }
  440. #define emith_ret() \
  441. EMIT_OP(0xc3)
  442. #define emith_jump_reg(r) \
  443. EMIT_OP_MODRM(0xff, 3, 4, r)
  444. #define emith_jump_ctx(offs) { \
  445. EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
  446. EMIT(offs, u32); \
  447. }
  448. #define emith_push_ret()
  449. #define emith_pop_and_ret() \
  450. emith_ret()
  451. #define EMITH_JMP_START(cond) { \
  452. u8 *cond_ptr; \
  453. JMP8_POS(cond_ptr)
  454. #define EMITH_JMP_END(cond) \
  455. JMP8_EMIT(cond, cond_ptr); \
  456. }
  457. #define EMITH_JMP3_START(cond) { \
  458. u8 *cond_ptr, *else_ptr; \
  459. JMP8_POS(cond_ptr)
  460. #define EMITH_JMP3_MID(cond) \
  461. JMP8_POS(else_ptr); \
  462. JMP8_EMIT(cond, cond_ptr);
  463. #define EMITH_JMP3_END() \
  464. JMP8_EMIT_NC(else_ptr); \
  465. }
  466. // "simple" jump (no more then a few insns)
  467. // ARM will use conditional instructions here
  468. #define EMITH_SJMP_START EMITH_JMP_START
  469. #define EMITH_SJMP_END EMITH_JMP_END
  470. #define EMITH_SJMP3_START EMITH_JMP3_START
  471. #define EMITH_SJMP3_MID EMITH_JMP3_MID
  472. #define EMITH_SJMP3_END EMITH_JMP3_END
  473. #define emith_pass_arg_r(arg, reg) { \
  474. int rd = 7; \
  475. host_arg2reg(rd, arg); \
  476. emith_move_r_r(rd, reg); \
  477. }
  478. #define emith_pass_arg_imm(arg, imm) { \
  479. int rd = 7; \
  480. host_arg2reg(rd, arg); \
  481. emith_move_r_imm(rd, imm); \
  482. }
  483. #define host_instructions_updated(base, end)
  484. #define host_arg2reg(rd, arg) \
  485. switch (arg) { \
  486. case 0: rd = xAX; break; \
  487. case 1: rd = xDX; break; \
  488. case 2: rd = xCX; break; \
  489. }
  490. /* SH2 drc specific */
  491. #define emith_sh2_drc_entry() { \
  492. emith_push(xBX); \
  493. emith_push(xBP); \
  494. emith_push(xSI); \
  495. emith_push(xDI); \
  496. }
  497. #define emith_sh2_drc_exit() { \
  498. emith_pop(xDI); \
  499. emith_pop(xSI); \
  500. emith_pop(xBP); \
  501. emith_pop(xBX); \
  502. emith_ret(); \
  503. }
  504. // assumes EBX is free temporary
  505. #define emith_sh2_wcall(a, tab, ret_ptr) { \
  506. int arg2_; \
  507. host_arg2reg(arg2_, 2); \
  508. emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
  509. EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
  510. EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
  511. emith_ctx_read(arg2_, offsetof(SH2, is_slave)); \
  512. emith_push_imm((long)(ret_ptr)); \
  513. emith_jump_reg(xBX); \
  514. }
  515. #define emith_sh2_dtbf_loop() { \
  516. u8 *jmp0; /* negative cycles check */ \
  517. u8 *jmp1; /* unsinged overflow check */ \
  518. int cr, rn; \
  519. int tmp_ = rcache_get_tmp(); \
  520. cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
  521. rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
  522. emith_sub_r_imm(rn, 1); \
  523. emith_sub_r_imm(cr, (cycles+1) << 12); \
  524. cycles = 0; \
  525. emith_asr(tmp_, cr, 2+12); \
  526. JMP8_POS(jmp0); /* no negative cycles */ \
  527. emith_move_r_imm(tmp_, 0); \
  528. JMP8_EMIT(ICOND_JNS, jmp0); \
  529. emith_and_r_imm(cr, 0xffe); \
  530. emith_subf_r_r(rn, tmp_); \
  531. JMP8_POS(jmp1); /* no overflow */ \
  532. emith_neg_r(rn); /* count left */ \
  533. emith_lsl(rn, rn, 2+12); \
  534. emith_or_r_r(cr, rn); \
  535. emith_or_r_imm(cr, 1); \
  536. emith_move_r_imm(rn, 0); \
  537. JMP8_EMIT(ICOND_JA, jmp1); \
  538. rcache_free_tmp(tmp_); \
  539. }
  540. #define emith_write_sr(sr, srcr) { \
  541. int tmp_ = rcache_get_tmp(); \
  542. emith_clear_msb(tmp_, srcr, 22); \
  543. emith_bic_r_imm(sr, 0x3ff); \
  544. emith_or_r_r(sr, tmp_); \
  545. rcache_free_tmp(tmp_); \
  546. }
  547. #define emith_tpop_carry(sr, is_sub) \
  548. emith_lsr(sr, sr, 1)
  549. #define emith_tpush_carry(sr, is_sub) \
  550. emith_adc_r_r(sr, sr)
  551. /*
  552. * if Q
  553. * t = carry(Rn += Rm)
  554. * else
  555. * t = carry(Rn -= Rm)
  556. * T ^= t
  557. */
  558. #define emith_sh2_div1_step(rn, rm, sr) { \
  559. u8 *jmp0, *jmp1; \
  560. int tmp_ = rcache_get_tmp(); \
  561. emith_eor_r_r(tmp_, tmp_); \
  562. emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
  563. JMP8_POS(jmp0); /* je do_sub */ \
  564. emith_add_r_r(rn, rm); \
  565. JMP8_POS(jmp1); /* jmp done */ \
  566. JMP8_EMIT(ICOND_JE, jmp0); /* do_sub: */ \
  567. emith_sub_r_r(rn, rm); \
  568. JMP8_EMIT_NC(jmp1); /* done: */ \
  569. emith_setc(tmp_); \
  570. EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
  571. rcache_free_tmp(tmp_); \
  572. }